vasilito/RedBear-OS
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

restore lost packages from 0.2.3 + fix overwritten 0.2.4 files

Browse Source 
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.)
- Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber)
- Restore 20+ local/scripts (audit, lint, test, build helpers)
- Restore src/cook/scheduler.rs, status.rs, gnu-config/
- Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh
- Recover TLC source from HEAD (was overwritten by 0.2.3 checkout)
- Recover 11 local/docs plans from HEAD (were overwritten)
- Recover qt6-wayland-smoke symlink from HEAD
- Fix MOTD: remove garbled ASCII art, use clean text
- Update version: 0.2.0 -> 0.2.4 in os-release, motd, config
- Reduce filesystem_size: 1536 -> 512 MiB
- Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages
- Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
vasilito
2026-06-19 12:39:14 +03:00
parent ffbe098ef8
commit dc68054305
6418 changed files with 7066233 additions and 8670 deletions
Download Patch File Download Diff File Expand all files Collapse all files
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/ata.h
+30
View File
@@ -0,0 +1,30 @@
/*
* Header for Bestcomm ATA task driver
*
*
* Copyright (C) 2006 Freescale - John Rigby
* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __BESTCOMM_ATA_H__
#define __BESTCOMM_ATA_H__
struct bcom_ata_bd {
u32 status;
u32 src_pa;
u32 dst_pa;
};
extern struct bcom_task * bcom_ata_init(int queue_len, int maxbufsize);
extern void bcom_ata_rx_prepare(struct bcom_task *tsk);
extern void bcom_ata_tx_prepare(struct bcom_task *tsk);
extern void bcom_ata_reset_bd(struct bcom_task *tsk);
extern void bcom_ata_release(struct bcom_task *tsk);
#endif /* __BESTCOMM_ATA_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/bestcomm.h
+213
View File
@@ -0,0 +1,213 @@
/*
* Public header for the MPC52xx processor BestComm driver
*
*
* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2005 Varma Electronics Oy,
* ( by Andrey Volkov <avolkov@varma-el.com> )
* Copyright (C) 2003-2004 MontaVista, Software, Inc.
* ( by Dale Farnsworth <dfarnsworth@mvista.com> )
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __BESTCOMM_H__
#define __BESTCOMM_H__
/**
* struct bcom_bd - Structure describing a generic BestComm buffer descriptor
* @status: The current status of this buffer. Exact meaning depends on the
* task type
* @data: An array of u32 extra data. Size of array is task dependent.
*
* Note: Don't dereference a bcom_bd pointer as an array. The size of the
* bcom_bd is variable. Use bcom_get_bd() instead.
*/
struct bcom_bd {
u32 status;
u32 data[]; /* variable payload size */
};
/* ======================================================================== */
/* Generic task management */
/* ======================================================================== */
/**
* struct bcom_task - Structure describing a loaded BestComm task
*
* This structure is never built by the driver it self. It's built and
* filled the intermediate layer of the BestComm API, the task dependent
* support code.
*
* Most likely you don't need to poke around inside this structure. The
* fields are exposed in the header just for the sake of inline functions
*/
struct bcom_task {
unsigned int tasknum;
unsigned int flags;
int irq;
struct bcom_bd *bd;
phys_addr_t bd_pa;
void **cookie;
unsigned short index;
unsigned short outdex;
unsigned int num_bd;
unsigned int bd_size;
void* priv;
};
#define BCOM_FLAGS_NONE 0x00000000ul
#define BCOM_FLAGS_ENABLE_TASK (1ul << 0)
/**
* bcom_enable - Enable a BestComm task
* @tsk: The BestComm task structure
*
* This function makes sure the given task is enabled and can be run
* by the BestComm engine as needed
*/
extern void bcom_enable(struct bcom_task *tsk);
/**
* bcom_disable - Disable a BestComm task
* @tsk: The BestComm task structure
*
* This function disable a given task, making sure it's not executed
* by the BestComm engine.
*/
extern void bcom_disable(struct bcom_task *tsk);
/**
* bcom_get_task_irq - Returns the irq number of a BestComm task
* @tsk: The BestComm task structure
*/
static inline int
bcom_get_task_irq(struct bcom_task *tsk) {
return tsk->irq;
}
/* ======================================================================== */
/* BD based tasks helpers */
/* ======================================================================== */
#define BCOM_BD_READY 0x40000000ul
/** _bcom_next_index - Get next input index.
* @tsk: pointer to task structure
*
* Support function; Device drivers should not call this
*/
static inline int
_bcom_next_index(struct bcom_task *tsk)
{
return ((tsk->index + 1) == tsk->num_bd) ? 0 : tsk->index + 1;
}
/** _bcom_next_outdex - Get next output index.
* @tsk: pointer to task structure
*
* Support function; Device drivers should not call this
*/
static inline int
_bcom_next_outdex(struct bcom_task *tsk)
{
return ((tsk->outdex + 1) == tsk->num_bd) ? 0 : tsk->outdex + 1;
}
/**
* bcom_queue_empty - Checks if a BestComm task BD queue is empty
* @tsk: The BestComm task structure
*/
static inline int
bcom_queue_empty(struct bcom_task *tsk)
{
return tsk->index == tsk->outdex;
}
/**
* bcom_queue_full - Checks if a BestComm task BD queue is full
* @tsk: The BestComm task structure
*/
static inline int
bcom_queue_full(struct bcom_task *tsk)
{
return tsk->outdex == _bcom_next_index(tsk);
}
/**
* bcom_get_bd - Get a BD from the queue
* @tsk: The BestComm task structure
* index: Index of the BD to fetch
*/
static inline struct bcom_bd
*bcom_get_bd(struct bcom_task *tsk, unsigned int index)
{
/* A cast to (void*) so the address can be incremented by the
* real size instead of by sizeof(struct bcom_bd) */
return ((void *)tsk->bd) + (index * tsk->bd_size);
}
/**
* bcom_buffer_done - Checks if a BestComm
* @tsk: The BestComm task structure
*/
static inline int
bcom_buffer_done(struct bcom_task *tsk)
{
struct bcom_bd *bd;
if (bcom_queue_empty(tsk))
return 0;
bd = bcom_get_bd(tsk, tsk->outdex);
return !(bd->status & BCOM_BD_READY);
}
/**
* bcom_prepare_next_buffer - clear status of next available buffer.
* @tsk: The BestComm task structure
*
* Returns pointer to next buffer descriptor
*/
static inline struct bcom_bd *
bcom_prepare_next_buffer(struct bcom_task *tsk)
{
struct bcom_bd *bd;
bd = bcom_get_bd(tsk, tsk->index);
bd->status = 0; /* cleanup last status */
return bd;
}
static inline void
bcom_submit_next_buffer(struct bcom_task *tsk, void *cookie)
{
struct bcom_bd *bd = bcom_get_bd(tsk, tsk->index);
tsk->cookie[tsk->index] = cookie;
mb(); /* ensure the bd is really up-to-date */
bd->status |= BCOM_BD_READY;
tsk->index = _bcom_next_index(tsk);
if (tsk->flags & BCOM_FLAGS_ENABLE_TASK)
bcom_enable(tsk);
}
static inline void *
bcom_retrieve_buffer(struct bcom_task *tsk, u32 *p_status, struct bcom_bd **p_bd)
{
void *cookie = tsk->cookie[tsk->outdex];
struct bcom_bd *bd = bcom_get_bd(tsk, tsk->outdex);
if (p_status)
*p_status = bd->status;
if (p_bd)
*p_bd = bd;
tsk->outdex = _bcom_next_outdex(tsk);
return cookie;
}
#endif /* __BESTCOMM_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/bestcomm_priv.h
+350
View File
@@ -0,0 +1,350 @@
/*
* Private header for the MPC52xx processor BestComm driver
*
* By private, we mean that driver should not use it directly. It's meant
* to be used by the BestComm engine driver itself and by the intermediate
* layer between the core and the drivers.
*
* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2005 Varma Electronics Oy,
* ( by Andrey Volkov <avolkov@varma-el.com> )
* Copyright (C) 2003-2004 MontaVista, Software, Inc.
* ( by Dale Farnsworth <dfarnsworth@mvista.com> )
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __BESTCOMM_PRIV_H__
#define __BESTCOMM_PRIV_H__
#include <linux/spinlock.h>
#include <linux/of.h>
#include <asm/io.h>
#include <asm/mpc52xx.h>
#include "sram.h"
/* ======================================================================== */
/* Engine related stuff */
/* ======================================================================== */
/* Zones sizes and needed alignments */
#define BCOM_MAX_TASKS 16
#define BCOM_MAX_VAR 24
#define BCOM_MAX_INC 8
#define BCOM_MAX_FDT 64
#define BCOM_MAX_CTX 20
#define BCOM_CTX_SIZE (BCOM_MAX_CTX * sizeof(u32))
#define BCOM_CTX_ALIGN 0x100
#define BCOM_VAR_SIZE (BCOM_MAX_VAR * sizeof(u32))
#define BCOM_INC_SIZE (BCOM_MAX_INC * sizeof(u32))
#define BCOM_VAR_ALIGN 0x80
#define BCOM_FDT_SIZE (BCOM_MAX_FDT * sizeof(u32))
#define BCOM_FDT_ALIGN 0x100
/**
* struct bcom_tdt - Task Descriptor Table Entry
*
*/
struct bcom_tdt {
u32 start;
u32 stop;
u32 var;
u32 fdt;
u32 exec_status; /* used internally by BestComm engine */
u32 mvtp; /* used internally by BestComm engine */
u32 context;
u32 litbase;
};
/**
* struct bcom_engine
*
* This holds all info needed globaly to handle the engine
*/
struct bcom_engine {
struct device_node *ofnode;
struct mpc52xx_sdma __iomem *regs;
phys_addr_t regs_base;
struct bcom_tdt *tdt;
u32 *ctx;
u32 *var;
u32 *fdt;
spinlock_t lock;
};
extern struct bcom_engine *bcom_eng;
/* ======================================================================== */
/* Tasks related stuff */
/* ======================================================================== */
/* Tasks image header */
#define BCOM_TASK_MAGIC 0x4243544B /* 'BCTK' */
struct bcom_task_header {
u32 magic;
u8 desc_size; /* the size fields */
u8 var_size; /* are given in number */
u8 inc_size; /* of 32-bits words */
u8 first_var;
u8 reserved[8];
};
/* Descriptors structure & co */
#define BCOM_DESC_NOP 0x000001f8
#define BCOM_LCD_MASK 0x80000000
#define BCOM_DRD_EXTENDED 0x40000000
#define BCOM_DRD_INITIATOR_SHIFT 21
/* Tasks pragma */
#define BCOM_PRAGMA_BIT_RSV 7 /* reserved pragma bit */
#define BCOM_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, */
/* 1=iter end */
#define BCOM_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on */
/* task enable */
#define BCOM_PRAGMA_BIT_PACK 4 /* pack data enable */
#define BCOM_PRAGMA_BIT_INTEGER 3 /* data alignment */
/* 0=frac(msb), 1=int(lsb) */
#define BCOM_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read */
#define BCOM_PRAGMA_BIT_CW 1 /* write line buffer enable */
#define BCOM_PRAGMA_BIT_RL 0 /* read line buffer enable */
/* Looks like XLB speculative read generates XLB errors when a buffer
* is at the end of the physical memory. i.e. when accessing the
* lasts words, the engine tries to prefetch the next but there is no
* next ...
*/
#define BCOM_STD_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \
(0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
(0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \
(0 << BCOM_PRAGMA_BIT_PACK) | \
(0 << BCOM_PRAGMA_BIT_INTEGER) | \
(0 << BCOM_PRAGMA_BIT_SPECREAD) | \
(1 << BCOM_PRAGMA_BIT_CW) | \
(1 << BCOM_PRAGMA_BIT_RL))
#define BCOM_PCI_PRAGMA ((0 << BCOM_PRAGMA_BIT_RSV) | \
(0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
(0 << BCOM_PRAGMA_BIT_RST_ERROR_NO) | \
(0 << BCOM_PRAGMA_BIT_PACK) | \
(1 << BCOM_PRAGMA_BIT_INTEGER) | \
(0 << BCOM_PRAGMA_BIT_SPECREAD) | \
(1 << BCOM_PRAGMA_BIT_CW) | \
(1 << BCOM_PRAGMA_BIT_RL))
#define BCOM_ATA_PRAGMA BCOM_STD_PRAGMA
#define BCOM_CRC16_DP_0_PRAGMA BCOM_STD_PRAGMA
#define BCOM_CRC16_DP_1_PRAGMA BCOM_STD_PRAGMA
#define BCOM_FEC_RX_BD_PRAGMA BCOM_STD_PRAGMA
#define BCOM_FEC_TX_BD_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_0_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_1_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_2_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_3_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_BD_0_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_DP_BD_1_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_RX_BD_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_TX_BD_PRAGMA BCOM_STD_PRAGMA
#define BCOM_GEN_LPC_PRAGMA BCOM_STD_PRAGMA
#define BCOM_PCI_RX_PRAGMA BCOM_PCI_PRAGMA
#define BCOM_PCI_TX_PRAGMA BCOM_PCI_PRAGMA
/* Initiators number */
#define BCOM_INITIATOR_ALWAYS 0
#define BCOM_INITIATOR_SCTMR_0 1
#define BCOM_INITIATOR_SCTMR_1 2
#define BCOM_INITIATOR_FEC_RX 3
#define BCOM_INITIATOR_FEC_TX 4
#define BCOM_INITIATOR_ATA_RX 5
#define BCOM_INITIATOR_ATA_TX 6
#define BCOM_INITIATOR_SCPCI_RX 7
#define BCOM_INITIATOR_SCPCI_TX 8
#define BCOM_INITIATOR_PSC3_RX 9
#define BCOM_INITIATOR_PSC3_TX 10
#define BCOM_INITIATOR_PSC2_RX 11
#define BCOM_INITIATOR_PSC2_TX 12
#define BCOM_INITIATOR_PSC1_RX 13
#define BCOM_INITIATOR_PSC1_TX 14
#define BCOM_INITIATOR_SCTMR_2 15
#define BCOM_INITIATOR_SCLPC 16
#define BCOM_INITIATOR_PSC5_RX 17
#define BCOM_INITIATOR_PSC5_TX 18
#define BCOM_INITIATOR_PSC4_RX 19
#define BCOM_INITIATOR_PSC4_TX 20
#define BCOM_INITIATOR_I2C2_RX 21
#define BCOM_INITIATOR_I2C2_TX 22
#define BCOM_INITIATOR_I2C1_RX 23
#define BCOM_INITIATOR_I2C1_TX 24
#define BCOM_INITIATOR_PSC6_RX 25
#define BCOM_INITIATOR_PSC6_TX 26
#define BCOM_INITIATOR_IRDA_RX 25
#define BCOM_INITIATOR_IRDA_TX 26
#define BCOM_INITIATOR_SCTMR_3 27
#define BCOM_INITIATOR_SCTMR_4 28
#define BCOM_INITIATOR_SCTMR_5 29
#define BCOM_INITIATOR_SCTMR_6 30
#define BCOM_INITIATOR_SCTMR_7 31
/* Initiators priorities */
#define BCOM_IPR_ALWAYS 7
#define BCOM_IPR_SCTMR_0 2
#define BCOM_IPR_SCTMR_1 2
#define BCOM_IPR_FEC_RX 6
#define BCOM_IPR_FEC_TX 5
#define BCOM_IPR_ATA_RX 7
#define BCOM_IPR_ATA_TX 7
#define BCOM_IPR_SCPCI_RX 2
#define BCOM_IPR_SCPCI_TX 2
#define BCOM_IPR_PSC3_RX 2
#define BCOM_IPR_PSC3_TX 2
#define BCOM_IPR_PSC2_RX 2
#define BCOM_IPR_PSC2_TX 2
#define BCOM_IPR_PSC1_RX 2
#define BCOM_IPR_PSC1_TX 2
#define BCOM_IPR_SCTMR_2 2
#define BCOM_IPR_SCLPC 2
#define BCOM_IPR_PSC5_RX 2
#define BCOM_IPR_PSC5_TX 2
#define BCOM_IPR_PSC4_RX 2
#define BCOM_IPR_PSC4_TX 2
#define BCOM_IPR_I2C2_RX 2
#define BCOM_IPR_I2C2_TX 2
#define BCOM_IPR_I2C1_RX 2
#define BCOM_IPR_I2C1_TX 2
#define BCOM_IPR_PSC6_RX 2
#define BCOM_IPR_PSC6_TX 2
#define BCOM_IPR_IRDA_RX 2
#define BCOM_IPR_IRDA_TX 2
#define BCOM_IPR_SCTMR_3 2
#define BCOM_IPR_SCTMR_4 2
#define BCOM_IPR_SCTMR_5 2
#define BCOM_IPR_SCTMR_6 2
#define BCOM_IPR_SCTMR_7 2
/* ======================================================================== */
/* API */
/* ======================================================================== */
extern struct bcom_task *bcom_task_alloc(int bd_count, int bd_size, int priv_size);
extern void bcom_task_free(struct bcom_task *tsk);
extern int bcom_load_image(int task, u32 *task_image);
extern void bcom_set_initiator(int task, int initiator);
#define TASK_ENABLE 0x8000
/**
* bcom_disable_prefetch - Hook to disable bus prefetching
*
* ATA DMA and the original MPC5200 need this due to silicon bugs. At the
* moment disabling prefetch is a one-way street. There is no mechanism
* in place to turn prefetch back on after it has been disabled. There is
* no reason it couldn't be done, it would just be more complex to implement.
*/
static inline void bcom_disable_prefetch(void)
{
u16 regval;
regval = in_be16(&bcom_eng->regs->PtdCntrl);
out_be16(&bcom_eng->regs->PtdCntrl, regval | 1);
};
static inline void
bcom_enable_task(int task)
{
u16 reg;
reg = in_be16(&bcom_eng->regs->tcr[task]);
out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE);
}
static inline void
bcom_disable_task(int task)
{
u16 reg = in_be16(&bcom_eng->regs->tcr[task]);
out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE);
}
static inline u32 *
bcom_task_desc(int task)
{
return bcom_sram_pa2va(bcom_eng->tdt[task].start);
}
static inline int
bcom_task_num_descs(int task)
{
return (bcom_eng->tdt[task].stop - bcom_eng->tdt[task].start)/sizeof(u32) + 1;
}
static inline u32 *
bcom_task_var(int task)
{
return bcom_sram_pa2va(bcom_eng->tdt[task].var);
}
static inline u32 *
bcom_task_inc(int task)
{
return &bcom_task_var(task)[BCOM_MAX_VAR];
}
static inline int
bcom_drd_is_extended(u32 desc)
{
return (desc) & BCOM_DRD_EXTENDED;
}
static inline int
bcom_desc_is_drd(u32 desc)
{
return !(desc & BCOM_LCD_MASK) && desc != BCOM_DESC_NOP;
}
static inline int
bcom_desc_initiator(u32 desc)
{
return (desc >> BCOM_DRD_INITIATOR_SHIFT) & 0x1f;
}
static inline void
bcom_set_desc_initiator(u32 *desc, int initiator)
{
*desc = (*desc & ~(0x1f << BCOM_DRD_INITIATOR_SHIFT)) |
((initiator & 0x1f) << BCOM_DRD_INITIATOR_SHIFT);
}
static inline void
bcom_set_task_pragma(int task, int pragma)
{
u32 *fdt = &bcom_eng->tdt[task].fdt;
*fdt = (*fdt & ~0xff) | pragma;
}
static inline void
bcom_set_task_auto_start(int task, int next_task)
{
u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task);
}
static inline void
bcom_set_tcr_initiator(int task, int initiator)
{
u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8));
}
#endif /* __BESTCOMM_PRIV_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/fec.h
+61
View File
@@ -0,0 +1,61 @@
/*
* Header for Bestcomm FEC tasks driver
*
*
* Copyright (C) 2006-2007 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003-2004 MontaVista, Software, Inc.
* ( by Dale Farnsworth <dfarnsworth@mvista.com> )
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __BESTCOMM_FEC_H__
#define __BESTCOMM_FEC_H__
struct bcom_fec_bd {
u32 status;
u32 skb_pa;
};
#define BCOM_FEC_TX_BD_TFD 0x08000000ul /* transmit frame done */
#define BCOM_FEC_TX_BD_TC 0x04000000ul /* transmit CRC */
#define BCOM_FEC_TX_BD_ABC 0x02000000ul /* append bad CRC */
#define BCOM_FEC_RX_BD_L 0x08000000ul /* buffer is last in frame */
#define BCOM_FEC_RX_BD_BC 0x00800000ul /* DA is broadcast */
#define BCOM_FEC_RX_BD_MC 0x00400000ul /* DA is multicast and not broadcast */
#define BCOM_FEC_RX_BD_LG 0x00200000ul /* Rx frame length violation */
#define BCOM_FEC_RX_BD_NO 0x00100000ul /* Rx non-octet aligned frame */
#define BCOM_FEC_RX_BD_CR 0x00040000ul /* Rx CRC error */
#define BCOM_FEC_RX_BD_OV 0x00020000ul /* overrun */
#define BCOM_FEC_RX_BD_TR 0x00010000ul /* Rx frame truncated */
#define BCOM_FEC_RX_BD_LEN_MASK 0x000007fful /* mask for length of received frame */
#define BCOM_FEC_RX_BD_ERRORS (BCOM_FEC_RX_BD_LG | BCOM_FEC_RX_BD_NO | \
BCOM_FEC_RX_BD_CR | BCOM_FEC_RX_BD_OV | BCOM_FEC_RX_BD_TR)
extern struct bcom_task *
bcom_fec_rx_init(int queue_len, phys_addr_t fifo, int maxbufsize);
extern int
bcom_fec_rx_reset(struct bcom_task *tsk);
extern void
bcom_fec_rx_release(struct bcom_task *tsk);
extern struct bcom_task *
bcom_fec_tx_init(int queue_len, phys_addr_t fifo);
extern int
bcom_fec_tx_reset(struct bcom_task *tsk);
extern void
bcom_fec_tx_release(struct bcom_task *tsk);
#endif /* __BESTCOMM_FEC_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/gen_bd.h
+47
View File
@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header for Bestcomm General Buffer Descriptor tasks driver
*
* Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2006 AppSpec Computer Technologies Corp.
* Jeff Gibbons <jeff.gibbons@appspec.com>
*/
#ifndef __BESTCOMM_GEN_BD_H__
#define __BESTCOMM_GEN_BD_H__
struct bcom_gen_bd {
u32 status;
u32 buf_pa;
};
extern struct bcom_task *
bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo,
int initiator, int ipr, int maxbufsize);
extern int
bcom_gen_bd_rx_reset(struct bcom_task *tsk);
extern void
bcom_gen_bd_rx_release(struct bcom_task *tsk);
extern struct bcom_task *
bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo,
int initiator, int ipr);
extern int
bcom_gen_bd_tx_reset(struct bcom_task *tsk);
extern void
bcom_gen_bd_tx_release(struct bcom_task *tsk);
/* PSC support utility wrappers */
struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len,
phys_addr_t fifo, int maxbufsize);
struct bcom_task * bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len,
phys_addr_t fifo);
#endif /* __BESTCOMM_GEN_BD_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/bestcomm/sram.h
+54
View File
@@ -0,0 +1,54 @@
/*
* Handling of a sram zone for bestcomm
*
*
* Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __BESTCOMM_SRAM_H__
#define __BESTCOMM_SRAM_H__
#include <asm/rheap.h>
#include <asm/mmu.h>
#include <linux/spinlock.h>
/* Structure used internally */
/* The internals are here for the inline functions
* sake, certainly not for the user to mess with !
*/
struct bcom_sram {
phys_addr_t base_phys;
void *base_virt;
unsigned int size;
rh_info_t *rh;
spinlock_t lock;
};
extern struct bcom_sram *bcom_sram;
/* Public API */
extern int bcom_sram_init(struct device_node *sram_node, char *owner);
extern void bcom_sram_cleanup(void);
extern void* bcom_sram_alloc(int size, int align, phys_addr_t *phys);
extern void bcom_sram_free(void *ptr);
static inline phys_addr_t bcom_sram_va2pa(void *va) {
return bcom_sram->base_phys +
(unsigned long)(va - bcom_sram->base_virt);
}
static inline void *bcom_sram_pa2va(phys_addr_t pa) {
return bcom_sram->base_virt +
(unsigned long)(pa - bcom_sram->base_phys);
}
#endif /* __BESTCOMM_SRAM_H__ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/edac.h
+9
View File
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef FSL_EDAC_H
#define FSL_EDAC_H
struct mpc85xx_edac_pci_plat_data {
struct device_node *of_node;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/enetc_mdio.h
+68
View File
@@ -0,0 +1,68 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2019 NXP */
#ifndef _FSL_ENETC_MDIO_H_
#define _FSL_ENETC_MDIO_H_
#include <linux/phy.h>
/* PCS registers */
#define ENETC_PCS_LINK_TIMER1 0x12
#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
#define ENETC_PCS_LINK_TIMER2 0x13
#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
#define ENETC_PCS_IF_MODE 0x14
#define ENETC_PCS_IF_MODE_SGMII_EN BIT(0)
#define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1)
#define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2))
#define ENETC_PCS_IF_MODE_DUPLEX_HALF BIT(3)
/* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
* Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS
* still thinks it's at gigabit.
*/
enum enetc_pcs_speed {
ENETC_PCS_SPEED_10 = 0,
ENETC_PCS_SPEED_100 = 1,
ENETC_PCS_SPEED_1000 = 2,
ENETC_PCS_SPEED_2500 = 2,
};
struct enetc_hw;
struct enetc_mdio_priv {
struct enetc_hw *hw;
int mdio_base;
};
#if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO)
int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum);
int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum,
u16 value);
int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id, int devad, int regnum);
int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id, int devad, int regnum,
u16 value);
struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs);
#else
static inline int enetc_mdio_read_c22(struct mii_bus *bus, int phy_id,
int regnum)
{ return -EINVAL; }
static inline int enetc_mdio_write_c22(struct mii_bus *bus, int phy_id,
int regnum, u16 value)
{ return -EINVAL; }
static inline int enetc_mdio_read_c45(struct mii_bus *bus, int phy_id,
int devad, int regnum)
{ return -EINVAL; }
static inline int enetc_mdio_write_c45(struct mii_bus *bus, int phy_id,
int devad, int regnum, u16 value)
{ return -EINVAL; }
static inline struct enetc_hw *enetc_hw_alloc(struct device *dev,
void __iomem *port_regs)
{ return ERR_PTR(-EINVAL); }
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/ftm.h
+88
View File
@@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0
#ifndef __FSL_FTM_H__
#define __FSL_FTM_H__
#define FTM_SC 0x0 /* Status And Control */
#define FTM_CNT 0x4 /* Counter */
#define FTM_MOD 0x8 /* Modulo */
#define FTM_CNTIN 0x4C /* Counter Initial Value */
#define FTM_STATUS 0x50 /* Capture And Compare Status */
#define FTM_MODE 0x54 /* Features Mode Selection */
#define FTM_SYNC 0x58 /* Synchronization */
#define FTM_OUTINIT 0x5C /* Initial State For Channels Output */
#define FTM_OUTMASK 0x60 /* Output Mask */
#define FTM_COMBINE 0x64 /* Function For Linked Channels */
#define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */
#define FTM_EXTTRIG 0x6C /* FTM External Trigger */
#define FTM_POL 0x70 /* Channels Polarity */
#define FTM_FMS 0x74 /* Fault Mode Status */
#define FTM_FILTER 0x78 /* Input Capture Filter Control */
#define FTM_FLTCTRL 0x7C /* Fault Control */
#define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */
#define FTM_CONF 0x84 /* Configuration */
#define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */
#define FTM_SYNCONF 0x8C /* Synchronization Configuration */
#define FTM_INVCTRL 0x90 /* FTM Inverting Control */
#define FTM_SWOCTRL 0x94 /* FTM Software Output Control */
#define FTM_PWMLOAD 0x98 /* FTM PWM Load */
#define FTM_SC_CLK_MASK_SHIFT 3
#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
#define FTM_SC_TOF 0x80
#define FTM_SC_TOIE 0x40
#define FTM_SC_CPWMS 0x20
#define FTM_SC_CLKS 0x18
#define FTM_SC_PS_1 0x0
#define FTM_SC_PS_2 0x1
#define FTM_SC_PS_4 0x2
#define FTM_SC_PS_8 0x3
#define FTM_SC_PS_16 0x4
#define FTM_SC_PS_32 0x5
#define FTM_SC_PS_64 0x6
#define FTM_SC_PS_128 0x7
#define FTM_SC_PS_MASK 0x7
#define FTM_MODE_FAULTIE 0x80
#define FTM_MODE_FAULTM 0x60
#define FTM_MODE_CAPTEST 0x10
#define FTM_MODE_PWMSYNC 0x8
#define FTM_MODE_WPDIS 0x4
#define FTM_MODE_INIT 0x2
#define FTM_MODE_FTMEN 0x1
/* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally
* and these bits cannot be set. Flextimer cannot use Filter in
* Quadrature Decoder Mode.
* https://community.nxp.com/thread/467648#comment-1010319
*/
#define FTM_QDCTRL_PHAFLTREN 0x80
#define FTM_QDCTRL_PHBFLTREN 0x40
#define FTM_QDCTRL_PHAPOL 0x20
#define FTM_QDCTRL_PHBPOL 0x10
#define FTM_QDCTRL_QUADMODE 0x8
#define FTM_QDCTRL_QUADDIR 0x4
#define FTM_QDCTRL_TOFDIR 0x2
#define FTM_QDCTRL_QUADEN 0x1
#define FTM_FMS_FAULTF 0x80
#define FTM_FMS_WPEN 0x40
#define FTM_FMS_FAULTIN 0x10
#define FTM_FMS_FAULTF3 0x8
#define FTM_FMS_FAULTF2 0x4
#define FTM_FMS_FAULTF1 0x2
#define FTM_FMS_FAULTF0 0x1
#define FTM_CSC_BASE 0xC
#define FTM_CSC_MSB 0x20
#define FTM_CSC_MSA 0x10
#define FTM_CSC_ELSB 0x8
#define FTM_CSC_ELSA 0x4
#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
#define FTM_CV_BASE 0x10
#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
#define FTM_PS_MAX 7
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/guts.h
+321
View File
@@ -0,0 +1,321 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Freecale 85xx and 86xx Global Utilties register set
*
* Authors: Jeff Brown
* Timur Tabi <timur@freescale.com>
*
* Copyright 2004,2007,2012 Freescale Semiconductor, Inc
*/
#ifndef __FSL_GUTS_H__
#define __FSL_GUTS_H__
#include <linux/types.h>
#include <linux/io.h>
/*
* Global Utility Registers.
*
* Not all registers defined in this structure are available on all chips, so
* you are expected to know whether a given register actually exists on your
* chip before you access it.
*
* Also, some registers are similar on different chips but have slightly
* different names. In these cases, one name is chosen to avoid extraneous
* #ifdefs.
*/
struct ccsr_guts {
u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
* Control Register
*/
u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
u8 res018[0x20 - 0x18];
u32 porcir; /* 0x.0020 - POR Configuration Information
* Register
*/
u8 res024[0x30 - 0x24];
u32 gpiocr; /* 0x.0030 - GPIO Control Register */
u8 res034[0x40 - 0x34];
u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
* Register
*/
u8 res044[0x50 - 0x44];
u32 gpindr; /* 0x.0050 - General-Purpose Input Data
* Register
*/
u8 res054[0x60 - 0x54];
u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
* Multiplex Control
*/
u32 pmuxcr2; /* 0x.0064 - Alternate function signal
* multiplex control 2
*/
u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
u8 res06c[0x70 - 0x6c];
u32 devdisr; /* 0x.0070 - Device Disable Control */
#define CCSR_GUTS_DEVDISR_TB1 0x00001000
#define CCSR_GUTS_DEVDISR_TB0 0x00004000
u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
u8 res078[0x7c - 0x78];
u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
* Register
*/
u32 powmgtcsr; /* 0x.0080 - Power Management Status and
* Control Register
*/
u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
* Configuration Register
*/
u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
* Configuration Register
*/
u32 pmcdr; /* 0x.008c - 4Power management clock disable
* register
*/
u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
u32 rstrscr; /* 0x.0094 - Reset Request Status and
* Control Register
*/
u32 ectrstcr; /* 0x.0098 - Exception reset control register */
u32 autorstsr; /* 0x.009c - Automatic reset status register */
u32 pvr; /* 0x.00a0 - Processor Version Register */
u32 svr; /* 0x.00a4 - System Version Register */
u8 res0a8[0xb0 - 0xa8];
u32 rstcr; /* 0x.00b0 - Reset Control Register */
u8 res0b4[0xc0 - 0xb4];
u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
Called 'elbcvselcr' on 86xx SOCs */
u8 res0c4[0x100 - 0xc4];
u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
There are 16 registers */
u8 res140[0x224 - 0x140];
u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
u8 res22c[0x604 - 0x22c];
u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
u8 res608[0x800 - 0x608];
u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
u8 res804[0x900 - 0x804];
u32 ircr; /* 0x.0900 - Infrared Control Register */
u8 res904[0x908 - 0x904];
u32 dmacr; /* 0x.0908 - DMA Control Register */
u8 res90c[0x914 - 0x90c];
u32 elbccr; /* 0x.0914 - eLBC Control Register */
u8 res918[0xb20 - 0x918];
u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
u8 resb2c[0xe00 - 0xb2c];
u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
u8 rese04[0xe10 - 0xe04];
u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
u8 rese14[0xe20 - 0xe14];
u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
* register
*/
u8 rese28[0xf04 - 0xe28];
u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
u8 resf0c[0xf2c - 0xf0c];
u32 itcr; /* 0x.0f2c - Internal transaction control
* register
*/
u8 resf30[0xf40 - 0xf30];
u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
/*
* Set the DMACR register in the GUTS
*
* The DMACR register determines the source of initiated transfers for each
* channel on each DMA controller. Rather than have a bunch of repetitive
* macros for the bit patterns, we just have a function that calculates
* them.
*
* guts: Pointer to GUTS structure
* co: The DMA controller (0 or 1)
* ch: The channel on the DMA controller (0, 1, 2, or 3)
* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
*/
static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int device)
{
unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
}
#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
/*
* Set the DMA external control bits in the GUTS
*
* The DMA external control bits in the PMUXCR are only meaningful for
* channels 0 and 3. Any other channels are ignored.
*
* guts: Pointer to GUTS structure
* co: The DMA controller (0 or 1)
* ch: The channel on the DMA controller (0, 1, 2, or 3)
* value: the new value for the bit (0 or 1)
*/
static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
unsigned int co, unsigned int ch, unsigned int value)
{
if ((ch == 0) || (ch == 3)) {
unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
}
}
#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
(((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
#endif
struct ccsr_rcpm_v1 {
u8 res0000[4];
__be32 cdozsr; /* 0x0004 Core Doze Status Register */
u8 res0008[4];
__be32 cdozcr; /* 0x000c Core Doze Control Register */
u8 res0010[4];
__be32 cnapsr; /* 0x0014 Core Nap Status Register */
u8 res0018[4];
__be32 cnapcr; /* 0x001c Core Nap Control Register */
u8 res0020[4];
__be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
u8 res0028[4];
__be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
u8 res0030[4];
__be32 cwaitsr; /* 0x0034 Core Wait Status Register */
u8 res0038[4];
__be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
__be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
#define RCPM_POWMGTCSR_SLP 0x00020000
u8 res0044[12];
__be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
u8 res0054[16];
__be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
u8 res0068[4];
__be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
u8 res0070[4];
__be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
u8 res0078[4];
__be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
u8 res0080[4];
__be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
u8 res0088[4];
__be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
u8 res0090[4];
__be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
u8 res0098[4];
__be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */
};
struct ccsr_rcpm_v2 {
u8 res_00[12];
__be32 tph10sr0; /* Thread PH10 Status Register */
u8 res_10[12];
__be32 tph10setr0; /* Thread PH10 Set Control Register */
u8 res_20[12];
__be32 tph10clrr0; /* Thread PH10 Clear Control Register */
u8 res_30[12];
__be32 tph10psr0; /* Thread PH10 Previous Status Register */
u8 res_40[12];
__be32 twaitsr0; /* Thread Wait Status Register */
u8 res_50[96];
__be32 pcph15sr; /* Physical Core PH15 Status Register */
__be32 pcph15setr; /* Physical Core PH15 Set Control Register */
__be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
__be32 pcph15psr; /* Physical Core PH15 Prev Status Register */
u8 res_c0[16];
__be32 pcph20sr; /* Physical Core PH20 Status Register */
__be32 pcph20setr; /* Physical Core PH20 Set Control Register */
__be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
__be32 pcph20psr; /* Physical Core PH20 Prev Status Register */
__be32 pcpw20sr; /* Physical Core PW20 Status Register */
u8 res_e0[12];
__be32 pcph30sr; /* Physical Core PH30 Status Register */
__be32 pcph30setr; /* Physical Core PH30 Set Control Register */
__be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
__be32 pcph30psr; /* Physical Core PH30 Prev Status Register */
u8 res_100[32];
__be32 ippwrgatecr; /* IP Power Gating Control Register */
u8 res_124[12];
__be32 powmgtcsr; /* Power Management Control & Status Reg */
#define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
u8 res_134[12];
__be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
u8 res_150[12];
__be32 tpmimr0; /* Thread PM Interrupt Mask Reg */
u8 res_160[12];
__be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
u8 res_170[12];
__be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
u8 res_180[12];
__be32 tpmnmimr0; /* Thread PM NMI Mask Reg */
u8 res_190[12];
__be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
__be32 pctbenr; /* Physical Core Time Base Enable Reg */
__be32 pctbclkselr; /* Physical Core Time Base Clock Select */
__be32 tbclkdivr; /* Time Base Clock Divider Register */
u8 res_1ac[4];
__be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
__be32 clpcl10sr; /* Cluster PCL10 Status Register */
__be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
__be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
__be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
__be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
__be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
__be32 cdpwroksetr; /* Core Domain Power OK Set Register */
__be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
__be32 cdpwrensr; /* Core Domain Power Enable Status Register */
__be32 cddslsr; /* Core Domain Deep Sleep Status Register */
u8 res_1e8[8];
__be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
u8 res_300[3568];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/mc.h
+677
View File
@@ -0,0 +1,677 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Freescale Management Complex (MC) bus public interface
*
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2019-2020 NXP
* Author: German Rivera <German.Rivera@freescale.com>
*
*/
#ifndef _FSL_MC_H_
#define _FSL_MC_H_
#include <linux/device.h>
#include <linux/mod_devicetable.h>
#include <linux/interrupt.h>
#include <uapi/linux/fsl_mc.h>
#define FSL_MC_VENDOR_FREESCALE 0x1957
struct irq_domain;
struct msi_domain_info;
struct fsl_mc_device;
struct fsl_mc_io;
/**
* struct fsl_mc_driver - MC object device driver object
* @driver: Generic device driver
* @match_id_table: table of supported device matching Ids
* @probe: Function called when a device is added
* @remove: Function called when a device is removed
* @shutdown: Function called at shutdown time to quiesce the device
* @suspend: Function called when a device is stopped
* @resume: Function called when a device is resumed
* @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
* For most device drivers, no need to care about this flag
* as long as all DMAs are handled through the kernel DMA API.
* For some special ones, for example VFIO drivers, they know
* how to manage the DMA themselves and set this flag so that
* the IOMMU layer will allow them to setup and manage their
* own I/O address space.
*
* Generic DPAA device driver object for device drivers that are registered
* with a DPRC bus. This structure is to be embedded in each device-specific
* driver structure.
*/
struct fsl_mc_driver {
struct device_driver driver;
const struct fsl_mc_device_id *match_id_table;
int (*probe)(struct fsl_mc_device *dev);
void (*remove)(struct fsl_mc_device *dev);
void (*shutdown)(struct fsl_mc_device *dev);
int (*suspend)(struct fsl_mc_device *dev, pm_message_t state);
int (*resume)(struct fsl_mc_device *dev);
bool driver_managed_dma;
};
#define to_fsl_mc_driver(_drv) \
container_of_const(_drv, struct fsl_mc_driver, driver)
/**
* enum fsl_mc_pool_type - Types of allocatable MC bus resources
*
* Entries in these enum are used as indices in the array of resource
* pools of an fsl_mc_bus object.
*/
enum fsl_mc_pool_type {
FSL_MC_POOL_DPMCP = 0x0, /* corresponds to "dpmcp" in the MC */
FSL_MC_POOL_DPBP, /* corresponds to "dpbp" in the MC */
FSL_MC_POOL_DPCON, /* corresponds to "dpcon" in the MC */
FSL_MC_POOL_IRQ,
/*
* NOTE: New resource pool types must be added before this entry
*/
FSL_MC_NUM_POOL_TYPES
};
/**
* struct fsl_mc_resource - MC generic resource
* @type: type of resource
* @id: unique MC resource Id within the resources of the same type
* @data: pointer to resource-specific data if the resource is currently
* allocated, or NULL if the resource is not currently allocated.
* @parent_pool: pointer to the parent resource pool from which this
* resource is allocated from.
* @node: Node in the free list of the corresponding resource pool
*
* NOTE: This structure is to be embedded as a field of specific
* MC resource structures.
*/
struct fsl_mc_resource {
enum fsl_mc_pool_type type;
s32 id;
void *data;
struct fsl_mc_resource_pool *parent_pool;
struct list_head node;
};
/**
* struct fsl_mc_device_irq - MC object device message-based interrupt
* @virq: Linux virtual interrupt number
* @mc_dev: MC object device that owns this interrupt
* @dev_irq_index: device-relative IRQ index
* @resource: MC generic resource associated with the interrupt
*/
struct fsl_mc_device_irq {
unsigned int virq;
struct fsl_mc_device *mc_dev;
u8 dev_irq_index;
struct fsl_mc_resource resource;
};
#define to_fsl_mc_irq(_mc_resource) \
container_of(_mc_resource, struct fsl_mc_device_irq, resource)
/* Opened state - Indicates that an object is open by at least one owner */
#define FSL_MC_OBJ_STATE_OPEN 0x00000001
/* Plugged state - Indicates that the object is plugged */
#define FSL_MC_OBJ_STATE_PLUGGED 0x00000002
/**
* Shareability flag - Object flag indicating no memory shareability.
* the object generates memory accesses that are non coherent with other
* masters;
* user is responsible for proper memory handling through IOMMU configuration.
*/
#define FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
/**
* struct fsl_mc_obj_desc - Object descriptor
* @type: Type of object: NULL terminated string
* @id: ID of logical object resource
* @vendor: Object vendor identifier
* @ver_major: Major version number
* @ver_minor: Minor version number
* @irq_count: Number of interrupts supported by the object
* @region_count: Number of mappable regions supported by the object
* @state: Object state: combination of FSL_MC_OBJ_STATE_ states
* @label: Object label: NULL terminated string
* @flags: Object's flags
*/
struct fsl_mc_obj_desc {
char type[16];
int id;
u16 vendor;
u16 ver_major;
u16 ver_minor;
u8 irq_count;
u8 region_count;
u32 state;
char label[16];
u16 flags;
};
/**
* Bit masks for a MC object device (struct fsl_mc_device) flags
*/
#define FSL_MC_IS_DPRC 0x0001
/* Region flags */
/* Indicates that region can be mapped as cacheable */
#define FSL_MC_REGION_CACHEABLE 0x00000001
/* Indicates that region can be mapped as shareable */
#define FSL_MC_REGION_SHAREABLE 0x00000002
/**
* struct fsl_mc_device - MC object device object
* @dev: Linux driver model device object
* @dma_mask: Default DMA mask
* @flags: MC object device flags
* @icid: Isolation context ID for the device
* @mc_handle: MC handle for the corresponding MC object opened
* @mc_io: Pointer to MC IO object assigned to this device or
* NULL if none.
* @obj_desc: MC description of the DPAA device
* @regions: pointer to array of MMIO region entries
* @irqs: pointer to array of pointers to interrupts allocated to this device
* @resource: generic resource associated with this MC object device, if any.
*
* Generic device object for MC object devices that are "attached" to a
* MC bus.
*
* NOTES:
* - For a non-DPRC object its icid is the same as its parent DPRC's icid.
* - The SMMU notifier callback gets invoked after device_add() has been
* called for an MC object device, but before the device-specific probe
* callback gets called.
* - DP_OBJ_DPRC objects are the only MC objects that have built-in MC
* portals. For all other MC objects, their device drivers are responsible for
* allocating MC portals for them by calling fsl_mc_portal_allocate().
* - Some types of MC objects (e.g., DP_OBJ_DPBP, DP_OBJ_DPCON) are
* treated as resources that can be allocated/deallocated from the
* corresponding resource pool in the object's parent DPRC, using the
* fsl_mc_object_allocate()/fsl_mc_object_free() functions. These MC objects
* are known as "allocatable" objects. For them, the corresponding
* fsl_mc_device's 'resource' points to the associated resource object.
* For MC objects that are not allocatable (e.g., DP_OBJ_DPRC, DP_OBJ_DPNI),
* 'resource' is NULL.
*/
struct fsl_mc_device {
struct device dev;
u64 dma_mask;
u16 flags;
u32 icid;
u16 mc_handle;
struct fsl_mc_io *mc_io;
struct fsl_mc_obj_desc obj_desc;
struct resource *regions;
struct fsl_mc_device_irq **irqs;
struct fsl_mc_resource *resource;
struct device_link *consumer_link;
};
#define to_fsl_mc_device(_dev) \
container_of(_dev, struct fsl_mc_device, dev)
struct mc_cmd_header {
u8 src_id;
u8 flags_hw;
u8 status;
u8 flags_sw;
__le16 token;
__le16 cmd_id;
};
enum mc_cmd_status {
MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */
MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */
MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */
MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */
MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */
MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */
MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */
MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */
MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */
MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */
};
/*
* MC command flags
*/
/* High priority flag */
#define MC_CMD_FLAG_PRI 0x80
/* Command completion flag */
#define MC_CMD_FLAG_INTR_DIS 0x01
static inline __le64 mc_encode_cmd_header(u16 cmd_id,
u32 cmd_flags,
u16 token)
{
__le64 header = 0;
struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
hdr->cmd_id = cpu_to_le16(cmd_id);
hdr->token = cpu_to_le16(token);
hdr->status = MC_CMD_STATUS_READY;
if (cmd_flags & MC_CMD_FLAG_PRI)
hdr->flags_hw = MC_CMD_FLAG_PRI;
if (cmd_flags & MC_CMD_FLAG_INTR_DIS)
hdr->flags_sw = MC_CMD_FLAG_INTR_DIS;
return header;
}
static inline u16 mc_cmd_hdr_read_token(struct fsl_mc_command *cmd)
{
struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
u16 token = le16_to_cpu(hdr->token);
return token;
}
struct mc_rsp_create {
__le32 object_id;
};
struct mc_rsp_api_ver {
__le16 major_ver;
__le16 minor_ver;
};
static inline u32 mc_cmd_read_object_id(struct fsl_mc_command *cmd)
{
struct mc_rsp_create *rsp_params;
rsp_params = (struct mc_rsp_create *)cmd->params;
return le32_to_cpu(rsp_params->object_id);
}
static inline void mc_cmd_read_api_version(struct fsl_mc_command *cmd,
u16 *major_ver,
u16 *minor_ver)
{
struct mc_rsp_api_ver *rsp_params;
rsp_params = (struct mc_rsp_api_ver *)cmd->params;
*major_ver = le16_to_cpu(rsp_params->major_ver);
*minor_ver = le16_to_cpu(rsp_params->minor_ver);
}
/**
* Bit masks for a MC I/O object (struct fsl_mc_io) flags
*/
#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL 0x0001
/**
* struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command()
* @dev: device associated with this Mc I/O object
* @flags: flags for mc_send_command()
* @portal_size: MC command portal size in bytes
* @portal_phys_addr: MC command portal physical address
* @portal_virt_addr: MC command portal virtual address
* @dpmcp_dev: pointer to the DPMCP device associated with the MC portal.
*
* Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not
* set:
* @mutex: Mutex to serialize mc_send_command() calls that use the same MC
* portal, if the fsl_mc_io object was created with the
* FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this
* fsl_mc_io object must be made only from non-atomic context.
*
* Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is
* set:
* @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC
* portal, if the fsl_mc_io object was created with the
* FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this
* fsl_mc_io object can be made from atomic or non-atomic context.
*/
struct fsl_mc_io {
struct device *dev;
u16 flags;
u32 portal_size;
phys_addr_t portal_phys_addr;
void __iomem *portal_virt_addr;
struct fsl_mc_device *dpmcp_dev;
union {
/*
* This field is only meaningful if the
* FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set
*/
struct mutex mutex; /* serializes mc_send_command() */
/*
* This field is only meaningful if the
* FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set
*/
raw_spinlock_t spinlock; /* serializes mc_send_command() */
};
};
int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd);
#ifdef CONFIG_FSL_MC_BUS
#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type)
#else
/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */
#define dev_is_fsl_mc(_dev) (0)
#endif
/* Macro to check if a device is a container device */
#define fsl_mc_is_cont_dev(_dev) (to_fsl_mc_device(_dev)->flags & \
FSL_MC_IS_DPRC)
/* Macro to get the container device of a MC device */
#define fsl_mc_cont_dev(_dev) (fsl_mc_is_cont_dev(_dev) ? \
(_dev) : (_dev)->parent)
/*
* module_fsl_mc_driver() - Helper macro for drivers that don't do
* anything special in module init/exit. This eliminates a lot of
* boilerplate. Each module may only use this macro once, and
* calling it replaces module_init() and module_exit()
*/
#define module_fsl_mc_driver(__fsl_mc_driver) \
module_driver(__fsl_mc_driver, fsl_mc_driver_register, \
fsl_mc_driver_unregister)
/*
* Macro to avoid include chaining to get THIS_MODULE
*/
#define fsl_mc_driver_register(drv) \
__fsl_mc_driver_register(drv, THIS_MODULE)
int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
struct module *owner);
void fsl_mc_driver_unregister(struct fsl_mc_driver *driver);
/**
* struct fsl_mc_version
* @major: Major version number: incremented on API compatibility changes
* @minor: Minor version number: incremented on API additions (that are
* backward compatible); reset when major version is incremented
* @revision: Internal revision number: incremented on implementation changes
* and/or bug fixes that have no impact on API
*/
struct fsl_mc_version {
u32 major;
u32 minor;
u32 revision;
};
struct fsl_mc_version *fsl_mc_get_version(void);
int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev,
u16 mc_io_flags,
struct fsl_mc_io **new_mc_io);
void fsl_mc_portal_free(struct fsl_mc_io *mc_io);
int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev,
enum fsl_mc_pool_type pool_type,
struct fsl_mc_device **new_mc_adev);
void fsl_mc_object_free(struct fsl_mc_device *mc_adev);
struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
struct msi_domain_info *info,
struct irq_domain *parent);
int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev);
void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
struct fsl_mc_device *fsl_mc_get_endpoint(struct fsl_mc_device *mc_dev,
u16 if_id);
extern const struct bus_type fsl_mc_bus_type;
extern const struct device_type fsl_mc_bus_dprc_type;
extern const struct device_type fsl_mc_bus_dpni_type;
extern const struct device_type fsl_mc_bus_dpio_type;
extern const struct device_type fsl_mc_bus_dpsw_type;
extern const struct device_type fsl_mc_bus_dpbp_type;
extern const struct device_type fsl_mc_bus_dpcon_type;
extern const struct device_type fsl_mc_bus_dpmcp_type;
extern const struct device_type fsl_mc_bus_dpmac_type;
extern const struct device_type fsl_mc_bus_dprtc_type;
extern const struct device_type fsl_mc_bus_dpseci_type;
extern const struct device_type fsl_mc_bus_dpdmux_type;
extern const struct device_type fsl_mc_bus_dpdcei_type;
extern const struct device_type fsl_mc_bus_dpaiop_type;
extern const struct device_type fsl_mc_bus_dpci_type;
extern const struct device_type fsl_mc_bus_dpdmai_type;
static inline bool is_fsl_mc_bus_dprc(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dprc_type;
}
static inline bool is_fsl_mc_bus_dpni(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpni_type;
}
static inline bool is_fsl_mc_bus_dpio(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpio_type;
}
static inline bool is_fsl_mc_bus_dpsw(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpsw_type;
}
static inline bool is_fsl_mc_bus_dpdmux(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpdmux_type;
}
static inline bool is_fsl_mc_bus_dpbp(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpbp_type;
}
static inline bool is_fsl_mc_bus_dpcon(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpcon_type;
}
static inline bool is_fsl_mc_bus_dpmcp(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpmcp_type;
}
static inline bool is_fsl_mc_bus_dpmac(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpmac_type;
}
static inline bool is_fsl_mc_bus_dprtc(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dprtc_type;
}
static inline bool is_fsl_mc_bus_dpseci(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpseci_type;
}
static inline bool is_fsl_mc_bus_dpdcei(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpdcei_type;
}
static inline bool is_fsl_mc_bus_dpaiop(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpaiop_type;
}
static inline bool is_fsl_mc_bus_dpci(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpci_type;
}
static inline bool is_fsl_mc_bus_dpdmai(const struct fsl_mc_device *mc_dev)
{
return mc_dev->dev.type == &fsl_mc_bus_dpdmai_type;
}
#define DPRC_RESET_OPTION_NON_RECURSIVE 0x00000001
int dprc_reset_container(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
int child_container_id,
u32 options);
int dprc_scan_container(struct fsl_mc_device *mc_bus_dev,
bool alloc_interrupts);
void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev,
struct fsl_mc_obj_desc *obj_desc_array,
int num_child_objects_in_mc);
int dprc_cleanup(struct fsl_mc_device *mc_dev);
int dprc_setup(struct fsl_mc_device *mc_dev);
/**
* Maximum number of total IRQs that can be pre-allocated for an MC bus'
* IRQ pool
*/
#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256
int fsl_mc_populate_irq_pool(struct fsl_mc_device *mc_bus_dev,
unsigned int irq_count);
void fsl_mc_cleanup_irq_pool(struct fsl_mc_device *mc_bus_dev);
/*
* Data Path Buffer Pool (DPBP) API
* Contains initialization APIs and runtime control APIs for DPBP
*/
int dpbp_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpbp_id,
u16 *token);
int dpbp_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpbp_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpbp_disable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpbp_reset(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
/**
* struct dpbp_attr - Structure representing DPBP attributes
* @id: DPBP object ID
* @bpid: Hardware buffer pool ID; should be used as an argument in
* acquire/release operations on buffers
*/
struct dpbp_attr {
int id;
u16 bpid;
};
int dpbp_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpbp_attr *attr);
/* Data Path Concentrator (DPCON) API
* Contains initialization APIs and runtime control APIs for DPCON
*/
/**
* Use it to disable notifications; see dpcon_set_notification()
*/
#define DPCON_INVALID_DPIO_ID (int)(-1)
int dpcon_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int dpcon_id,
u16 *token);
int dpcon_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpcon_enable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpcon_disable(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int dpcon_reset(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int fsl_mc_obj_open(struct fsl_mc_io *mc_io,
u32 cmd_flags,
int obj_id,
char *obj_type,
u16 *token);
int fsl_mc_obj_close(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
int fsl_mc_obj_reset(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token);
/**
* struct dpcon_attr - Structure representing DPCON attributes
* @id: DPCON object ID
* @qbman_ch_id: Channel ID to be used by dequeue operation
* @num_priorities: Number of priorities for the DPCON channel (1-8)
*/
struct dpcon_attr {
int id;
u16 qbman_ch_id;
u8 num_priorities;
};
int dpcon_get_attributes(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpcon_attr *attr);
/**
* struct dpcon_notification_cfg - Structure representing notification params
* @dpio_id: DPIO object ID; must be configured with a notification channel;
* to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
* @priority: Priority selection within the DPIO channel; valid values
* are 0-7, depending on the number of priorities in that channel
* @user_ctx: User context value provided with each CDAN message
*/
struct dpcon_notification_cfg {
int dpio_id;
u8 priority;
u64 user_ctx;
};
int dpcon_set_notification(struct fsl_mc_io *mc_io,
u32 cmd_flags,
u16 token,
struct dpcon_notification_cfg *cfg);
#endif /* _FSL_MC_H_ */
local/recipes/gpu/amdgpu-source/include/linux/fsl/netc_global.h
+19
View File
@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2024 NXP
*/
#ifndef __NETC_GLOBAL_H
#define __NETC_GLOBAL_H
#include <linux/io.h>
static inline u32 netc_read(void __iomem *reg)
{
return ioread32(reg);
}
static inline void netc_write(void __iomem *reg, u32 val)
{
iowrite32(val, reg);
}
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/ntmp.h
+128
View File
@@ -0,0 +1,128 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* Copyright 2025 NXP */
#ifndef __NETC_NTMP_H
#define __NETC_NTMP_H
#include <linux/bitops.h>
#include <linux/if_ether.h>
struct maft_keye_data {
u8 mac_addr[ETH_ALEN];
__le16 resv;
};
struct maft_cfge_data {
__le16 si_bitmap;
__le16 resv;
};
struct netc_cbdr_regs {
void __iomem *pir;
void __iomem *cir;
void __iomem *mr;
void __iomem *bar0;
void __iomem *bar1;
void __iomem *lenr;
};
struct netc_tbl_vers {
u8 maft_ver;
u8 rsst_ver;
};
struct netc_swcbd {
void *buf;
dma_addr_t dma;
size_t size;
};
struct netc_cbdr {
struct device *dev;
struct netc_cbdr_regs regs;
int bd_num;
int next_to_use;
int next_to_clean;
int dma_size;
void *addr_base;
void *addr_base_align;
dma_addr_t dma_base;
dma_addr_t dma_base_align;
struct netc_swcbd *swcbd;
/* Serialize the order of command BD ring */
struct mutex ring_lock;
};
struct ntmp_user {
int cbdr_num; /* number of control BD ring */
struct device *dev;
struct netc_cbdr *ring;
struct netc_tbl_vers tbl;
};
struct maft_entry_data {
struct maft_keye_data keye;
struct maft_cfge_data cfge;
};
#if IS_ENABLED(CONFIG_NXP_NETC_LIB)
int ntmp_init_cbdr(struct netc_cbdr *cbdr, struct device *dev,
const struct netc_cbdr_regs *regs);
void ntmp_free_cbdr(struct netc_cbdr *cbdr);
/* NTMP APIs */
int ntmp_maft_add_entry(struct ntmp_user *user, u32 entry_id,
struct maft_entry_data *maft);
int ntmp_maft_query_entry(struct ntmp_user *user, u32 entry_id,
struct maft_entry_data *maft);
int ntmp_maft_delete_entry(struct ntmp_user *user, u32 entry_id);
int ntmp_rsst_update_entry(struct ntmp_user *user, const u32 *table,
int count);
int ntmp_rsst_query_entry(struct ntmp_user *user,
u32 *table, int count);
#else
static inline int ntmp_init_cbdr(struct netc_cbdr *cbdr, struct device *dev,
const struct netc_cbdr_regs *regs)
{
return 0;
}
static inline void ntmp_free_cbdr(struct netc_cbdr *cbdr)
{
}
static inline int ntmp_maft_add_entry(struct ntmp_user *user, u32 entry_id,
struct maft_entry_data *maft)
{
return 0;
}
static inline int ntmp_maft_query_entry(struct ntmp_user *user, u32 entry_id,
struct maft_entry_data *maft)
{
return 0;
}
static inline int ntmp_maft_delete_entry(struct ntmp_user *user, u32 entry_id)
{
return 0;
}
static inline int ntmp_rsst_update_entry(struct ntmp_user *user,
const u32 *table, int count)
{
return 0;
}
static inline int ntmp_rsst_query_entry(struct ntmp_user *user,
u32 *table, int count)
{
return 0;
}
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/fsl/ptp_qoriq.h
+198
View File
@@ -0,0 +1,198 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2010 OMICRON electronics GmbH
* Copyright 2018 NXP
*/
#ifndef __PTP_QORIQ_H__
#define __PTP_QORIQ_H__
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/ptp_clock_kernel.h>
/*
* qoriq ptp registers
*/
struct ctrl_regs {
u32 tmr_ctrl; /* Timer control register */
u32 tmr_tevent; /* Timestamp event register */
u32 tmr_temask; /* Timer event mask register */
u32 tmr_pevent; /* Timestamp event register */
u32 tmr_pemask; /* Timer event mask register */
u32 tmr_stat; /* Timestamp status register */
u32 tmr_cnt_h; /* Timer counter high register */
u32 tmr_cnt_l; /* Timer counter low register */
u32 tmr_add; /* Timer drift compensation addend register */
u32 tmr_acc; /* Timer accumulator register */
u32 tmr_prsc; /* Timer prescale */
u8 res1[4];
u32 tmroff_h; /* Timer offset high */
u32 tmroff_l; /* Timer offset low */
};
struct alarm_regs {
u32 tmr_alarm1_h; /* Timer alarm 1 high register */
u32 tmr_alarm1_l; /* Timer alarm 1 high register */
u32 tmr_alarm2_h; /* Timer alarm 2 high register */
u32 tmr_alarm2_l; /* Timer alarm 2 high register */
};
struct fiper_regs {
u32 tmr_fiper1; /* Timer fixed period interval */
u32 tmr_fiper2; /* Timer fixed period interval */
u32 tmr_fiper3; /* Timer fixed period interval */
};
struct etts_regs {
u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
};
struct ptp_qoriq_registers {
struct ctrl_regs __iomem *ctrl_regs;
struct alarm_regs __iomem *alarm_regs;
struct fiper_regs __iomem *fiper_regs;
struct etts_regs __iomem *etts_regs;
};
/* Offset definitions for the four register groups */
#define ETSEC_CTRL_REGS_OFFSET 0x0
#define ETSEC_ALARM_REGS_OFFSET 0x40
#define ETSEC_FIPER_REGS_OFFSET 0x80
#define ETSEC_ETTS_REGS_OFFSET 0xa0
#define CTRL_REGS_OFFSET 0x80
#define ALARM_REGS_OFFSET 0xb8
#define FIPER_REGS_OFFSET 0xd0
#define ETTS_REGS_OFFSET 0xe0
/* Bit definitions for the TMR_CTRL register */
#define ALM1P (1<<31) /* Alarm1 output polarity */
#define ALM2P (1<<30) /* Alarm2 output polarity */
#define FIPERST (1<<28) /* FIPER start indication */
#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
#define TCLK_PERIOD_MASK (0x3ff)
#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
#define FRD (1<<14) /* FIPER Realignment Disable */
#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
#define COPH (1<<7) /* Generated clock output phase. */
#define CIPH (1<<6) /* External oscillator input clock phase */
#define TMSR (1<<5) /* Timer soft reset. */
#define BYP (1<<3) /* Bypass drift compensated clock */
#define TE (1<<2) /* 1588 timer enable. */
#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
#define CKSEL_MASK (0x3)
/* Bit definitions for the TMR_TEVENT register */
#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
#define ALM2 (1<<17) /* Current time = alarm time register 2 */
#define ALM1 (1<<16) /* Current time = alarm time register 1 */
#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
/* Bit definitions for the TMR_TEMASK register */
#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
#define ALM2EN (1<<17) /* Timer ALM2 event enable */
#define ALM1EN (1<<16) /* Timer ALM1 event enable */
#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
/* Bit definitions for the TMR_PEVENT register */
#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
#define RXP (1<<0) /* PTP frame has been received */
/* Bit definitions for the TMR_PEMASK register */
#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
#define RXPEN (1<<0) /* Receive PTP packet event enable */
/* Bit definitions for the TMR_STAT register */
#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
#define STAT_VEC_MASK (0x3f)
#define ETS1_VLD (1<<24)
#define ETS2_VLD (1<<25)
/* Bit definitions for the TMR_PRSC register */
#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
#define PRSC_OCK_MASK (0xffff)
#define DRIVER "ptp_qoriq"
#define N_EXT_TS 2
#define DEFAULT_CKSEL 1
#define DEFAULT_TMR_PRSC 2
#define DEFAULT_FIPER1_PERIOD 1000000000
#define DEFAULT_FIPER2_PERIOD 1000000000
#define DEFAULT_FIPER3_PERIOD 1000000000
struct ptp_qoriq {
void __iomem *base;
struct ptp_qoriq_registers regs;
spinlock_t lock; /* protects regs */
struct ptp_clock *clock;
struct ptp_clock_info caps;
struct resource *rsrc;
struct device *dev;
bool extts_fifo_support;
bool fiper3_support;
bool etsec;
int irq;
int phc_index;
u32 tclk_period; /* nanoseconds */
u32 tmr_prsc;
u32 tmr_add;
u32 cksel;
u32 tmr_fiper1;
u32 tmr_fiper2;
u32 tmr_fiper3;
u32 (*read)(unsigned __iomem *addr);
void (*write)(unsigned __iomem *addr, u32 val);
};
static inline u32 qoriq_read_be(unsigned __iomem *addr)
{
return ioread32be(addr);
}
static inline void qoriq_write_be(unsigned __iomem *addr, u32 val)
{
iowrite32be(val, addr);
}
static inline u32 qoriq_read_le(unsigned __iomem *addr)
{
return ioread32(addr);
}
static inline void qoriq_write_le(unsigned __iomem *addr, u32 val)
{
iowrite32(val, addr);
}
irqreturn_t ptp_qoriq_isr(int irq, void *priv);
int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
const struct ptp_clock_info *caps);
void ptp_qoriq_free(struct ptp_qoriq *ptp_qoriq);
int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta);
int ptp_qoriq_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts);
int ptp_qoriq_settime(struct ptp_clock_info *ptp,
const struct timespec64 *ts);
int ptp_qoriq_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on);
int extts_clean_up(struct ptp_qoriq *ptp_qoriq, int index, bool update_event);
#endif