restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
@@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*/
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#ifndef _DMAENGINE_AMD_XDMA_H
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#define _DMAENGINE_AMD_XDMA_H
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num);
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void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num);
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int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index);
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#endif /* _DMAENGINE_AMD_XDMA_H */
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@@ -0,0 +1,54 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for the Synopsys DesignWare DMA Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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* Copyright (C) 2014 Intel Corporation
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*/
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#ifndef _DMA_DW_H
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#define _DMA_DW_H
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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struct dw_dma;
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/**
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* struct dw_dma_chip - representation of DesignWare DMA controller hardware
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* @dev: struct device of the DMA controller
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* @id: instance ID
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* @irq: irq line
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* @regs: memory mapped I/O space
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* @clk: hclk clock
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* @dw: struct dw_dma that is filed by dw_dma_probe()
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* @pdata: pointer to platform data
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*/
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struct dw_dma_chip {
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struct device *dev;
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int id;
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int irq;
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void __iomem *regs;
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struct clk *clk;
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struct dw_dma *dw;
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const struct dw_dma_platform_data *pdata;
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};
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/* Export to the platform drivers */
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#if IS_ENABLED(CONFIG_DW_DMAC_CORE)
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int dw_dma_probe(struct dw_dma_chip *chip);
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int dw_dma_remove(struct dw_dma_chip *chip);
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int idma32_dma_probe(struct dw_dma_chip *chip);
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int idma32_dma_remove(struct dw_dma_chip *chip);
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#else
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static inline int dw_dma_probe(struct dw_dma_chip *chip) { return -ENODEV; }
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static inline int dw_dma_remove(struct dw_dma_chip *chip) { return 0; }
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static inline int idma32_dma_probe(struct dw_dma_chip *chip) { return -ENODEV; }
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static inline int idma32_dma_remove(struct dw_dma_chip *chip) { return 0; }
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#endif /* CONFIG_DW_DMAC_CORE */
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#endif /* _DMA_DW_H */
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@@ -0,0 +1,125 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
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* Synopsys DesignWare eDMA core driver
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*
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* Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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*/
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#ifndef _DW_EDMA_H
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#define _DW_EDMA_H
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#define EDMA_MAX_WR_CH 8
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#define EDMA_MAX_RD_CH 8
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struct dw_edma;
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struct dw_edma_region {
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u64 paddr;
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union {
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void *mem;
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void __iomem *io;
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} vaddr;
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size_t sz;
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};
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/**
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* struct dw_edma_plat_ops - platform-specific eDMA methods
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* @irq_vector: Get IRQ number of the passed eDMA channel. Note the
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* method accepts the channel id in the end-to-end
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* numbering with the eDMA write channels being placed
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* first in the row.
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* @pci_address: Get PCIe bus address corresponding to the passed CPU
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* address. Note there is no need in specifying this
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* function if the address translation is performed by
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* the DW PCIe RP/EP controller with the DW eDMA device in
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* subject and DMA_BYPASS isn't set for all the outbound
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* iATU windows. That will be done by the controller
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* automatically.
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*/
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struct dw_edma_plat_ops {
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int (*irq_vector)(struct device *dev, unsigned int nr);
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u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr);
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};
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enum dw_edma_map_format {
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EDMA_MF_EDMA_LEGACY = 0x0,
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EDMA_MF_EDMA_UNROLL = 0x1,
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EDMA_MF_HDMA_COMPAT = 0x5,
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EDMA_MF_HDMA_NATIVE = 0x7,
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};
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/**
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* enum dw_edma_chip_flags - Flags specific to an eDMA chip
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* @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
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*/
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enum dw_edma_chip_flags {
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DW_EDMA_CHIP_LOCAL = BIT(0),
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};
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/**
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* struct dw_edma_chip - representation of DesignWare eDMA controller hardware
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* @dev: struct device of the eDMA controller
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* @nr_irqs: total number of DMA IRQs
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* @ops: DMA channel to IRQ number mapping
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* @flags: dw_edma_chip_flags
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* @reg_base: DMA register base address
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* @ll_wr_cnt: DMA write link list count
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* @ll_rd_cnt: DMA read link list count
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* @ll_region_wr: DMA descriptor link list memory for write channel
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* @ll_region_rd: DMA descriptor link list memory for read channel
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* @dt_region_wr: DMA data memory for write channel
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* @dt_region_rd: DMA data memory for read channel
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* @db_irq: Virtual IRQ dedicated to interrupt emulation
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* @db_offset: Offset from DMA register base
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* @mf: DMA register map format
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* @dw: struct dw_edma that is filled by dw_edma_probe()
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*/
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struct dw_edma_chip {
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struct device *dev;
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int nr_irqs;
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const struct dw_edma_plat_ops *ops;
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u32 flags;
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void __iomem *reg_base;
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u16 ll_wr_cnt;
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u16 ll_rd_cnt;
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/* link list address */
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struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
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struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
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/* data region */
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struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
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struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
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/* interrupt emulation */
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int db_irq;
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resource_size_t db_offset;
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enum dw_edma_map_format mf;
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struct dw_edma *dw;
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bool cfg_non_ll;
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};
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/* Export to the platform drivers */
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#if IS_REACHABLE(CONFIG_DW_EDMA)
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int dw_edma_probe(struct dw_edma_chip *chip);
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int dw_edma_remove(struct dw_edma_chip *chip);
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#else
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static inline int dw_edma_probe(struct dw_edma_chip *chip)
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{
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return -ENODEV;
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}
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static inline int dw_edma_remove(struct dw_edma_chip *chip)
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{
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return 0;
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}
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#endif /* CONFIG_DW_EDMA */
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#endif /* _DW_EDMA_H */
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@@ -0,0 +1,63 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Driver for the High Speed UART DMA
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*
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* Copyright (C) 2015 Intel Corporation
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*/
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#ifndef _DMA_HSU_H
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#define _DMA_HSU_H
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#include <linux/errno.h>
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#include <linux/kconfig.h>
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#include <linux/types.h>
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#include <linux/platform_data/dma-hsu.h>
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struct device;
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struct hsu_dma;
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/**
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* struct hsu_dma_chip - representation of HSU DMA hardware
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* @dev: struct device of the DMA controller
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* @irq: irq line
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* @regs: memory mapped I/O space
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* @length: I/O space length
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* @offset: offset of the I/O space where registers are located
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* @hsu: struct hsu_dma that is filed by ->probe()
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* @pdata: platform data for the DMA controller if provided
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*/
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struct hsu_dma_chip {
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struct device *dev;
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int irq;
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void __iomem *regs;
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unsigned int length;
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unsigned int offset;
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struct hsu_dma *hsu;
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};
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#if IS_ENABLED(CONFIG_HSU_DMA)
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/* Export to the internal users */
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int hsu_dma_get_status(struct hsu_dma_chip *chip, unsigned short nr,
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u32 *status);
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int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status);
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/* Export to the platform drivers */
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int hsu_dma_probe(struct hsu_dma_chip *chip);
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int hsu_dma_remove(struct hsu_dma_chip *chip);
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#else
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static inline int hsu_dma_get_status(struct hsu_dma_chip *chip,
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unsigned short nr, u32 *status)
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{
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return 0;
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}
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static inline int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr,
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u32 status)
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{
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return 0;
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}
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static inline int hsu_dma_probe(struct hsu_dma_chip *chip) { return -ENODEV; }
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static inline int hsu_dma_remove(struct hsu_dma_chip *chip) { return 0; }
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#endif /* CONFIG_HSU_DMA */
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#endif /* _DMA_HSU_H */
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@@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Definitions for the Intel integrated DMA 64-bit
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*
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* Copyright (C) 2019 Intel Corporation
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*/
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#ifndef __LINUX_DMA_IDMA64_H__
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#define __LINUX_DMA_IDMA64_H__
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/* Platform driver name */
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#define LPSS_IDMA64_DRIVER_NAME "idma64"
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#endif /* __LINUX_DMA_IDMA64_H__ */
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@@ -0,0 +1,103 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __LINUX_DMA_IMX_H
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#define __LINUX_DMA_IMX_H
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#include <linux/scatterlist.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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/*
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* This enumerates peripheral types. Used for SDMA.
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*/
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enum sdma_peripheral_type {
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IMX_DMATYPE_SSI, /* MCU domain SSI */
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IMX_DMATYPE_SSI_SP, /* Shared SSI */
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IMX_DMATYPE_MMC, /* MMC */
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IMX_DMATYPE_SDHC, /* SDHC */
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IMX_DMATYPE_UART, /* MCU domain UART */
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IMX_DMATYPE_UART_SP, /* Shared UART */
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IMX_DMATYPE_FIRI, /* FIRI */
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IMX_DMATYPE_CSPI, /* MCU domain CSPI */
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IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
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IMX_DMATYPE_SIM, /* SIM */
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IMX_DMATYPE_ATA, /* ATA */
|
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IMX_DMATYPE_CCM, /* CCM */
|
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IMX_DMATYPE_EXT, /* External peripheral */
|
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IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
|
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IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
|
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IMX_DMATYPE_DSP, /* DSP */
|
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IMX_DMATYPE_MEMORY, /* Memory */
|
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IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
|
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IMX_DMATYPE_SPDIF, /* SPDIF */
|
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IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
|
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IMX_DMATYPE_ASRC, /* ASRC */
|
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IMX_DMATYPE_ESAI, /* ESAI */
|
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IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
|
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IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
|
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IMX_DMATYPE_SAI, /* SAI */
|
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IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
|
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IMX_DMATYPE_HDMI, /* HDMI Audio */
|
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IMX_DMATYPE_I2C, /* I2C */
|
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};
|
||||
|
||||
enum imx_dma_prio {
|
||||
DMA_PRIO_HIGH = 0,
|
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DMA_PRIO_MEDIUM = 1,
|
||||
DMA_PRIO_LOW = 2
|
||||
};
|
||||
|
||||
struct imx_dma_data {
|
||||
int dma_request; /* DMA request line */
|
||||
int dma_request2; /* secondary DMA request line */
|
||||
enum sdma_peripheral_type peripheral_type;
|
||||
int priority;
|
||||
};
|
||||
|
||||
static inline int imx_dma_is_ipu(struct dma_chan *chan)
|
||||
{
|
||||
return !strcmp(dev_name(chan->device->dev), "ipu-core");
|
||||
}
|
||||
|
||||
static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
|
||||
{
|
||||
return !strcmp(chan->device->dev->driver->name, "imx-sdma") ||
|
||||
!strcmp(chan->device->dev->driver->name, "imx-dma");
|
||||
}
|
||||
|
||||
/**
|
||||
* struct sdma_peripheral_config - SDMA config for audio
|
||||
* @n_fifos_src: Number of FIFOs for recording
|
||||
* @n_fifos_dst: Number of FIFOs for playback
|
||||
* @stride_fifos_src: FIFO address stride for recording, 0 means all FIFOs are
|
||||
* continuous, 1 means 1 word stride between FIFOs. All stride
|
||||
* between FIFOs should be same.
|
||||
* @stride_fifos_dst: FIFO address stride for playback
|
||||
* @words_per_fifo: numbers of words per FIFO fetch/fill, 1 means
|
||||
* one channel per FIFO, 2 means 2 channels per FIFO..
|
||||
* If 'n_fifos_src = 4' and 'words_per_fifo = 2', it
|
||||
* means the first two words(channels) fetch from FIFO0
|
||||
* and then jump to FIFO1 for next two words, and so on
|
||||
* after the last FIFO3 fetched, roll back to FIFO0.
|
||||
* @sw_done: Use software done. Needed for PDM (micfil)
|
||||
*
|
||||
* Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
|
||||
* registers. For multichannel recording/playback the SAI/micfil have
|
||||
* one FIFO register per channel and the SDMA engine has to read/write
|
||||
* the next channel from/to the next register and wrap around to the
|
||||
* first register when all channels are handled. The number of active
|
||||
* channels must be communicated to the SDMA engine using this struct.
|
||||
*/
|
||||
struct sdma_peripheral_config {
|
||||
int n_fifos_src;
|
||||
int n_fifos_dst;
|
||||
int stride_fifos_src;
|
||||
int stride_fifos_dst;
|
||||
int words_per_fifo;
|
||||
bool sw_done;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_DMA_IMX_H */
|
||||
@@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
|
||||
*/
|
||||
|
||||
#ifndef K3_EVENT_ROUTER_
|
||||
#define K3_EVENT_ROUTER_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct k3_event_route_data {
|
||||
void *priv;
|
||||
int (*set_event)(void *priv, u32 event);
|
||||
};
|
||||
|
||||
#endif /* K3_EVENT_ROUTER_ */
|
||||
@@ -0,0 +1,86 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
|
||||
*/
|
||||
|
||||
#ifndef K3_PSIL_H_
|
||||
#define K3_PSIL_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000
|
||||
|
||||
struct device;
|
||||
|
||||
/**
|
||||
* enum udma_tp_level - Channel Throughput Levels
|
||||
* @UDMA_TP_NORMAL: Normal channel
|
||||
* @UDMA_TP_HIGH: High Throughput channel
|
||||
* @UDMA_TP_ULTRAHIGH: Ultra High Throughput channel
|
||||
*/
|
||||
enum udma_tp_level {
|
||||
UDMA_TP_NORMAL = 0,
|
||||
UDMA_TP_HIGH,
|
||||
UDMA_TP_ULTRAHIGH,
|
||||
UDMA_TP_LAST,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum psil_endpoint_type - PSI-L Endpoint type
|
||||
* @PSIL_EP_NATIVE: Normal channel
|
||||
* @PSIL_EP_PDMA_XY: XY mode PDMA
|
||||
* @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
|
||||
* @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
|
||||
*/
|
||||
enum psil_endpoint_type {
|
||||
PSIL_EP_NATIVE = 0,
|
||||
PSIL_EP_PDMA_XY,
|
||||
PSIL_EP_PDMA_MCAN,
|
||||
PSIL_EP_PDMA_AASRC,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct psil_endpoint_config - PSI-L Endpoint configuration
|
||||
* @ep_type: PSI-L endpoint type
|
||||
* @channel_tpl: Desired throughput level for the channel
|
||||
* @pkt_mode: If set, the channel must be in Packet mode, otherwise in
|
||||
* TR mode
|
||||
* @notdpkt: TDCM must be suppressed on the TX channel
|
||||
* @needs_epib: Endpoint needs EPIB
|
||||
* @pdma_acc32: ACC32 must be enabled on the PDMA side
|
||||
* @pdma_burst: BURST must be enabled on the PDMA side
|
||||
* @psd_size: If set, PSdata is used by the endpoint
|
||||
* @mapped_channel_id: PKTDMA thread to channel mapping for mapped channels.
|
||||
* The thread must be serviced by the specified channel if
|
||||
* mapped_channel_id is >= 0 in case of PKTDMA
|
||||
* @flow_start: PKDMA flow range start of mapped channel. Unmapped
|
||||
* channels use flow_id == chan_id
|
||||
* @flow_num: PKDMA flow count of mapped channel. Unmapped channels
|
||||
* use flow_id == chan_id
|
||||
* @default_flow_id: PKDMA default (r)flow index of mapped channel.
|
||||
* Must be within the flow range of the mapped channel.
|
||||
*/
|
||||
struct psil_endpoint_config {
|
||||
enum psil_endpoint_type ep_type;
|
||||
enum udma_tp_level channel_tpl;
|
||||
|
||||
unsigned pkt_mode:1;
|
||||
unsigned notdpkt:1;
|
||||
unsigned needs_epib:1;
|
||||
/* PDMA properties, valid for PSIL_EP_PDMA_* */
|
||||
unsigned pdma_acc32:1;
|
||||
unsigned pdma_burst:1;
|
||||
|
||||
u32 psd_size;
|
||||
/* PKDMA mapped channel */
|
||||
s16 mapped_channel_id;
|
||||
/* PKTDMA tflow and rflow ranges for mapped channel */
|
||||
u16 flow_start;
|
||||
u16 flow_num;
|
||||
s16 default_flow_id;
|
||||
};
|
||||
|
||||
int psil_set_new_ep_config(struct device *dev, const char *name,
|
||||
struct psil_endpoint_config *ep_config);
|
||||
|
||||
#endif /* K3_PSIL_H_ */
|
||||
@@ -0,0 +1,153 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
|
||||
*/
|
||||
|
||||
#ifndef K3_UDMA_GLUE_H_
|
||||
#define K3_UDMA_GLUE_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/soc/ti/k3-ringacc.h>
|
||||
#include <linux/dma/ti-cppi5.h>
|
||||
|
||||
struct k3_udma_glue_tx_channel_cfg {
|
||||
struct k3_ring_cfg tx_cfg;
|
||||
struct k3_ring_cfg txcq_cfg;
|
||||
|
||||
bool tx_pause_on_err;
|
||||
bool tx_filt_einfo;
|
||||
bool tx_filt_pswords;
|
||||
bool tx_supr_tdpkt;
|
||||
u32 swdata_size;
|
||||
};
|
||||
|
||||
struct k3_udma_glue_tx_channel;
|
||||
|
||||
struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev,
|
||||
const char *name, struct k3_udma_glue_tx_channel_cfg *cfg);
|
||||
|
||||
struct k3_udma_glue_tx_channel *
|
||||
k3_udma_glue_request_tx_chn_for_thread_id(struct device *dev,
|
||||
struct k3_udma_glue_tx_channel_cfg *cfg,
|
||||
struct device_node *udmax_np, u32 thread_id);
|
||||
|
||||
void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
struct cppi5_host_desc_t *desc_tx,
|
||||
dma_addr_t desc_dma);
|
||||
int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
dma_addr_t *desc_dma);
|
||||
int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
bool sync);
|
||||
void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
void *data, void (*cleanup)(void *data, dma_addr_t desc_dma));
|
||||
u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
struct device *
|
||||
k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn);
|
||||
void k3_udma_glue_tx_dma_to_cppi5_addr(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
dma_addr_t *addr);
|
||||
void k3_udma_glue_tx_cppi5_to_dma_addr(struct k3_udma_glue_tx_channel *tx_chn,
|
||||
dma_addr_t *addr);
|
||||
|
||||
enum {
|
||||
K3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,
|
||||
K3_UDMA_GLUE_SRC_TAG_LO_USE_FLOW_REG = 1,
|
||||
K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_FLOW_ID = 2,
|
||||
K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG = 4,
|
||||
};
|
||||
|
||||
/**
|
||||
* k3_udma_glue_rx_flow_cfg - UDMA RX flow cfg
|
||||
*
|
||||
* @rx_cfg: RX ring configuration
|
||||
* @rxfdq_cfg: RX free Host PD ring configuration
|
||||
* @ring_rxq_id: RX ring id (or -1 for any)
|
||||
* @ring_rxfdq0_id: RX free Host PD ring (FDQ) if (or -1 for any)
|
||||
* @rx_error_handling: Rx Error Handling Mode (0 - drop, 1 - re-try)
|
||||
* @src_tag_lo_sel: Rx Source Tag Low Byte Selector in Host PD
|
||||
*/
|
||||
struct k3_udma_glue_rx_flow_cfg {
|
||||
struct k3_ring_cfg rx_cfg;
|
||||
struct k3_ring_cfg rxfdq_cfg;
|
||||
int ring_rxq_id;
|
||||
int ring_rxfdq0_id;
|
||||
bool rx_error_handling;
|
||||
int src_tag_lo_sel;
|
||||
};
|
||||
|
||||
/**
|
||||
* k3_udma_glue_rx_channel_cfg - UDMA RX channel cfg
|
||||
*
|
||||
* @psdata_size: SW Data is present in Host PD of @swdata_size bytes
|
||||
* @flow_id_base: first flow_id used by channel.
|
||||
* if @flow_id_base = -1 - range of GP rflows will be
|
||||
* allocated dynamically.
|
||||
* @flow_id_num: number of RX flows used by channel
|
||||
* @flow_id_use_rxchan_id: use RX channel id as flow id,
|
||||
* used only if @flow_id_num = 1
|
||||
* @remote indication that RX channel is remote - some remote CPU
|
||||
* core owns and control the RX channel. Linux Host only
|
||||
* allowed to attach and configure RX Flow within RX
|
||||
* channel. if set - not RX channel operation will be
|
||||
* performed by K3 NAVSS DMA glue interface.
|
||||
* @def_flow_cfg default RX flow configuration,
|
||||
* used only if @flow_id_num = 1
|
||||
*/
|
||||
struct k3_udma_glue_rx_channel_cfg {
|
||||
u32 swdata_size;
|
||||
int flow_id_base;
|
||||
int flow_id_num;
|
||||
bool flow_id_use_rxchan_id;
|
||||
bool remote;
|
||||
|
||||
struct k3_udma_glue_rx_flow_cfg *def_flow_cfg;
|
||||
};
|
||||
|
||||
struct k3_udma_glue_rx_channel;
|
||||
|
||||
struct k3_udma_glue_rx_channel *k3_udma_glue_request_rx_chn(
|
||||
struct device *dev,
|
||||
const char *name,
|
||||
struct k3_udma_glue_rx_channel_cfg *cfg);
|
||||
|
||||
struct k3_udma_glue_rx_channel *
|
||||
k3_udma_glue_request_remote_rx_chn_for_thread_id(struct device *dev,
|
||||
struct k3_udma_glue_rx_channel_cfg *cfg,
|
||||
struct device_node *udmax_np, u32 thread_id);
|
||||
|
||||
void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
|
||||
int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
|
||||
void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
|
||||
void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
bool sync);
|
||||
int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_num, struct cppi5_host_desc_t *desc_tx,
|
||||
dma_addr_t desc_dma);
|
||||
int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_num, dma_addr_t *desc_dma);
|
||||
int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_idx, struct k3_udma_glue_rx_flow_cfg *flow_cfg);
|
||||
u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_idx);
|
||||
u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn);
|
||||
int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_num);
|
||||
void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_num, void *data,
|
||||
void (*cleanup)(void *data, dma_addr_t desc_dma));
|
||||
int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_idx);
|
||||
int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
u32 flow_idx);
|
||||
struct device *
|
||||
k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn);
|
||||
void k3_udma_glue_rx_dma_to_cppi5_addr(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
dma_addr_t *addr);
|
||||
void k3_udma_glue_rx_cppi5_to_dma_addr(struct k3_udma_glue_rx_channel *rx_chn,
|
||||
dma_addr_t *addr);
|
||||
|
||||
#endif /* K3_UDMA_GLUE_H_ */
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _MXS_DMA_H_
|
||||
#define _MXS_DMA_H_
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define MXS_DMA_CTRL_WAIT4END BIT(31)
|
||||
#define MXS_DMA_CTRL_WAIT4RDY BIT(30)
|
||||
|
||||
/*
|
||||
* The mxs dmaengine can do PIO transfers. We pass a pointer to the PIO words
|
||||
* in the second argument to dmaengine_prep_slave_sg when the direction is
|
||||
* set to DMA_TRANS_NONE. To make this clear and to prevent users from doing
|
||||
* the error prone casting we have this wrapper function
|
||||
*/
|
||||
static inline struct dma_async_tx_descriptor *mxs_dmaengine_prep_pio(
|
||||
struct dma_chan *chan, u32 *pio, unsigned int npio,
|
||||
enum dma_transfer_direction dir, unsigned long flags)
|
||||
{
|
||||
return dmaengine_prep_slave_sg(chan, (struct scatterlist *)pio, npio,
|
||||
dir, flags);
|
||||
}
|
||||
|
||||
#endif /* _MXS_DMA_H_ */
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _PXA_DMA_H_
|
||||
#define _PXA_DMA_H_
|
||||
|
||||
enum pxad_chan_prio {
|
||||
PXAD_PRIO_HIGHEST = 0,
|
||||
PXAD_PRIO_NORMAL,
|
||||
PXAD_PRIO_LOW,
|
||||
PXAD_PRIO_LOWEST,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pxad_param - dma channel request parameters
|
||||
* @drcmr: requestor line number
|
||||
* @prio: minimal mandatory priority of the channel
|
||||
*
|
||||
* If a requested channel is granted, its priority will be at least @prio,
|
||||
* ie. if PXAD_PRIO_LOW is required, the requested channel will be either
|
||||
* PXAD_PRIO_LOW, PXAD_PRIO_NORMAL or PXAD_PRIO_HIGHEST.
|
||||
*/
|
||||
struct pxad_param {
|
||||
unsigned int drcmr;
|
||||
enum pxad_chan_prio prio;
|
||||
};
|
||||
|
||||
#endif /* _PXA_DMA_H_ */
|
||||
@@ -0,0 +1,86 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020, Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef QCOM_GPI_DMA_H
|
||||
#define QCOM_GPI_DMA_H
|
||||
|
||||
/**
|
||||
* enum spi_transfer_cmd - spi transfer commands
|
||||
* @SPI_TX: SPI peripheral TX command
|
||||
* @SPI_RX: SPI peripheral RX command
|
||||
* @SPI_DUPLEX: SPI peripheral Duplex command
|
||||
*/
|
||||
enum spi_transfer_cmd {
|
||||
SPI_TX = 1,
|
||||
SPI_RX,
|
||||
SPI_DUPLEX,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct gpi_spi_config - spi config for peripheral
|
||||
*
|
||||
* @loopback_en: spi loopback enable when set
|
||||
* @clock_pol_high: clock polarity
|
||||
* @data_pol_high: data polarity
|
||||
* @pack_en: process tx/rx buffers as packed
|
||||
* @word_len: spi word length
|
||||
* @clk_div: source clock divider
|
||||
* @clk_src: serial clock
|
||||
* @cmd: spi cmd
|
||||
* @fragmentation: keep CS asserted at end of sequence
|
||||
* @cs: chip select toggle
|
||||
* @set_config: set peripheral config
|
||||
* @rx_len: receive length for buffer
|
||||
*/
|
||||
struct gpi_spi_config {
|
||||
u8 set_config;
|
||||
u8 loopback_en;
|
||||
u8 clock_pol_high;
|
||||
u8 data_pol_high;
|
||||
u8 pack_en;
|
||||
u8 word_len;
|
||||
u8 fragmentation;
|
||||
u8 cs;
|
||||
u32 clk_div;
|
||||
u32 clk_src;
|
||||
enum spi_transfer_cmd cmd;
|
||||
u32 rx_len;
|
||||
};
|
||||
|
||||
enum i2c_op {
|
||||
I2C_WRITE = 1,
|
||||
I2C_READ,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct gpi_i2c_config - i2c config for peripheral
|
||||
*
|
||||
* @pack_enable: process tx/rx buffers as packed
|
||||
* @cycle_count: clock cycles to be sent
|
||||
* @high_count: high period of clock
|
||||
* @low_count: low period of clock
|
||||
* @clk_div: source clock divider
|
||||
* @addr: i2c bus address
|
||||
* @stretch: stretch the clock at eot
|
||||
* @set_config: set peripheral config
|
||||
* @rx_len: receive length for buffer
|
||||
* @op: i2c cmd
|
||||
* @multi_msg: is part of multi i2c r-w msgs
|
||||
*/
|
||||
struct gpi_i2c_config {
|
||||
u8 set_config;
|
||||
u8 pack_enable;
|
||||
u8 cycle_count;
|
||||
u8 high_count;
|
||||
u8 low_count;
|
||||
u8 addr;
|
||||
u8 stretch;
|
||||
u16 clk_div;
|
||||
u32 rx_len;
|
||||
enum i2c_op op;
|
||||
bool multi_msg;
|
||||
};
|
||||
|
||||
#endif /* QCOM_GPI_DMA_H */
|
||||
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
#ifndef __LINUX_DMA_QCOM_ADM_H
|
||||
#define __LINUX_DMA_QCOM_ADM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct qcom_adm_peripheral_config {
|
||||
u32 crci;
|
||||
u32 mux;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_DMA_QCOM_ADM_H */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _QCOM_BAM_DMA_H
|
||||
#define _QCOM_BAM_DMA_H
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
/*
|
||||
* This data type corresponds to the native Command Element
|
||||
* supported by BAM DMA Engine.
|
||||
*
|
||||
* @cmd_and_addr - upper 8 bits command and lower 24 bits register address.
|
||||
* @data - for write command: content to be written into peripheral register.
|
||||
* for read command: dest addr to write peripheral register value.
|
||||
* @mask - register mask.
|
||||
* @reserved - for future usage.
|
||||
*
|
||||
*/
|
||||
struct bam_cmd_element {
|
||||
__le32 cmd_and_addr;
|
||||
__le32 data;
|
||||
__le32 mask;
|
||||
__le32 reserved;
|
||||
};
|
||||
|
||||
/*
|
||||
* This enum indicates the command type in a command element
|
||||
*/
|
||||
enum bam_command_type {
|
||||
BAM_WRITE_COMMAND = 0,
|
||||
BAM_READ_COMMAND,
|
||||
};
|
||||
|
||||
/*
|
||||
* prep_bam_ce_le32 - Wrapper function to prepare a single BAM command
|
||||
* element with the data already in le32 format.
|
||||
*
|
||||
* @bam_ce: bam command element
|
||||
* @addr: target address
|
||||
* @cmd: BAM command
|
||||
* @data: actual data for write and dest addr for read in le32
|
||||
*/
|
||||
static inline void
|
||||
bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr,
|
||||
enum bam_command_type cmd, __le32 data)
|
||||
{
|
||||
bam_ce->cmd_and_addr =
|
||||
cpu_to_le32((addr & 0xffffff) | ((cmd & 0xff) << 24));
|
||||
bam_ce->data = data;
|
||||
bam_ce->mask = cpu_to_le32(0xffffffff);
|
||||
}
|
||||
|
||||
/*
|
||||
* bam_prep_ce - Wrapper function to prepare a single BAM command element
|
||||
* with the data.
|
||||
*
|
||||
* @bam_ce: BAM command element
|
||||
* @addr: target address
|
||||
* @cmd: BAM command
|
||||
* @data: actual data for write and dest addr for read
|
||||
*/
|
||||
static inline void
|
||||
bam_prep_ce(struct bam_cmd_element *bam_ce, u32 addr,
|
||||
enum bam_command_type cmd, u32 data)
|
||||
{
|
||||
bam_prep_ce_le32(bam_ce, addr, cmd, cpu_to_le32(data));
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,190 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef _SPRD_DMA_H_
|
||||
#define _SPRD_DMA_H_
|
||||
|
||||
#define SPRD_DMA_REQ_SHIFT 8
|
||||
#define SPRD_DMA_TRG_MODE_SHIFT 16
|
||||
#define SPRD_DMA_CHN_MODE_SHIFT 24
|
||||
#define SPRD_DMA_FLAGS(chn_mode, trg_mode, req_mode, int_type) \
|
||||
((chn_mode) << SPRD_DMA_CHN_MODE_SHIFT | \
|
||||
(trg_mode) << SPRD_DMA_TRG_MODE_SHIFT | \
|
||||
(req_mode) << SPRD_DMA_REQ_SHIFT | (int_type))
|
||||
|
||||
/*
|
||||
* The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
|
||||
* we can request 2 dma channels, one for source channel, and another one for
|
||||
* destination channel. Each channel is independent, and has its own
|
||||
* configurations. Once the source channel's transaction is done, it will
|
||||
* trigger the destination channel's transaction automatically by hardware
|
||||
* signal.
|
||||
*
|
||||
* To support 2-stage tansfer, we must configure the channel mode and trigger
|
||||
* mode as below definition.
|
||||
*/
|
||||
|
||||
/*
|
||||
* enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
|
||||
* @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
|
||||
* support the 2-stage transfer.
|
||||
* @SPRD_DMA_SRC_CHN0: Channel used as source channel 0.
|
||||
* @SPRD_DMA_SRC_CHN1: Channel used as source channel 1.
|
||||
* @SPRD_DMA_DST_CHN0: Channel used as destination channel 0.
|
||||
* @SPRD_DMA_DST_CHN1: Channel used as destination channel 1.
|
||||
*
|
||||
* Now the DMA controller can supports 2 groups 2-stage transfer.
|
||||
*/
|
||||
enum sprd_dma_chn_mode {
|
||||
SPRD_DMA_CHN_MODE_NONE,
|
||||
SPRD_DMA_SRC_CHN0,
|
||||
SPRD_DMA_SRC_CHN1,
|
||||
SPRD_DMA_DST_CHN0,
|
||||
SPRD_DMA_DST_CHN1,
|
||||
};
|
||||
|
||||
/*
|
||||
* enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
|
||||
* transfer
|
||||
* @SPRD_DMA_NO_TRG: No trigger setting.
|
||||
* @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
|
||||
* automatically once the source channel's fragment request is done.
|
||||
* @SPRD_DMA_BLOCK_DONE_TRG: Trigger the transaction of destination channel
|
||||
* automatically once the source channel's block request is done.
|
||||
* @SPRD_DMA_TRANS_DONE_TRG: Trigger the transaction of destination channel
|
||||
* automatically once the source channel's transfer request is done.
|
||||
* @SPRD_DMA_LIST_DONE_TRG: Trigger the transaction of destination channel
|
||||
* automatically once the source channel's link-list request is done.
|
||||
*/
|
||||
enum sprd_dma_trg_mode {
|
||||
SPRD_DMA_NO_TRG,
|
||||
SPRD_DMA_FRAG_DONE_TRG,
|
||||
SPRD_DMA_BLOCK_DONE_TRG,
|
||||
SPRD_DMA_TRANS_DONE_TRG,
|
||||
SPRD_DMA_LIST_DONE_TRG,
|
||||
};
|
||||
|
||||
/*
|
||||
* enum sprd_dma_req_mode: define the DMA request mode
|
||||
* @SPRD_DMA_FRAG_REQ: fragment request mode
|
||||
* @SPRD_DMA_BLK_REQ: block request mode
|
||||
* @SPRD_DMA_TRANS_REQ: transaction request mode
|
||||
* @SPRD_DMA_LIST_REQ: link-list request mode
|
||||
*
|
||||
* We have 4 types request mode: fragment mode, block mode, transaction mode
|
||||
* and linklist mode. One transaction can contain several blocks, one block can
|
||||
* contain several fragments. Link-list mode means we can save several DMA
|
||||
* configuration into one reserved memory, then DMA can fetch each DMA
|
||||
* configuration automatically to start transfer.
|
||||
*/
|
||||
enum sprd_dma_req_mode {
|
||||
SPRD_DMA_FRAG_REQ,
|
||||
SPRD_DMA_BLK_REQ,
|
||||
SPRD_DMA_TRANS_REQ,
|
||||
SPRD_DMA_LIST_REQ,
|
||||
};
|
||||
|
||||
/*
|
||||
* enum sprd_dma_int_type: define the DMA interrupt type
|
||||
* @SPRD_DMA_NO_INT: do not need generate DMA interrupts.
|
||||
* @SPRD_DMA_FRAG_INT: fragment done interrupt when one fragment request
|
||||
* is done.
|
||||
* @SPRD_DMA_BLK_INT: block done interrupt when one block request is done.
|
||||
* @SPRD_DMA_BLK_FRAG_INT: block and fragment interrupt when one fragment
|
||||
* or one block request is done.
|
||||
* @SPRD_DMA_TRANS_INT: tansaction done interrupt when one transaction
|
||||
* request is done.
|
||||
* @SPRD_DMA_TRANS_FRAG_INT: transaction and fragment interrupt when one
|
||||
* transaction request or fragment request is done.
|
||||
* @SPRD_DMA_TRANS_BLK_INT: transaction and block interrupt when one
|
||||
* transaction request or block request is done.
|
||||
* @SPRD_DMA_LIST_INT: link-list done interrupt when one link-list request
|
||||
* is done.
|
||||
* @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
|
||||
* incorrect.
|
||||
*/
|
||||
enum sprd_dma_int_type {
|
||||
SPRD_DMA_NO_INT,
|
||||
SPRD_DMA_FRAG_INT,
|
||||
SPRD_DMA_BLK_INT,
|
||||
SPRD_DMA_BLK_FRAG_INT,
|
||||
SPRD_DMA_TRANS_INT,
|
||||
SPRD_DMA_TRANS_FRAG_INT,
|
||||
SPRD_DMA_TRANS_BLK_INT,
|
||||
SPRD_DMA_LIST_INT,
|
||||
SPRD_DMA_CFGERR_INT,
|
||||
};
|
||||
|
||||
/*
|
||||
* struct sprd_dma_linklist - DMA link-list address structure
|
||||
* @virt_addr: link-list virtual address to configure link-list node
|
||||
* @phy_addr: link-list physical address to link DMA transfer
|
||||
* @wrap_addr: the wrap address for link-list mode, which means once the
|
||||
* transfer address reaches the wrap address, the next transfer address
|
||||
* will jump to the address specified by wrap_to register.
|
||||
*
|
||||
* The Spreadtrum DMA controller supports the link-list mode, that means slaves
|
||||
* can supply several groups configurations (each configuration represents one
|
||||
* DMA transfer) saved in memory, and DMA controller will link these groups
|
||||
* configurations by writing the physical address of each configuration into the
|
||||
* link-list register.
|
||||
*
|
||||
* Just as shown below, the link-list pointer register will be pointed to the
|
||||
* physical address of 'configuration 1', and the 'configuration 1' link-list
|
||||
* pointer will be pointed to 'configuration 2', and so on.
|
||||
* Once trigger the DMA transfer, the DMA controller will load 'configuration
|
||||
* 1' to its registers automatically, after 'configuration 1' transaction is
|
||||
* done, DMA controller will load 'configuration 2' automatically, until all
|
||||
* DMA transactions are done.
|
||||
*
|
||||
* Note: The last link-list pointer should point to the physical address
|
||||
* of 'configuration 1', which can avoid DMA controller loads incorrect
|
||||
* configuration when the last configuration transaction is done.
|
||||
*
|
||||
* DMA controller linklist memory
|
||||
* ====================== -----------------------
|
||||
*| | | configuration 1 |<---
|
||||
*| DMA controller | ------->| | |
|
||||
*| | | | | |
|
||||
*| | | | | |
|
||||
*| | | | | |
|
||||
*| linklist pointer reg |---- ----| linklist pointer | |
|
||||
* ====================== | ----------------------- |
|
||||
* | |
|
||||
* | ----------------------- |
|
||||
* | | configuration 2 | |
|
||||
* --->| | |
|
||||
* | | |
|
||||
* | | |
|
||||
* | | |
|
||||
* ----| linklist pointer | |
|
||||
* | ----------------------- |
|
||||
* | |
|
||||
* | ----------------------- |
|
||||
* | | configuration 3 | |
|
||||
* --->| | |
|
||||
* | | |
|
||||
* | . | |
|
||||
* . |
|
||||
* . |
|
||||
* . |
|
||||
* | . |
|
||||
* | ----------------------- |
|
||||
* | | configuration n | |
|
||||
* --->| | |
|
||||
* | | |
|
||||
* | | |
|
||||
* | | |
|
||||
* | linklist pointer |----
|
||||
* -----------------------
|
||||
*
|
||||
* To support the link-list mode, DMA slaves should allocate one segment memory
|
||||
* from always-on IRAM or dma coherent memory to store these groups of DMA
|
||||
* configuration, and pass the virtual and physical address to DMA controller.
|
||||
*/
|
||||
struct sprd_dma_linklist {
|
||||
unsigned long virt_addr;
|
||||
phys_addr_t phy_addr;
|
||||
phys_addr_t wrap_addr;
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,45 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Xilinx DMA Engine drivers support header file
|
||||
*
|
||||
* Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __DMA_XILINX_DMA_H
|
||||
#define __DMA_XILINX_DMA_H
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
/**
|
||||
* struct xilinx_vdma_config - VDMA Configuration structure
|
||||
* @frm_dly: Frame delay
|
||||
* @gen_lock: Whether in gen-lock mode
|
||||
* @master: Master that it syncs to
|
||||
* @frm_cnt_en: Enable frame count enable
|
||||
* @park: Whether wants to park
|
||||
* @park_frm: Frame to park on
|
||||
* @coalesc: Interrupt coalescing threshold
|
||||
* @delay: Delay counter
|
||||
* @reset: Reset Channel
|
||||
* @ext_fsync: External Frame Sync source
|
||||
* @vflip_en: Vertical Flip enable
|
||||
*/
|
||||
struct xilinx_vdma_config {
|
||||
int frm_dly;
|
||||
int gen_lock;
|
||||
int master;
|
||||
int frm_cnt_en;
|
||||
int park;
|
||||
int park_frm;
|
||||
int coalesc;
|
||||
int delay;
|
||||
int reset;
|
||||
int ext_fsync;
|
||||
bool vflip_en;
|
||||
};
|
||||
|
||||
int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
|
||||
struct xilinx_vdma_config *cfg);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_DMA_XILINX_DPDMA_H
|
||||
#define __LINUX_DMA_XILINX_DPDMA_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct xilinx_dpdma_peripheral_config {
|
||||
bool video_group;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_DMA_XILINX_DPDMA_H */
|
||||
Reference in New Issue
Block a user