restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
@@ -0,0 +1,79 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2019 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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*/
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#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
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#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
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#include <linux/types.h>
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/* DIVQ_VALUES: number of valid DIVQ values */
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#define DIVQ_VALUES 6
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/*
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* Bit definitions for struct wrpll_cfg.flags
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*
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* WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
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* programmed to enter bypass
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* WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
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* WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
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* feedback mode
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* WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
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* feedback mode (not yet supported by this driver)
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*/
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#define WRPLL_FLAGS_BYPASS_SHIFT 0
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#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
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#define WRPLL_FLAGS_RESET_SHIFT 1
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#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
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#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
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#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
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#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
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#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
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/**
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* struct wrpll_cfg - WRPLL configuration values
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* @divr: reference divider value (6 bits), as presented to the PLL signals
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* @divf: feedback divider value (9 bits), as presented to the PLL signals
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* @divq: output divider value (3 bits), as presented to the PLL signals
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* @flags: PLL configuration flags. See above for more information
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* @range: PLL loop filter range. See below for more information
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* @output_rate_cache: cached output rates, swept across DIVQ
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* @parent_rate: PLL refclk rate for which values are valid
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* @max_r: maximum possible R divider value, given @parent_rate
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* @init_r: initial R divider value to start the search from
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*
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* @divr, @divq, @divq, @range represent what the PLL expects to see
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* on its input signals. Thus @divr and @divf are the actual divisors
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* minus one. @divq is a power-of-two divider; for example, 1 =
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* divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
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*
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* When initially passing a struct wrpll_cfg record, the
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* record should be zero-initialized with the exception of the @flags
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* field. The only flag bits that need to be set are either
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* WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
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*/
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struct wrpll_cfg {
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u8 divr;
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u8 divq;
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u8 range;
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u8 flags;
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u16 divf;
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/* private: */
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u32 output_rate_cache[DIVQ_VALUES];
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unsigned long parent_rate;
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u8 max_r;
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u8 init_r;
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};
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int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
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unsigned long parent_rate);
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unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
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unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
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unsigned long parent_rate);
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#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
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@@ -0,0 +1,276 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/linux/clk/at91_pmc.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Power Management Controller (PMC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*/
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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#include <linux/bits.h>
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#define AT91_PMC_V1 (1) /* PMC version 1 */
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#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */
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#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
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#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
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#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
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#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
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#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
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#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
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#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
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#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
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#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
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#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
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#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
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#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
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#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
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#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
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#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
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#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
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#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
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#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */
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#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
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#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */
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#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */
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#define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */
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#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
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#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */
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#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_PMC_KEY_MASK (0xff << 16)
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#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
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#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
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#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
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#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
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#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
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#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */
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#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */
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#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
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#define AT91_PMC_DIV (0xff << 0) /* Divider */
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
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#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
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#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff)
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#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
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#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f)
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#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
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#define AT91_PMC_USBDIV_1 (0 << 28)
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#define AT91_PMC_USBDIV_2 (1 << 28)
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#define AT91_PMC_USBDIV_4 (2 << 28)
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */
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#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
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#define AT91_PMC_CSS_SLOW (0 << 0)
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#define AT91_PMC_CSS_MAIN (1 << 0)
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#define AT91_PMC_CSS_PLLA (2 << 0)
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#define AT91_PMC_CSS_PLLB (3 << 0)
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#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
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#define PMC_PRES_OFFSET 2
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#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
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#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET)
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#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET)
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#define PMC_ALT_PRES_OFFSET 4
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#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */
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#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET)
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
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#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
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#define AT91RM9200_PMC_MDIV_2 (1 << 8)
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#define AT91RM9200_PMC_MDIV_3 (2 << 8)
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#define AT91RM9200_PMC_MDIV_4 (3 << 8)
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#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
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#define AT91SAM9_PMC_MDIV_2 (1 << 8)
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#define AT91SAM9_PMC_MDIV_4 (2 << 8)
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#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
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#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
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#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
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#define AT91_PMC_PDIV_1 (0 << 12)
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#define AT91_PMC_PDIV_2 (1 << 12)
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#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
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#define AT91_PMC_PLLADIV2_OFF (0 << 12)
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#define AT91_PMC_PLLADIV2_ON (1 << 12)
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#define AT91_PMC_H32MXDIV BIT(24)
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#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
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#define AT91_PMC_MCR_V2_ID_MSK (0xF)
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#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK)
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#define AT91_PMC_MCR_V2_CMD (1 << 7)
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#define AT91_PMC_MCR_V2_DIV (7 << 8)
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#define AT91_PMC_MCR_V2_DIV1 (0 << 8)
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#define AT91_PMC_MCR_V2_DIV2 (1 << 8)
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#define AT91_PMC_MCR_V2_DIV4 (2 << 8)
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#define AT91_PMC_MCR_V2_DIV8 (3 << 8)
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#define AT91_PMC_MCR_V2_DIV16 (4 << 8)
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#define AT91_PMC_MCR_V2_DIV32 (5 << 8)
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#define AT91_PMC_MCR_V2_DIV64 (6 << 8)
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#define AT91_PMC_MCR_V2_DIV3 (7 << 8)
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#define AT91_PMC_MCR_V2_CSS (0x1F << 16)
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#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16)
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#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16)
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#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16)
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#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16)
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#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16)
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#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16)
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#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16)
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#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16)
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#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16)
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#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16)
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#define AT91_PMC_MCR_V2_EN (1 << 28)
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#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
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#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
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#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
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#define AT91_PMC_USBS_PLLA (0 << 0)
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#define AT91_PMC_USBS_UPLL (1 << 0)
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#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
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#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
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#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8)
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#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8)
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#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
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#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
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#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
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#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
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#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
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#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
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||||
#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
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||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
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#define AT91_PMC_CSSMCK_CSS (0 << 8)
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#define AT91_PMC_CSSMCK_MCK (1 << 8)
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||||
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#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
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||||
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR 0x68 /* Status Register */
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */
|
||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
|
||||
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
|
||||
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
|
||||
#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */
|
||||
#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */
|
||||
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */
|
||||
#define AT91_PMC_FSTT(n) BIT(n)
|
||||
#define AT91_PMC_RTTAL BIT(16)
|
||||
#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
|
||||
#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
|
||||
#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */
|
||||
#define AT91_PMC_LPM BIT(20) /* Low-power Mode */
|
||||
#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */
|
||||
#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */
|
||||
|
||||
#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */
|
||||
|
||||
#define AT91_PMC_FS_INPUT_MASK 0x7ff
|
||||
|
||||
#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
|
||||
|
||||
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
|
||||
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
|
||||
#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
|
||||
#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
|
||||
|
||||
#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
|
||||
#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
|
||||
#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
|
||||
|
||||
#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */
|
||||
|
||||
#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
|
||||
#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */
|
||||
#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
|
||||
|
||||
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
|
||||
#define AT91_PMC_PCR_PID_MASK 0x3f
|
||||
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
|
||||
#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20)
|
||||
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
|
||||
#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
|
||||
|
||||
#define AT91_PMC_AUDIO_PLL0 0x14c
|
||||
#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0)
|
||||
#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1)
|
||||
#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2)
|
||||
#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3)
|
||||
#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8
|
||||
#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
|
||||
#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
|
||||
|
||||
#define AT91_PMC_AUDIO_PLL1 0x150
|
||||
#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
|
||||
#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
|
||||
* Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*/
|
||||
|
||||
#ifndef __CLK_CONF_H
|
||||
#define __CLK_CONF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct device_node;
|
||||
|
||||
#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
|
||||
int of_clk_set_defaults(struct device_node *node, bool clk_supplier);
|
||||
#else
|
||||
static inline int of_clk_set_defaults(struct device_node *node,
|
||||
bool clk_supplier)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CLK_CONF_H */
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Clock drivers for TI DaVinci PLL and PSC controllers
|
||||
*
|
||||
* Copyright (C) 2018 David Lechner <david@lechnology.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_DAVINCI_PLL_H___
|
||||
#define __LINUX_CLK_DAVINCI_PLL_H___
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* function for registering clocks in early boot */
|
||||
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
|
||||
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Lee Jones <lee.jones@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_IMX_H
|
||||
#define __LINUX_CLK_IMX_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
void imx6sl_set_wait_clk(bool enter);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_MXS_H
|
||||
#define __LINUX_CLK_MXS_H
|
||||
|
||||
int mxs_saif_clkmux_select(unsigned int clkmux);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
extern int pxa25x_clocks_init(void __iomem *regs);
|
||||
extern int pxa27x_clocks_init(void __iomem *regs);
|
||||
extern int pxa3xx_clocks_init(void __iomem *regs, void __iomem *oscc_reg);
|
||||
|
||||
#ifdef CONFIG_PXA3xx
|
||||
extern unsigned pxa3xx_get_clk_frequency_khz(int);
|
||||
extern void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask);
|
||||
#else
|
||||
#define pxa3xx_get_clk_frequency_khz(x) (0)
|
||||
#define pxa3xx_clk_update_accr(disable, enable, xclkcfg, mask) do { } while (0)
|
||||
#endif
|
||||
@@ -0,0 +1,191 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
* Copyright 2013, 2014 Horms Solutions Ltd.
|
||||
*
|
||||
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
* Contact: Simon Horman <horms@verge.net.au>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_RENESAS_H_
|
||||
#define __LINUX_CLK_RENESAS_H_
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
struct device;
|
||||
struct device_node;
|
||||
struct generic_pm_domain;
|
||||
|
||||
void cpg_mstp_add_clk_domain(struct device_node *np);
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSTP
|
||||
int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
#define cpg_mstp_attach_dev NULL
|
||||
#define cpg_mstp_detach_dev NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CLK_RENESAS_CPG_MSSR
|
||||
int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev);
|
||||
#else
|
||||
#define cpg_mssr_attach_dev NULL
|
||||
#define cpg_mssr_detach_dev NULL
|
||||
#endif
|
||||
|
||||
enum {
|
||||
PLL5_TARGET_DPI,
|
||||
PLL5_TARGET_DSI
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CLK_RZG2L
|
||||
void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target);
|
||||
#else
|
||||
static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { }
|
||||
#endif
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_limits - PLL parameter constraints
|
||||
*
|
||||
* This structure defines the minimum and maximum allowed values for
|
||||
* various parameters used to configure a PLL. These limits ensure
|
||||
* the PLL operates within valid and stable ranges.
|
||||
*
|
||||
* @fout: Output frequency range (in MHz)
|
||||
* @fout.min: Minimum allowed output frequency
|
||||
* @fout.max: Maximum allowed output frequency
|
||||
*
|
||||
* @fvco: PLL oscillation frequency range (in MHz)
|
||||
* @fvco.min: Minimum allowed VCO frequency
|
||||
* @fvco.max: Maximum allowed VCO frequency
|
||||
*
|
||||
* @m: Main-divider range
|
||||
* @m.min: Minimum main-divider value
|
||||
* @m.max: Maximum main-divider value
|
||||
*
|
||||
* @p: Pre-divider range
|
||||
* @p.min: Minimum pre-divider value
|
||||
* @p.max: Maximum pre-divider value
|
||||
*
|
||||
* @s: Divider range
|
||||
* @s.min: Minimum divider value
|
||||
* @s.max: Maximum divider value
|
||||
*
|
||||
* @k: Delta-sigma modulator range (signed)
|
||||
* @k.min: Minimum delta-sigma value
|
||||
* @k.max: Maximum delta-sigma value
|
||||
*/
|
||||
struct rzv2h_pll_limits {
|
||||
struct {
|
||||
u32 min;
|
||||
u32 max;
|
||||
} fout;
|
||||
|
||||
struct {
|
||||
u32 min;
|
||||
u32 max;
|
||||
} fvco;
|
||||
|
||||
struct {
|
||||
u16 min;
|
||||
u16 max;
|
||||
} m;
|
||||
|
||||
struct {
|
||||
u8 min;
|
||||
u8 max;
|
||||
} p;
|
||||
|
||||
struct {
|
||||
u8 min;
|
||||
u8 max;
|
||||
} s;
|
||||
|
||||
struct {
|
||||
s16 min;
|
||||
s16 max;
|
||||
} k;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_pars - PLL configuration parameters
|
||||
*
|
||||
* This structure contains the configuration parameters for the
|
||||
* Phase-Locked Loop (PLL), used to achieve a specific output frequency.
|
||||
*
|
||||
* @m: Main divider value
|
||||
* @p: Pre-divider value
|
||||
* @s: Output divider value
|
||||
* @k: Delta-sigma modulation value
|
||||
* @freq_millihz: Calculated PLL output frequency in millihertz
|
||||
* @error_millihz: Frequency error from target in millihertz (signed)
|
||||
*/
|
||||
struct rzv2h_pll_pars {
|
||||
u16 m;
|
||||
u8 p;
|
||||
u8 s;
|
||||
s16 k;
|
||||
u64 freq_millihz;
|
||||
s64 error_millihz;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_div_pars - PLL parameters with post-divider
|
||||
*
|
||||
* This structure is used for PLLs that include an additional post-divider
|
||||
* stage after the main PLL block. It contains both the PLL configuration
|
||||
* parameters and the resulting frequency/error values after the divider.
|
||||
*
|
||||
* @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars)
|
||||
*
|
||||
* @div: Post-divider configuration and result
|
||||
* @div.divider_value: Divider applied to the PLL output
|
||||
* @div.freq_millihz: Output frequency after divider in millihertz
|
||||
* @div.error_millihz: Frequency error from target in millihertz (signed)
|
||||
*/
|
||||
struct rzv2h_pll_div_pars {
|
||||
struct rzv2h_pll_pars pll;
|
||||
struct {
|
||||
u8 divider_value;
|
||||
u64 freq_millihz;
|
||||
s64 error_millihz;
|
||||
} div;
|
||||
};
|
||||
|
||||
#define RZV2H_CPG_PLL_DSI_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 375 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#ifdef CONFIG_CLK_RZV2H
|
||||
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars, u64 freq_millihz);
|
||||
|
||||
bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_div_pars *pars,
|
||||
const u8 *table, u8 table_size, u64 freq_millihz);
|
||||
#else
|
||||
static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars,
|
||||
u64 freq_millihz)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_div_pars *pars,
|
||||
const u8 *table, u8 table_size,
|
||||
u64 freq_millihz)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_SAMSUNG_H_
|
||||
#define __LINUX_CLK_SAMSUNG_H_
|
||||
|
||||
#include <linux/compiler_types.h>
|
||||
|
||||
struct device_node;
|
||||
|
||||
#ifdef CONFIG_S3C64XX_COMMON_CLK
|
||||
void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
||||
unsigned long xusbxti_f, bool s3c6400,
|
||||
void __iomem *base);
|
||||
#else
|
||||
static inline void s3c64xx_clk_init(struct device_node *np,
|
||||
unsigned long xtal_f,
|
||||
unsigned long xusbxti_f,
|
||||
bool s3c6400, void __iomem *base) { }
|
||||
#endif /* CONFIG_S3C64XX_COMMON_CLK */
|
||||
|
||||
#endif /* __LINUX_CLK_SAMSUNG_H_ */
|
||||
@@ -0,0 +1,37 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2020 STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* Author: Lee Jones <lee.jones@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_SPEAR_H
|
||||
#define __LINUX_CLK_SPEAR_H
|
||||
|
||||
#ifdef CONFIG_ARCH_SPEAR3XX
|
||||
void __init spear3xx_clk_init(void __iomem *misc_base,
|
||||
void __iomem *soc_config_base);
|
||||
#else
|
||||
static inline void __init spear3xx_clk_init(void __iomem *misc_base,
|
||||
void __iomem *soc_config_base) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_SPEAR6XX
|
||||
void __init spear6xx_clk_init(void __iomem *misc_base);
|
||||
#else
|
||||
static inline void __init spear6xx_clk_init(void __iomem *misc_base) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR1310
|
||||
void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
|
||||
#else
|
||||
static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR1340
|
||||
void __init spear1340_clk_init(void __iomem *misc_base);
|
||||
#else
|
||||
static inline void spear1340_clk_init(void __iomem *misc_base) {}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_CLK_SUNXI_NG_H_
|
||||
#define _LINUX_CLK_SUNXI_NG_H_
|
||||
|
||||
int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode);
|
||||
int sunxi_ccu_get_mmc_timing_mode(struct clk *clk);
|
||||
|
||||
int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,263 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2012-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_TEGRA_H_
|
||||
#define __LINUX_CLK_TEGRA_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
/*
|
||||
* Tegra CPU clock and reset control ops
|
||||
*
|
||||
* wait_for_reset:
|
||||
* keep waiting until the CPU in reset state
|
||||
* put_in_reset:
|
||||
* put the CPU in reset state
|
||||
* out_of_reset:
|
||||
* release the CPU from reset state
|
||||
* enable_clock:
|
||||
* CPU clock un-gate
|
||||
* disable_clock:
|
||||
* CPU clock gate
|
||||
* rail_off_ready:
|
||||
* CPU is ready for rail off
|
||||
* suspend:
|
||||
* save the clock settings when CPU go into low-power state
|
||||
* resume:
|
||||
* restore the clock settings when CPU exit low-power state
|
||||
*/
|
||||
struct tegra_cpu_car_ops {
|
||||
void (*wait_for_reset)(u32 cpu);
|
||||
void (*put_in_reset)(u32 cpu);
|
||||
void (*out_of_reset)(u32 cpu);
|
||||
void (*enable_clock)(u32 cpu);
|
||||
void (*disable_clock)(u32 cpu);
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
bool (*rail_off_ready)(void);
|
||||
void (*suspend)(void);
|
||||
void (*resume)(void);
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA
|
||||
extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
|
||||
|
||||
static inline void tegra_wait_cpu_in_reset(u32 cpu)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->wait_for_reset(cpu);
|
||||
}
|
||||
|
||||
static inline void tegra_put_cpu_in_reset(u32 cpu)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->put_in_reset(cpu);
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_out_of_reset(u32 cpu)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->out_of_reset(cpu);
|
||||
}
|
||||
|
||||
static inline void tegra_enable_cpu_clock(u32 cpu)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->enable_clock(cpu);
|
||||
}
|
||||
|
||||
static inline void tegra_disable_cpu_clock(u32 cpu)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->disable_clock(cpu);
|
||||
}
|
||||
#else
|
||||
static inline void tegra_wait_cpu_in_reset(u32 cpu)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tegra_put_cpu_in_reset(u32 cpu)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_out_of_reset(u32 cpu)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tegra_enable_cpu_clock(u32 cpu)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tegra_disable_cpu_clock(u32 cpu)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_PM_SLEEP)
|
||||
static inline bool tegra_cpu_rail_off_ready(void)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
|
||||
return false;
|
||||
|
||||
return tegra_cpu_car_ops->rail_off_ready();
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_clock_suspend(void)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->suspend))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->suspend();
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_clock_resume(void)
|
||||
{
|
||||
if (WARN_ON(!tegra_cpu_car_ops->resume))
|
||||
return;
|
||||
|
||||
tegra_cpu_car_ops->resume();
|
||||
}
|
||||
#else
|
||||
static inline bool tegra_cpu_rail_off_ready(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_clock_suspend(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void tegra_cpu_clock_resume(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
struct clk;
|
||||
struct tegra_emc;
|
||||
|
||||
typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
|
||||
unsigned long min_rate,
|
||||
unsigned long max_rate,
|
||||
void *arg);
|
||||
typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
|
||||
unsigned long rate);
|
||||
typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
|
||||
unsigned long rate);
|
||||
|
||||
struct tegra210_clk_emc_config {
|
||||
unsigned long rate;
|
||||
bool same_freq;
|
||||
u32 value;
|
||||
|
||||
unsigned long parent_rate;
|
||||
u8 parent;
|
||||
};
|
||||
|
||||
struct tegra210_clk_emc_provider {
|
||||
struct module *owner;
|
||||
struct device *dev;
|
||||
|
||||
struct tegra210_clk_emc_config *configs;
|
||||
unsigned int num_configs;
|
||||
|
||||
int (*set_rate)(struct device *dev,
|
||||
const struct tegra210_clk_emc_config *config);
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
|
||||
void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
|
||||
void *cb_arg);
|
||||
int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
|
||||
#else
|
||||
static inline void
|
||||
tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
|
||||
void *cb_arg)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int
|
||||
tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TEGRA124_CLK_EMC
|
||||
void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
|
||||
tegra124_emc_complete_timing_change_cb *complete_cb);
|
||||
#else
|
||||
static inline void
|
||||
tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
|
||||
tegra124_emc_complete_timing_change_cb *complete_cb)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_210_SOC
|
||||
int tegra210_plle_hw_sequence_start(void);
|
||||
bool tegra210_plle_hw_sequence_is_enabled(void);
|
||||
void tegra210_xusb_pll_hw_control_enable(void);
|
||||
void tegra210_xusb_pll_hw_sequence_start(void);
|
||||
void tegra210_sata_pll_hw_control_enable(void);
|
||||
void tegra210_sata_pll_hw_sequence_start(void);
|
||||
void tegra210_set_sata_pll_seq_sw(bool state);
|
||||
void tegra210_put_utmipll_in_iddq(void);
|
||||
void tegra210_put_utmipll_out_iddq(void);
|
||||
int tegra210_clk_handle_mbist_war(unsigned int id);
|
||||
void tegra210_clk_emc_dll_enable(bool flag);
|
||||
void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
|
||||
void tegra210_clk_emc_update_setting(u32 emc_src_value);
|
||||
|
||||
int tegra210_clk_emc_attach(struct clk *clk,
|
||||
struct tegra210_clk_emc_provider *provider);
|
||||
void tegra210_clk_emc_detach(struct clk *clk);
|
||||
#else
|
||||
static inline int tegra210_plle_hw_sequence_start(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool tegra210_plle_hw_sequence_is_enabled(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int tegra210_clk_handle_mbist_war(unsigned int id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
tegra210_clk_emc_attach(struct clk *clk,
|
||||
struct tegra210_clk_emc_provider *provider)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void tegra210_xusb_pll_hw_control_enable(void) {}
|
||||
static inline void tegra210_xusb_pll_hw_sequence_start(void) {}
|
||||
static inline void tegra210_sata_pll_hw_control_enable(void) {}
|
||||
static inline void tegra210_sata_pll_hw_sequence_start(void) {}
|
||||
static inline void tegra210_set_sata_pll_seq_sw(bool state) {}
|
||||
static inline void tegra210_put_utmipll_in_iddq(void) {}
|
||||
static inline void tegra210_put_utmipll_out_iddq(void) {}
|
||||
static inline void tegra210_clk_emc_dll_enable(bool flag) {}
|
||||
static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}
|
||||
static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}
|
||||
static inline void tegra210_clk_emc_detach(struct clk *clk) {}
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_CLK_TEGRA_H_ */
|
||||
@@ -0,0 +1,340 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* TI clock drivers support
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*/
|
||||
#ifndef __LINUX_CLK_TI_H__
|
||||
#define __LINUX_CLK_TI_H__
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
/**
|
||||
* struct clk_omap_reg - OMAP register declaration
|
||||
* @offset: offset from the master IP module base address
|
||||
* @bit: register bit offset
|
||||
* @index: index of the master IP module
|
||||
* @flags: flags
|
||||
*/
|
||||
struct clk_omap_reg {
|
||||
void __iomem *ptr;
|
||||
u16 offset;
|
||||
u8 bit;
|
||||
u8 index;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct dpll_data - DPLL registers and integration data
|
||||
* @mult_div1_reg: register containing the DPLL M and N bitfields
|
||||
* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
|
||||
* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
|
||||
* @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
|
||||
* @clk_ref: struct clk_hw pointer to the clock's reference clock input
|
||||
* @control_reg: register containing the DPLL mode bitfield
|
||||
* @enable_mask: mask of the DPLL mode bitfield in @control_reg
|
||||
* @last_rounded_rate: cache of the last rate result of omap2_dpll_determine_rate()
|
||||
* @last_rounded_m: cache of the last M result of omap2_dpll_determine_rate()
|
||||
* @last_rounded_m4xen: cache of the last M4X result of
|
||||
* omap4_dpll_regm4xen_determine_rate()
|
||||
* @last_rounded_lpmode: cache of the last lpmode result of
|
||||
* omap4_dpll_lpmode_recalc()
|
||||
* @max_multiplier: maximum valid non-bypass multiplier value (actual)
|
||||
* @last_rounded_n: cache of the last N result of omap2_dpll_determine_rate()
|
||||
* @min_divider: minimum valid non-bypass divider value (actual)
|
||||
* @max_divider: maximum valid non-bypass divider value (actual)
|
||||
* @max_rate: maximum clock rate for the DPLL
|
||||
* @modes: possible values of @enable_mask
|
||||
* @autoidle_reg: register containing the DPLL autoidle mode bitfield
|
||||
* @idlest_reg: register containing the DPLL idle status bitfield
|
||||
* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
|
||||
* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
|
||||
* @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
|
||||
* @dcc_rate: rate atleast which DCC @dcc_mask must be set
|
||||
* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
|
||||
* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
|
||||
* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
|
||||
* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
|
||||
* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
|
||||
* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
|
||||
* @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
|
||||
* @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
|
||||
* @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
|
||||
* @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
|
||||
* @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
|
||||
* @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
|
||||
* @control_reg
|
||||
* @ssc_modfreq: the DPLL SSC frequency modulation in kHz
|
||||
* @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
|
||||
* @ssc_downspread: require the only low frequency spread of the DPLL in SSC
|
||||
* mode
|
||||
* @flags: DPLL type/features (see below)
|
||||
*
|
||||
* Possible values for @flags:
|
||||
* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
|
||||
*
|
||||
* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
|
||||
*
|
||||
* XXX Some DPLLs have multiple bypass inputs, so it's not technically
|
||||
* correct to only have one @clk_bypass pointer.
|
||||
*
|
||||
* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
|
||||
* @last_rounded_n) should be separated from the runtime-fixed fields
|
||||
* and placed into a different structure, so that the runtime-fixed data
|
||||
* can be placed into read-only space.
|
||||
*/
|
||||
struct dpll_data {
|
||||
struct clk_omap_reg mult_div1_reg;
|
||||
u32 mult_mask;
|
||||
u32 div1_mask;
|
||||
struct clk_hw *clk_bypass;
|
||||
struct clk_hw *clk_ref;
|
||||
struct clk_omap_reg control_reg;
|
||||
u32 enable_mask;
|
||||
unsigned long last_rounded_rate;
|
||||
u16 last_rounded_m;
|
||||
u8 last_rounded_m4xen;
|
||||
u8 last_rounded_lpmode;
|
||||
u16 max_multiplier;
|
||||
u8 last_rounded_n;
|
||||
u8 min_divider;
|
||||
u16 max_divider;
|
||||
unsigned long max_rate;
|
||||
u8 modes;
|
||||
struct clk_omap_reg autoidle_reg;
|
||||
struct clk_omap_reg idlest_reg;
|
||||
u32 autoidle_mask;
|
||||
u32 freqsel_mask;
|
||||
u32 idlest_mask;
|
||||
u32 dco_mask;
|
||||
u32 sddiv_mask;
|
||||
u32 dcc_mask;
|
||||
unsigned long dcc_rate;
|
||||
u32 lpmode_mask;
|
||||
u32 m4xen_mask;
|
||||
u8 auto_recal_bit;
|
||||
u8 recal_en_bit;
|
||||
u8 recal_st_bit;
|
||||
struct clk_omap_reg ssc_deltam_reg;
|
||||
struct clk_omap_reg ssc_modfreq_reg;
|
||||
u32 ssc_deltam_int_mask;
|
||||
u32 ssc_deltam_frac_mask;
|
||||
u32 ssc_modfreq_mant_mask;
|
||||
u32 ssc_modfreq_exp_mask;
|
||||
u32 ssc_enable_mask;
|
||||
u32 ssc_downspread_mask;
|
||||
u32 ssc_modfreq;
|
||||
u32 ssc_deltam;
|
||||
bool ssc_downspread;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct clk_hw_omap;
|
||||
|
||||
/**
|
||||
* struct clk_hw_omap_ops - OMAP clk ops
|
||||
* @find_idlest: find idlest register information for a clock
|
||||
* @find_companion: find companion clock register information for a clock,
|
||||
* basically converts CM_ICLKEN* <-> CM_FCLKEN*
|
||||
* @allow_idle: enables autoidle hardware functionality for a clock
|
||||
* @deny_idle: prevent autoidle hardware functionality for a clock
|
||||
*/
|
||||
struct clk_hw_omap_ops {
|
||||
void (*find_idlest)(struct clk_hw_omap *oclk,
|
||||
struct clk_omap_reg *idlest_reg,
|
||||
u8 *idlest_bit, u8 *idlest_val);
|
||||
void (*find_companion)(struct clk_hw_omap *oclk,
|
||||
struct clk_omap_reg *other_reg,
|
||||
u8 *other_bit);
|
||||
void (*allow_idle)(struct clk_hw_omap *oclk);
|
||||
void (*deny_idle)(struct clk_hw_omap *oclk);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_hw_omap - OMAP struct clk
|
||||
* @node: list_head connecting this clock into the full clock list
|
||||
* @enable_reg: register to write to enable the clock (see @enable_bit)
|
||||
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
|
||||
* @flags: see "struct clk.flags possibilities" above
|
||||
* @clksel_reg: for clksel clks, register va containing src/divisor select
|
||||
* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
|
||||
* @clkdm_name: clockdomain name that this clock is contained in
|
||||
* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
|
||||
* @ops: clock ops for this clock
|
||||
*/
|
||||
struct clk_hw_omap {
|
||||
struct clk_hw hw;
|
||||
struct list_head node;
|
||||
unsigned long fixed_rate;
|
||||
u8 fixed_div;
|
||||
struct clk_omap_reg enable_reg;
|
||||
u8 enable_bit;
|
||||
unsigned long flags;
|
||||
struct clk_omap_reg clksel_reg;
|
||||
struct dpll_data *dpll_data;
|
||||
const char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
const struct clk_hw_omap_ops *ops;
|
||||
u32 context;
|
||||
int autoidle_count;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct clk_hw_omap.flags possibilities
|
||||
*
|
||||
* XXX document the rest of the clock flags here
|
||||
*
|
||||
* ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
|
||||
* with 32bit ops, by default OMAP1 uses 16bit ops.
|
||||
* CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
|
||||
* CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
|
||||
* clock is put to no-idle mode.
|
||||
* ENABLE_ON_INIT: Clock is enabled on init.
|
||||
* INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
|
||||
* disable. This inverts the behavior making '0' enable and '1' disable.
|
||||
* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
|
||||
* bits share the same register. This flag allows the
|
||||
* omap4_dpllmx*() code to determine which GATE_CTRL bit field
|
||||
* should be used. This is a temporary solution - a better approach
|
||||
* would be to associate clock type-specific data with the clock,
|
||||
* similar to the struct dpll_data approach.
|
||||
*/
|
||||
#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
|
||||
#define CLOCK_IDLE_CONTROL (1 << 1)
|
||||
#define CLOCK_NO_IDLE_PARENT (1 << 2)
|
||||
#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
|
||||
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
|
||||
#define CLOCK_CLKOUTX2 (1 << 5)
|
||||
|
||||
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
|
||||
#define DPLL_LOW_POWER_STOP 0x1
|
||||
#define DPLL_LOW_POWER_BYPASS 0x5
|
||||
#define DPLL_LOCKED 0x7
|
||||
|
||||
/* DPLL Type and DCO Selection Flags */
|
||||
#define DPLL_J_TYPE 0x1
|
||||
|
||||
/* Static memmap indices */
|
||||
enum {
|
||||
TI_CLKM_CM = 0,
|
||||
TI_CLKM_CM2,
|
||||
TI_CLKM_PRM,
|
||||
TI_CLKM_SCRM,
|
||||
TI_CLKM_CTRL,
|
||||
TI_CLKM_CTRL_AUX,
|
||||
TI_CLKM_PLLSS,
|
||||
CLK_MAX_MEMMAPS
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_clk_ll_ops - low-level ops for clocks
|
||||
* @clk_readl: pointer to register read function
|
||||
* @clk_writel: pointer to register write function
|
||||
* @clk_rmw: pointer to register read-modify-write function
|
||||
* @clkdm_clk_enable: pointer to clockdomain enable function
|
||||
* @clkdm_clk_disable: pointer to clockdomain disable function
|
||||
* @clkdm_lookup: pointer to clockdomain lookup function
|
||||
* @cm_wait_module_ready: pointer to CM module wait ready function
|
||||
* @cm_split_idlest_reg: pointer to CM module function to split idlest reg
|
||||
*
|
||||
* Low-level ops are generally used by the basic clock types (clk-gate,
|
||||
* clk-mux, clk-divider etc.) to provide support for various low-level
|
||||
* hadrware interfaces (direct MMIO, regmap etc.), and is initialized
|
||||
* by board code. Low-level ops also contain some other platform specific
|
||||
* operations not provided directly by clock drivers.
|
||||
*/
|
||||
struct ti_clk_ll_ops {
|
||||
u32 (*clk_readl)(const struct clk_omap_reg *reg);
|
||||
void (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
|
||||
void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
|
||||
int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
|
||||
int (*clkdm_clk_disable)(struct clockdomain *clkdm,
|
||||
struct clk *clk);
|
||||
struct clockdomain * (*clkdm_lookup)(const char *name);
|
||||
int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
|
||||
u8 idlest_shift);
|
||||
int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
|
||||
s16 *prcm_inst, u8 *idlest_reg_id);
|
||||
};
|
||||
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
bool omap2_clk_is_hw_omap(struct clk_hw *hw);
|
||||
int omap2_clk_disable_autoidle_all(void);
|
||||
int omap2_clk_enable_autoidle_all(void);
|
||||
int omap2_clk_allow_idle(struct clk *clk);
|
||||
int omap2_clk_deny_idle(struct clk *clk);
|
||||
unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
|
||||
void omap2xxx_clkt_vps_init(void);
|
||||
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
|
||||
|
||||
void ti_dt_clk_init_retry_clks(void);
|
||||
void ti_dt_clockdomains_setup(void);
|
||||
int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
|
||||
|
||||
struct regmap;
|
||||
|
||||
int omap2_clk_provider_init(struct device_node *parent, int index,
|
||||
struct regmap *syscon, void __iomem *mem);
|
||||
void omap2_clk_legacy_provider_init(int index, void __iomem *mem);
|
||||
|
||||
int omap3430_dt_clk_init(void);
|
||||
int omap3630_dt_clk_init(void);
|
||||
int am35xx_dt_clk_init(void);
|
||||
int dm814x_dt_clk_init(void);
|
||||
int dm816x_dt_clk_init(void);
|
||||
int omap4xxx_dt_clk_init(void);
|
||||
int omap5xxx_dt_clk_init(void);
|
||||
int dra7xx_dt_clk_init(void);
|
||||
int am33xx_dt_clk_init(void);
|
||||
int am43xx_dt_clk_init(void);
|
||||
int omap2420_dt_clk_init(void);
|
||||
int omap2430_dt_clk_init(void);
|
||||
|
||||
struct ti_clk_features {
|
||||
u32 flags;
|
||||
long fint_min;
|
||||
long fint_max;
|
||||
long fint_band1_max;
|
||||
long fint_band2_min;
|
||||
u8 dpll_bypass_vals;
|
||||
u8 cm_idlest_val;
|
||||
};
|
||||
|
||||
#define TI_CLK_DPLL_HAS_FREQSEL BIT(0)
|
||||
#define TI_CLK_DPLL4_DENY_REPROGRAM BIT(1)
|
||||
#define TI_CLK_DISABLE_CLKDM_CONTROL BIT(2)
|
||||
#define TI_CLK_ERRATA_I810 BIT(3)
|
||||
#define TI_CLK_CLKCTRL_COMPAT BIT(4)
|
||||
#define TI_CLK_DEVICE_TYPE_GP BIT(5)
|
||||
|
||||
void ti_clk_setup_features(struct ti_clk_features *features);
|
||||
const struct ti_clk_features *ti_clk_get_features(void);
|
||||
bool ti_clk_is_in_standby(struct clk *clk);
|
||||
int omap3_noncore_dpll_save_context(struct clk_hw *hw);
|
||||
void omap3_noncore_dpll_restore_context(struct clk_hw *hw);
|
||||
|
||||
int omap3_core_dpll_save_context(struct clk_hw *hw);
|
||||
void omap3_core_dpll_restore_context(struct clk_hw *hw);
|
||||
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
|
||||
|
||||
#ifdef CONFIG_ATAGS
|
||||
int omap3430_clk_legacy_init(void);
|
||||
int omap3430es1_clk_legacy_init(void);
|
||||
int omap36xx_clk_legacy_init(void);
|
||||
int am35xx_clk_legacy_init(void);
|
||||
#else
|
||||
static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
|
||||
static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
|
||||
static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
|
||||
static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2013 Xilinx Inc.
|
||||
* Copyright (C) 2012 National Instruments
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_ZYNQ_H_
|
||||
#define __LINUX_CLK_ZYNQ_H_
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
void zynq_clock_init(void);
|
||||
|
||||
struct clk *clk_register_zynq_pll(const char *name, const char *parent,
|
||||
void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
|
||||
spinlock_t *lock);
|
||||
#endif
|
||||
Reference in New Issue
Block a user