restore lost packages from 0.2.3 + fix overwritten 0.2.4 files
- Restore 29 recipe symlinks (libdrm, qtbase, dbus, sddm, pipewire, etc.) - Restore 33 patches (KDE, libdrm, mesa, pipewire, sddm, wireplumber) - Restore 20+ local/scripts (audit, lint, test, build helpers) - Restore src/cook/scheduler.rs, status.rs, gnu-config/ - Restore scripts/patch-inclusion-gate.sh, run_mini1.sh, validate-collision-log.sh - Recover TLC source from HEAD (was overwritten by 0.2.3 checkout) - Recover 11 local/docs plans from HEAD (were overwritten) - Recover qt6-wayland-smoke symlink from HEAD - Fix MOTD: remove garbled ASCII art, use clean text - Update version: 0.2.0 -> 0.2.4 in os-release, motd, config - Reduce filesystem_size: 1536 -> 512 MiB - Add ABSOLUTE RULE to AGENTS.md: never delete/ignore packages - Reduce pcid scheme log verbosity: info -> debug
This commit is contained in:
@@ -0,0 +1,209 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/include/amba/bus.h
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*
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* This device type deals with ARM PrimeCells and anything else that
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* presents a proper CID (0xB105F00D) at the end of the I/O register
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* region or that is derived from a PrimeCell.
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
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*/
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#ifndef ASMARM_AMBA_H
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#define ASMARM_AMBA_H
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/err.h>
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#include <linux/resource.h>
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#include <linux/regulator/consumer.h>
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#define AMBA_NR_IRQS 9
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#define AMBA_CID 0xb105f00d
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#define CORESIGHT_CID 0xb105900d
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/*
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* CoreSight Architecture specification updates the ID specification
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* for components on the AMBA bus. (ARM IHI 0029E)
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*
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* Bits 15:12 of the CID are the device class.
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*
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* Class 0xF remains for PrimeCell and legacy components. (AMBA_CID above)
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* Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
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* Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
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* at present.
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* Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
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*
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* Remaining CID bits stay as 0xb105-00d
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*/
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/**
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* Class 0x9 components use additional values to form a Unique Component
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* Identifier (UCI), where peripheral ID values are identical for different
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* components. Passed to the amba bus code from the component driver via
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* the amba_id->data pointer.
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* @devarch : coresight devarch register value
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* @devarch_mask: mask bits used for matching. 0 indicates UCI not used.
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* @devtype : coresight device type value
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* @data : additional driver data. As we have usurped the original
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* pointer some devices may still need additional data
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*/
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struct amba_cs_uci_id {
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unsigned int devarch;
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unsigned int devarch_mask;
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unsigned int devtype;
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void *data;
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};
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/* define offsets for registers used by UCI */
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#define UCI_REG_DEVTYPE_OFFSET 0xFCC
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#define UCI_REG_DEVARCH_OFFSET 0xFBC
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struct clk;
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struct amba_device {
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struct device dev;
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struct resource res;
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struct clk *pclk;
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struct device_dma_parameters dma_parms;
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unsigned int periphid;
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struct mutex periphid_lock;
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unsigned int cid;
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struct amba_cs_uci_id uci;
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unsigned int irq[AMBA_NR_IRQS];
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/*
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* Driver name to force a match. Do not set directly, because core
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* frees it. Use driver_set_override() to set or clear it.
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*/
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const char *driver_override;
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};
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struct amba_driver {
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struct device_driver drv;
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int (*probe)(struct amba_device *, const struct amba_id *);
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void (*remove)(struct amba_device *);
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void (*shutdown)(struct amba_device *);
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const struct amba_id *id_table;
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/*
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* For most device drivers, no need to care about this flag as long as
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* all DMAs are handled through the kernel DMA API. For some special
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* ones, for example VFIO drivers, they know how to manage the DMA
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* themselves and set this flag so that the IOMMU layer will allow them
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* to setup and manage their own I/O address space.
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*/
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bool driver_managed_dma;
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};
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/*
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* Constants for the designer field of the Peripheral ID register. When bit 7
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* is set to '1', bits [6:0] should be the JEP106 manufacturer identity code.
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*/
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enum amba_vendor {
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AMBA_VENDOR_ARM = 0x41,
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AMBA_VENDOR_ST = 0x80,
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AMBA_VENDOR_QCOM = 0x51,
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AMBA_VENDOR_LSI = 0xb6,
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};
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extern const struct bus_type amba_bustype;
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#define to_amba_device(d) container_of_const(d, struct amba_device, dev)
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#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
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#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
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/*
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* use a macro to avoid include chaining to get THIS_MODULE
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*/
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#define amba_driver_register(drv) \
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__amba_driver_register(drv, THIS_MODULE)
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#ifdef CONFIG_ARM_AMBA
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int __amba_driver_register(struct amba_driver *, struct module *);
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void amba_driver_unregister(struct amba_driver *);
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bool dev_is_amba(const struct device *dev);
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#else
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static inline int __amba_driver_register(struct amba_driver *drv,
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struct module *owner)
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{
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return -EINVAL;
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}
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static inline void amba_driver_unregister(struct amba_driver *drv)
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{
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}
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static inline bool dev_is_amba(const struct device *dev)
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{
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return false;
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}
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#endif
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struct amba_device *amba_device_alloc(const char *, resource_size_t, size_t);
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void amba_device_put(struct amba_device *);
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int amba_device_add(struct amba_device *, struct resource *);
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int amba_device_register(struct amba_device *, struct resource *);
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void amba_device_unregister(struct amba_device *);
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int amba_request_regions(struct amba_device *, const char *);
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void amba_release_regions(struct amba_device *);
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/* Some drivers don't use the struct amba_device */
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#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
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#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
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#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
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#define AMBA_PART_BITS(a) ((a) & 0xfff)
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#define amba_config(d) AMBA_CONFIG_BITS((d)->periphid)
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#define amba_rev(d) AMBA_REV_BITS((d)->periphid)
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#define amba_manf(d) AMBA_MANF_BITS((d)->periphid)
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#define amba_part(d) AMBA_PART_BITS((d)->periphid)
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#define __AMBA_DEV(busid, data, mask) \
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{ \
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.coherent_dma_mask = mask, \
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.init_name = busid, \
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.platform_data = data, \
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}
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/*
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* APB devices do not themselves have the ability to address memory,
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* so DMA masks should be zero (much like USB peripheral devices.)
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* The DMA controller DMA masks should be used instead (much like
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* USB host controllers in conventional PCs.)
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*/
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#define AMBA_APB_DEVICE(name, busid, id, base, irqs, data) \
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struct amba_device name##_device = { \
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.dev = __AMBA_DEV(busid, data, 0), \
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.res = DEFINE_RES_MEM(base, SZ_4K), \
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.irq = irqs, \
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.periphid = id, \
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}
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/*
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* AHB devices are DMA capable, so set their DMA masks
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*/
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#define AMBA_AHB_DEVICE(name, busid, id, base, irqs, data) \
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struct amba_device name##_device = { \
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.dev = __AMBA_DEV(busid, data, ~0ULL), \
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.res = DEFINE_RES_MEM(base, SZ_4K), \
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.irq = irqs, \
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.periphid = id, \
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}
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/*
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* module_amba_driver() - Helper macro for drivers that don't do anything
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* special in module init/exit. This eliminates a lot of boilerplate. Each
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* module may only use this macro once, and calling it replaces module_init()
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* and module_exit()
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*/
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#define module_amba_driver(__amba_drv) \
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module_driver(__amba_drv, amba_driver_register, amba_driver_unregister)
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/*
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* builtin_amba_driver() - Helper macro for drivers that don't do anything
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* special in driver initcall. This eliminates a lot of boilerplate. Each
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* driver may only use this macro once, and calling it replaces the instance
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* device_initcall().
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*/
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#define builtin_amba_driver(__amba_drv) \
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builtin_driver(__amba_drv, amba_driver_register)
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#endif
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@@ -0,0 +1,78 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/include/asm-arm/hardware/amba_kmi.h
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*
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* Internal header file for AMBA KMI ports
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* ---------------------------------------------------------------------------
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* From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
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* Reference Manual - ARM DDI 0143B - see http://www.arm.com/
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* ---------------------------------------------------------------------------
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*/
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#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
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#define ASM_ARM_HARDWARE_AMBA_KMI_H
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/*
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* KMI control register:
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* KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
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* KMICR_RXINTREN 1 = enable RX interrupts
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* KMICR_TXINTREN 1 = enable TX interrupts
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* KMICR_EN 1 = enable KMI
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* KMICR_FD 1 = force KMI data low
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* KMICR_FC 1 = force KMI clock low
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*/
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#define KMICR (KMI_BASE + 0x00)
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#define KMICR_TYPE (1 << 5)
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#define KMICR_RXINTREN (1 << 4)
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#define KMICR_TXINTREN (1 << 3)
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#define KMICR_EN (1 << 2)
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#define KMICR_FD (1 << 1)
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#define KMICR_FC (1 << 0)
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/*
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* KMI status register:
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* KMISTAT_TXEMPTY 1 = transmitter register empty
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* KMISTAT_TXBUSY 1 = currently sending data
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* KMISTAT_RXFULL 1 = receiver register ready to be read
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* KMISTAT_RXBUSY 1 = currently receiving data
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* KMISTAT_RXPARITY parity of last databyte received
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* KMISTAT_IC current level of KMI clock input
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* KMISTAT_ID current level of KMI data input
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*/
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#define KMISTAT (KMI_BASE + 0x04)
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#define KMISTAT_TXEMPTY (1 << 6)
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#define KMISTAT_TXBUSY (1 << 5)
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#define KMISTAT_RXFULL (1 << 4)
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#define KMISTAT_RXBUSY (1 << 3)
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#define KMISTAT_RXPARITY (1 << 2)
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#define KMISTAT_IC (1 << 1)
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#define KMISTAT_ID (1 << 0)
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/*
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* KMI data register
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*/
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#define KMIDATA (KMI_BASE + 0x08)
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/*
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* KMI clock divisor: to generate 8MHz internal clock
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* div = (ref / 8MHz) - 1; 0 <= div <= 15
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*/
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#define KMICLKDIV (KMI_BASE + 0x0c)
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/*
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* KMI interrupt register:
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* KMIIR_TXINTR 1 = transmit interrupt asserted
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* KMIIR_RXINTR 1 = receive interrupt asserted
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*/
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#define KMIIR (KMI_BASE + 0x10)
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#define KMIIR_TXINTR (1 << 1)
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#define KMIIR_RXINTR (1 << 0)
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/*
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* The size of the KMI primecell
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*/
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#define KMI_SIZE (0x100)
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#endif
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@@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* include/linux/amba/mmci.h
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*/
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#ifndef AMBA_MMCI_H
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#define AMBA_MMCI_H
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#include <linux/mmc/host.h>
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/**
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* struct mmci_platform_data - platform configuration for the MMCI
|
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* (also known as PL180) block.
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* @ocr_mask: available voltages on the 4 pins from the block, this
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* is ignored if a regulator is used, see the MMC_VDD_* masks in
|
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* mmc/host.h
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* @status: if no GPIO line was given to the block in this function will
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* be called to determine whether a card is present in the MMC slot or not
|
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*/
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struct mmci_platform_data {
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unsigned int ocr_mask;
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unsigned int (*status)(struct device *);
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||||
};
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#endif
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@@ -0,0 +1,278 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
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/*
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* include/linux/amba/pl022.h
|
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*
|
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* Copyright (C) 2008-2009 ST-Ericsson AB
|
||||
* Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
|
||||
*
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
*
|
||||
* Initial version inspired by:
|
||||
* linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
|
||||
* Initial adoption to PL022 by:
|
||||
* Sachin Verma <sachin.verma@st.com>
|
||||
*/
|
||||
|
||||
#ifndef _SSP_PL022_H
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||||
#define _SSP_PL022_H
|
||||
|
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#include <linux/dmaengine.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* whether SSP is in loopback mode or not
|
||||
*/
|
||||
enum ssp_loopback {
|
||||
LOOPBACK_DISABLED,
|
||||
LOOPBACK_ENABLED
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_interface - interfaces allowed for this SSP Controller
|
||||
* @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
|
||||
* @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
|
||||
* interface
|
||||
* @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
|
||||
* interface
|
||||
* @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
|
||||
* &STn8815 only)
|
||||
*/
|
||||
enum ssp_interface {
|
||||
SSP_INTERFACE_MOTOROLA_SPI,
|
||||
SSP_INTERFACE_TI_SYNC_SERIAL,
|
||||
SSP_INTERFACE_NATIONAL_MICROWIRE,
|
||||
SSP_INTERFACE_UNIDIRECTIONAL
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_hierarchy - whether SSP is configured as Master or Slave
|
||||
*/
|
||||
enum ssp_hierarchy {
|
||||
SSP_MASTER,
|
||||
SSP_SLAVE
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_clock_params - clock parameters, to set SSP clock at a
|
||||
* desired freq
|
||||
*/
|
||||
struct ssp_clock_params {
|
||||
u8 cpsdvsr; /* value from 2 to 254 (even only!) */
|
||||
u8 scr; /* value from 0 to 255 */
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_rx_endian - endianess of Rx FIFO Data
|
||||
* this feature is only available in ST versionf of PL022
|
||||
*/
|
||||
enum ssp_rx_endian {
|
||||
SSP_RX_MSB,
|
||||
SSP_RX_LSB
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_tx_endian - endianess of Tx FIFO Data
|
||||
*/
|
||||
enum ssp_tx_endian {
|
||||
SSP_TX_MSB,
|
||||
SSP_TX_LSB
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_data_size - number of bits in one data element
|
||||
*/
|
||||
enum ssp_data_size {
|
||||
SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
|
||||
SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
|
||||
SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
|
||||
SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
|
||||
SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
|
||||
SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
|
||||
SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
|
||||
SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
|
||||
SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
|
||||
SSP_DATA_BITS_31, SSP_DATA_BITS_32
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_mode - SSP mode of operation (Communication modes)
|
||||
*/
|
||||
enum ssp_mode {
|
||||
INTERRUPT_TRANSFER,
|
||||
POLLING_TRANSFER,
|
||||
DMA_TRANSFER
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_rx_level_trig - receive FIFO watermark level which triggers
|
||||
* IT: Interrupt fires when _N_ or more elements in RX FIFO.
|
||||
*/
|
||||
enum ssp_rx_level_trig {
|
||||
SSP_RX_1_OR_MORE_ELEM,
|
||||
SSP_RX_4_OR_MORE_ELEM,
|
||||
SSP_RX_8_OR_MORE_ELEM,
|
||||
SSP_RX_16_OR_MORE_ELEM,
|
||||
SSP_RX_32_OR_MORE_ELEM
|
||||
};
|
||||
|
||||
/**
|
||||
* Transmit FIFO watermark level which triggers (IT Interrupt fires
|
||||
* when _N_ or more empty locations in TX FIFO)
|
||||
*/
|
||||
enum ssp_tx_level_trig {
|
||||
SSP_TX_1_OR_MORE_EMPTY_LOC,
|
||||
SSP_TX_4_OR_MORE_EMPTY_LOC,
|
||||
SSP_TX_8_OR_MORE_EMPTY_LOC,
|
||||
SSP_TX_16_OR_MORE_EMPTY_LOC,
|
||||
SSP_TX_32_OR_MORE_EMPTY_LOC
|
||||
};
|
||||
|
||||
/**
|
||||
* enum SPI Clock Phase - clock phase (Motorola SPI interface only)
|
||||
* @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
|
||||
* @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
|
||||
*/
|
||||
enum ssp_spi_clk_phase {
|
||||
SSP_CLK_FIRST_EDGE,
|
||||
SSP_CLK_SECOND_EDGE
|
||||
};
|
||||
|
||||
/**
|
||||
* enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
|
||||
* @SSP_CLK_POL_IDLE_LOW: Low inactive level
|
||||
* @SSP_CLK_POL_IDLE_HIGH: High inactive level
|
||||
*/
|
||||
enum ssp_spi_clk_pol {
|
||||
SSP_CLK_POL_IDLE_LOW,
|
||||
SSP_CLK_POL_IDLE_HIGH
|
||||
};
|
||||
|
||||
/**
|
||||
* Microwire Conrol Lengths Command size in microwire format
|
||||
*/
|
||||
enum ssp_microwire_ctrl_len {
|
||||
SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
|
||||
SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
|
||||
SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
|
||||
SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
|
||||
SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
|
||||
SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
|
||||
SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
|
||||
SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
|
||||
SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
|
||||
SSP_BITS_31, SSP_BITS_32
|
||||
};
|
||||
|
||||
/**
|
||||
* enum Microwire Wait State
|
||||
* @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
|
||||
* @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
|
||||
*/
|
||||
enum ssp_microwire_wait_state {
|
||||
SSP_MWIRE_WAIT_ZERO,
|
||||
SSP_MWIRE_WAIT_ONE
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_duplex - whether Full/Half Duplex on microwire, only
|
||||
* available in the ST Micro variant.
|
||||
* @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
|
||||
* SSPRXD not used
|
||||
* @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
|
||||
* an input.
|
||||
*/
|
||||
enum ssp_duplex {
|
||||
SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
|
||||
SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ssp_clkdelay - an optional clock delay on the feedback clock
|
||||
* only available in the ST Micro PL023 variant.
|
||||
* @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
|
||||
* slave is sampled directly
|
||||
* @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
|
||||
* a delay of T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
|
||||
* @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
|
||||
*/
|
||||
enum ssp_clkdelay {
|
||||
SSP_FEEDBACK_CLK_DELAY_NONE,
|
||||
SSP_FEEDBACK_CLK_DELAY_1T,
|
||||
SSP_FEEDBACK_CLK_DELAY_2T,
|
||||
SSP_FEEDBACK_CLK_DELAY_3T,
|
||||
SSP_FEEDBACK_CLK_DELAY_4T,
|
||||
SSP_FEEDBACK_CLK_DELAY_5T,
|
||||
SSP_FEEDBACK_CLK_DELAY_6T,
|
||||
SSP_FEEDBACK_CLK_DELAY_7T
|
||||
};
|
||||
|
||||
/**
|
||||
* CHIP select/deselect commands
|
||||
*/
|
||||
enum ssp_chip_select {
|
||||
SSP_CHIP_SELECT,
|
||||
SSP_CHIP_DESELECT
|
||||
};
|
||||
|
||||
|
||||
struct dma_chan;
|
||||
/**
|
||||
* struct pl022_ssp_master - device.platform_data for SPI controller devices.
|
||||
* @bus_id: identifier for this bus
|
||||
* @enable_dma: if true enables DMA driven transfers.
|
||||
* @dma_filter: callback filter for dma_request_channel.
|
||||
* @dma_rx_param: parameter to locate an RX DMA channel.
|
||||
* @dma_tx_param: parameter to locate a TX DMA channel.
|
||||
* @autosuspend_delay: delay in ms following transfer completion before the
|
||||
* runtime power management system suspends the device. A setting of 0
|
||||
* indicates no delay and the device will be suspended immediately.
|
||||
* @rt: indicates the controller should run the message pump with realtime
|
||||
* priority to minimise the transfer latency on the bus.
|
||||
*/
|
||||
struct pl022_ssp_controller {
|
||||
u16 bus_id;
|
||||
u8 enable_dma:1;
|
||||
dma_filter_fn dma_filter;
|
||||
void *dma_rx_param;
|
||||
void *dma_tx_param;
|
||||
int autosuspend_delay;
|
||||
bool rt;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ssp_config_chip - spi_board_info.controller_data for SPI
|
||||
* slave devices, copied to spi_device.controller_data.
|
||||
*
|
||||
* @iface: Interface type(Motorola, TI, Microwire, Universal)
|
||||
* @hierarchy: sets whether interface is master or slave
|
||||
* @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
|
||||
* @clk_freq: Tune freq parameters of SSP(when in master mode)
|
||||
* @com_mode: communication mode: polling, Interrupt or DMA
|
||||
* @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
|
||||
* @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
|
||||
* @ctrl_len: Microwire interface: Control length
|
||||
* @wait_state: Microwire interface: Wait state
|
||||
* @duplex: Microwire interface: Full/Half duplex
|
||||
* @clkdelay: on the PL023 variant, the delay in feeback clock cycles
|
||||
* before sampling the incoming line
|
||||
*/
|
||||
struct pl022_config_chip {
|
||||
enum ssp_interface iface;
|
||||
enum ssp_hierarchy hierarchy;
|
||||
bool slave_tx_disable;
|
||||
struct ssp_clock_params clk_freq;
|
||||
enum ssp_mode com_mode;
|
||||
enum ssp_rx_level_trig rx_lev_trig;
|
||||
enum ssp_tx_level_trig tx_lev_trig;
|
||||
enum ssp_microwire_ctrl_len ctrl_len;
|
||||
enum ssp_microwire_wait_state wait_state;
|
||||
enum ssp_duplex duplex;
|
||||
enum ssp_clkdelay clkdelay;
|
||||
};
|
||||
|
||||
#endif /* _SSP_PL022_H */
|
||||
@@ -0,0 +1,217 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* include/linux/amba/pl080.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* http://armlinux.simtec.co.uk/
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* ARM PrimeCell PL080 DMA controller
|
||||
*/
|
||||
|
||||
/* Note, there are some Samsung updates to this controller block which
|
||||
* make it not entierly compatible with the PL080 specification from
|
||||
* ARM. When in doubt, check the Samsung documentation first.
|
||||
*
|
||||
* The Samsung defines are PL080S, and add an extra control register,
|
||||
* the ability to move more than 2^11 counts of data and some extra
|
||||
* OneNAND features.
|
||||
*/
|
||||
|
||||
#ifndef ASM_PL080_H
|
||||
#define ASM_PL080_H
|
||||
|
||||
#define PL080_INT_STATUS (0x00)
|
||||
#define PL080_TC_STATUS (0x04)
|
||||
#define PL080_TC_CLEAR (0x08)
|
||||
#define PL080_ERR_STATUS (0x0C)
|
||||
#define PL080_ERR_CLEAR (0x10)
|
||||
#define PL080_RAW_TC_STATUS (0x14)
|
||||
#define PL080_RAW_ERR_STATUS (0x18)
|
||||
#define PL080_EN_CHAN (0x1c)
|
||||
#define PL080_SOFT_BREQ (0x20)
|
||||
#define PL080_SOFT_SREQ (0x24)
|
||||
#define PL080_SOFT_LBREQ (0x28)
|
||||
#define PL080_SOFT_LSREQ (0x2C)
|
||||
|
||||
#define PL080_CONFIG (0x30)
|
||||
#define PL080_CONFIG_M2_BE BIT(2)
|
||||
#define PL080_CONFIG_M1_BE BIT(1)
|
||||
#define PL080_CONFIG_ENABLE BIT(0)
|
||||
|
||||
#define PL080_SYNC (0x34)
|
||||
|
||||
/* The Faraday Technology FTDMAC020 variant registers */
|
||||
#define FTDMAC020_CH_BUSY (0x20)
|
||||
/* Identical to PL080_CONFIG */
|
||||
#define FTDMAC020_CSR (0x24)
|
||||
/* Identical to PL080_SYNC */
|
||||
#define FTDMAC020_SYNC (0x2C)
|
||||
#define FTDMAC020_REVISION (0x30)
|
||||
#define FTDMAC020_FEATURE (0x34)
|
||||
|
||||
/* Per channel configuration registers */
|
||||
#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
|
||||
#define PL080_CH_SRC_ADDR (0x00)
|
||||
#define PL080_CH_DST_ADDR (0x04)
|
||||
#define PL080_CH_LLI (0x08)
|
||||
#define PL080_CH_CONTROL (0x0C)
|
||||
#define PL080_CH_CONFIG (0x10)
|
||||
#define PL080S_CH_CONTROL2 (0x10)
|
||||
#define PL080S_CH_CONFIG (0x14)
|
||||
/* The Faraday FTDMAC020 derivative shuffles the registers around */
|
||||
#define FTDMAC020_CH_CSR (0x00)
|
||||
#define FTDMAC020_CH_CFG (0x04)
|
||||
#define FTDMAC020_CH_SRC_ADDR (0x08)
|
||||
#define FTDMAC020_CH_DST_ADDR (0x0C)
|
||||
#define FTDMAC020_CH_LLP (0x10)
|
||||
#define FTDMAC020_CH_SIZE (0x14)
|
||||
|
||||
#define PL080_LLI_ADDR_MASK GENMASK(31, 2)
|
||||
#define PL080_LLI_ADDR_SHIFT (2)
|
||||
#define PL080_LLI_LM_AHB2 BIT(0)
|
||||
|
||||
#define PL080_CONTROL_TC_IRQ_EN BIT(31)
|
||||
#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
|
||||
#define PL080_CONTROL_PROT_SHIFT (28)
|
||||
#define PL080_CONTROL_PROT_CACHE BIT(30)
|
||||
#define PL080_CONTROL_PROT_BUFF BIT(29)
|
||||
#define PL080_CONTROL_PROT_SYS BIT(28)
|
||||
#define PL080_CONTROL_DST_INCR BIT(27)
|
||||
#define PL080_CONTROL_SRC_INCR BIT(26)
|
||||
#define PL080_CONTROL_DST_AHB2 BIT(25)
|
||||
#define PL080_CONTROL_SRC_AHB2 BIT(24)
|
||||
#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
|
||||
#define PL080_CONTROL_DWIDTH_SHIFT (21)
|
||||
#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
|
||||
#define PL080_CONTROL_SWIDTH_SHIFT (18)
|
||||
#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
|
||||
#define PL080_CONTROL_DB_SIZE_SHIFT (15)
|
||||
#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
|
||||
#define PL080_CONTROL_SB_SIZE_SHIFT (12)
|
||||
#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
|
||||
#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
|
||||
#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
|
||||
|
||||
#define PL080_BSIZE_1 (0x0)
|
||||
#define PL080_BSIZE_4 (0x1)
|
||||
#define PL080_BSIZE_8 (0x2)
|
||||
#define PL080_BSIZE_16 (0x3)
|
||||
#define PL080_BSIZE_32 (0x4)
|
||||
#define PL080_BSIZE_64 (0x5)
|
||||
#define PL080_BSIZE_128 (0x6)
|
||||
#define PL080_BSIZE_256 (0x7)
|
||||
|
||||
#define PL080_WIDTH_8BIT (0x0)
|
||||
#define PL080_WIDTH_16BIT (0x1)
|
||||
#define PL080_WIDTH_32BIT (0x2)
|
||||
|
||||
#define PL080N_CONFIG_ITPROT BIT(20)
|
||||
#define PL080N_CONFIG_SECPROT BIT(19)
|
||||
#define PL080_CONFIG_HALT BIT(18)
|
||||
#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
|
||||
#define PL080_CONFIG_LOCK BIT(16)
|
||||
#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
|
||||
#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
|
||||
#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
|
||||
#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
|
||||
#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
|
||||
#define PL080_CONFIG_DST_SEL_SHIFT (6)
|
||||
#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
|
||||
#define PL080_CONFIG_SRC_SEL_SHIFT (1)
|
||||
#define PL080_CONFIG_ENABLE BIT(0)
|
||||
|
||||
#define PL080_FLOW_MEM2MEM (0x0)
|
||||
#define PL080_FLOW_MEM2PER (0x1)
|
||||
#define PL080_FLOW_PER2MEM (0x2)
|
||||
#define PL080_FLOW_SRC2DST (0x3)
|
||||
#define PL080_FLOW_SRC2DST_DST (0x4)
|
||||
#define PL080_FLOW_MEM2PER_PER (0x5)
|
||||
#define PL080_FLOW_PER2MEM_PER (0x6)
|
||||
#define PL080_FLOW_SRC2DST_SRC (0x7)
|
||||
|
||||
#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
|
||||
/* Later versions have a threshold in bits 24..26, */
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
|
||||
#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
|
||||
#define FTDMAC020_CH_CSR_PROT3 BIT(21)
|
||||
#define FTDMAC020_CH_CSR_PROT2 BIT(20)
|
||||
#define FTDMAC020_CH_CSR_PROT1 BIT(19)
|
||||
#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
|
||||
#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
|
||||
#define FTDMAC020_CH_CSR_ABT BIT(15)
|
||||
#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
|
||||
#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
|
||||
#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
|
||||
#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
|
||||
#define FTDMAC020_CH_CSR_MODE BIT(7)
|
||||
/* 00 = increase, 01 = decrease, 10 = fix */
|
||||
#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
|
||||
#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
|
||||
#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
|
||||
#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
|
||||
#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
|
||||
#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
|
||||
#define FTDMAC020_CH_CSR_EN BIT(0)
|
||||
|
||||
/* FIFO threshold setting */
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
|
||||
#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
|
||||
/* The FTDMAC020 supports 64bit wide transfers */
|
||||
#define FTDMAC020_WIDTH_64BIT (0x3)
|
||||
/* Address can be increased, decreased or fixed */
|
||||
#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
|
||||
#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
|
||||
#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
|
||||
|
||||
#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
|
||||
#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
|
||||
#define FTDMAC020_CH_CFG_BUSY BIT(8)
|
||||
#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
|
||||
#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
|
||||
#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
|
||||
|
||||
/* Inside the LLIs, the applicable CSR fields are mapped differently */
|
||||
#define FTDMAC020_LLI_TC_MSK BIT(28)
|
||||
#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
|
||||
#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
|
||||
#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
|
||||
#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
|
||||
#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
|
||||
#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
|
||||
#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
|
||||
#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
|
||||
#define FTDMAC020_LLI_SRC_SEL BIT(17)
|
||||
#define FTDMAC020_LLI_DST_SEL BIT(16)
|
||||
#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
|
||||
#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
|
||||
|
||||
#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
|
||||
#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
|
||||
#define FTDMAC020_CFG_BUSY BIT(8)
|
||||
#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
|
||||
#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
|
||||
#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
|
||||
|
||||
/* DMA linked list chain structure */
|
||||
|
||||
struct pl080_lli {
|
||||
u32 src_addr;
|
||||
u32 dst_addr;
|
||||
u32 next_lli;
|
||||
u32 control0;
|
||||
};
|
||||
|
||||
struct pl080s_lli {
|
||||
u32 src_addr;
|
||||
u32 dst_addr;
|
||||
u32 next_lli;
|
||||
u32 control0;
|
||||
u32 control1;
|
||||
};
|
||||
|
||||
#endif /* ASM_PL080_H */
|
||||
@@ -0,0 +1,130 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
|
||||
*
|
||||
* Copyright (C) 2005 ARM Ltd
|
||||
* Copyright (C) 2010 ST-Ericsson SA
|
||||
*
|
||||
* pl08x information required by platform code
|
||||
*
|
||||
* Please credit ARM.com
|
||||
* Documentation: ARM DDI 0196D
|
||||
*/
|
||||
|
||||
#ifndef AMBA_PL08X_H
|
||||
#define AMBA_PL08X_H
|
||||
|
||||
/* We need sizes of structs from this header */
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
struct pl08x_driver_data;
|
||||
struct pl08x_phy_chan;
|
||||
struct pl08x_txd;
|
||||
|
||||
/* Bitmasks for selecting AHB ports for DMA transfers */
|
||||
enum {
|
||||
PL08X_AHB1 = (1 << 0),
|
||||
PL08X_AHB2 = (1 << 1)
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_channel_data - data structure to pass info between
|
||||
* platform and PL08x driver regarding channel configuration
|
||||
* @bus_id: name of this device channel, not just a device name since
|
||||
* devices may have more than one channel e.g. "foo_tx"
|
||||
* @min_signal: the minimum DMA signal number to be muxed in for this
|
||||
* channel (for platforms supporting muxed signals). If you have
|
||||
* static assignments, make sure this is set to the assigned signal
|
||||
* number, PL08x have 16 possible signals in number 0 thru 15 so
|
||||
* when these are not enough they often get muxed (in hardware)
|
||||
* disabling simultaneous use of the same channel for two devices.
|
||||
* @max_signal: the maximum DMA signal number to be muxed in for
|
||||
* the channel. Set to the same as min_signal for
|
||||
* devices with static assignments
|
||||
* @muxval: a number usually used to poke into some mux regiser to
|
||||
* mux in the signal to this channel
|
||||
* @addr: source/target address in physical memory for this DMA channel,
|
||||
* can be the address of a FIFO register for burst requests for example.
|
||||
* This can be left undefined if the PrimeCell API is used for configuring
|
||||
* this.
|
||||
* @single: the device connected to this channel will request single DMA
|
||||
* transfers, not bursts. (Bursts are default.)
|
||||
* @periph_buses: the device connected to this channel is accessible via
|
||||
* these buses (use PL08X_AHB1 | PL08X_AHB2).
|
||||
*/
|
||||
struct pl08x_channel_data {
|
||||
const char *bus_id;
|
||||
int min_signal;
|
||||
int max_signal;
|
||||
u32 muxval;
|
||||
dma_addr_t addr;
|
||||
bool single;
|
||||
u8 periph_buses;
|
||||
};
|
||||
|
||||
enum pl08x_burst_size {
|
||||
PL08X_BURST_SZ_1,
|
||||
PL08X_BURST_SZ_4,
|
||||
PL08X_BURST_SZ_8,
|
||||
PL08X_BURST_SZ_16,
|
||||
PL08X_BURST_SZ_32,
|
||||
PL08X_BURST_SZ_64,
|
||||
PL08X_BURST_SZ_128,
|
||||
PL08X_BURST_SZ_256,
|
||||
};
|
||||
|
||||
enum pl08x_bus_width {
|
||||
PL08X_BUS_WIDTH_8_BITS,
|
||||
PL08X_BUS_WIDTH_16_BITS,
|
||||
PL08X_BUS_WIDTH_32_BITS,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pl08x_platform_data - the platform configuration for the PL08x
|
||||
* PrimeCells.
|
||||
* @slave_channels: the channels defined for the different devices on the
|
||||
* platform, all inclusive, including multiplexed channels. The available
|
||||
* physical channels will be multiplexed around these signals as they are
|
||||
* requested, just enumerate all possible channels.
|
||||
* @num_slave_channels: number of elements in the slave channel array
|
||||
* @memcpy_burst_size: the appropriate burst size for memcpy operations
|
||||
* @memcpy_bus_width: memory bus width
|
||||
* @memcpy_prot_buff: whether memcpy DMA is bufferable
|
||||
* @memcpy_prot_cache: whether memcpy DMA is cacheable
|
||||
* @get_xfer_signal: request a physical signal to be used for a DMA transfer
|
||||
* immediately: if there is some multiplexing or similar blocking the use
|
||||
* of the channel the transfer can be denied by returning less than zero,
|
||||
* else it returns the allocated signal number
|
||||
* @put_xfer_signal: indicate to the platform that this physical signal is not
|
||||
* running any DMA transfer and multiplexing can be recycled
|
||||
* @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
|
||||
* @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
|
||||
* @slave_map: DMA slave matching table
|
||||
* @slave_map_len: number of elements in @slave_map
|
||||
*/
|
||||
struct pl08x_platform_data {
|
||||
struct pl08x_channel_data *slave_channels;
|
||||
unsigned int num_slave_channels;
|
||||
enum pl08x_burst_size memcpy_burst_size;
|
||||
enum pl08x_bus_width memcpy_bus_width;
|
||||
bool memcpy_prot_buff;
|
||||
bool memcpy_prot_cache;
|
||||
int (*get_xfer_signal)(const struct pl08x_channel_data *);
|
||||
void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
|
||||
u8 lli_buses;
|
||||
u8 mem_buses;
|
||||
const struct dma_slave_map *slave_map;
|
||||
int slave_map_len;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_AMBA_PL08X
|
||||
bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* AMBA_PL08X_H */
|
||||
@@ -0,0 +1,237 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* linux/include/asm-arm/hardware/serial_amba.h
|
||||
*
|
||||
* Internal header file for AMBA serial ports
|
||||
*
|
||||
* Copyright (C) ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
*/
|
||||
#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
|
||||
#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bits.h>
|
||||
#endif
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* -------------------------------------------------------------------------------
|
||||
* From AMBA UART (PL010) Block Specification
|
||||
* -------------------------------------------------------------------------------
|
||||
* UART Register Offsets.
|
||||
*/
|
||||
#define UART01x_DR 0x00 /* Data read or written from the interface. */
|
||||
#define UART01x_RSR 0x04 /* Receive status register (Read). */
|
||||
#define UART01x_ECR 0x04 /* Error clear register (Write). */
|
||||
#define UART010_LCRH 0x08 /* Line control register, high byte. */
|
||||
#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
|
||||
#define UART010_LCRM 0x0C /* Line control register, middle byte. */
|
||||
#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
|
||||
#define UART010_LCRL 0x10 /* Line control register, low byte. */
|
||||
#define UART010_CR 0x14 /* Control register. */
|
||||
#define UART01x_FR 0x18 /* Flag register (Read only). */
|
||||
#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
|
||||
#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
|
||||
#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
|
||||
#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
|
||||
#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
|
||||
#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
|
||||
#define UART011_LCRH 0x2c /* Line control register. */
|
||||
#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
|
||||
#define UART011_CR 0x30 /* Control register. */
|
||||
#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
|
||||
#define UART011_IMSC 0x38 /* Interrupt mask. */
|
||||
#define UART011_RIS 0x3c /* Raw interrupt status. */
|
||||
#define UART011_MIS 0x40 /* Masked interrupt status. */
|
||||
#define UART011_ICR 0x44 /* Interrupt clear register. */
|
||||
#define UART011_DMACR 0x48 /* DMA control register. */
|
||||
#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
|
||||
#define ST_UART011_XON1 0x54 /* XON1 register. */
|
||||
#define ST_UART011_XON2 0x58 /* XON2 register. */
|
||||
#define ST_UART011_XOFF1 0x5C /* XON1 register. */
|
||||
#define ST_UART011_XOFF2 0x60 /* XON2 register. */
|
||||
#define ST_UART011_ITCR 0x80 /* Integration test control register. */
|
||||
#define ST_UART011_ITIP 0x84 /* Integration test input register. */
|
||||
#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
|
||||
#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
|
||||
|
||||
/*
|
||||
* ZTE UART register offsets. This UART has a radically different address
|
||||
* allocation from the ARM and ST variants, so we list all registers here.
|
||||
* We assume unlisted registers do not exist.
|
||||
*/
|
||||
#define ZX_UART011_DR 0x04
|
||||
#define ZX_UART011_FR 0x14
|
||||
#define ZX_UART011_IBRD 0x24
|
||||
#define ZX_UART011_FBRD 0x28
|
||||
#define ZX_UART011_LCRH 0x30
|
||||
#define ZX_UART011_CR 0x34
|
||||
#define ZX_UART011_IFLS 0x38
|
||||
#define ZX_UART011_IMSC 0x40
|
||||
#define ZX_UART011_RIS 0x44
|
||||
#define ZX_UART011_MIS 0x48
|
||||
#define ZX_UART011_ICR 0x4c
|
||||
#define ZX_UART011_DMACR 0x50
|
||||
|
||||
#define UART011_DR_OE BIT(11)
|
||||
#define UART011_DR_BE BIT(10)
|
||||
#define UART011_DR_PE BIT(9)
|
||||
#define UART011_DR_FE BIT(8)
|
||||
|
||||
#define UART01x_RSR_OE BIT(3)
|
||||
#define UART01x_RSR_BE BIT(2)
|
||||
#define UART01x_RSR_PE BIT(1)
|
||||
#define UART01x_RSR_FE BIT(0)
|
||||
|
||||
#define UART011_FR_RI BIT(8)
|
||||
#define UART011_FR_TXFE BIT(7)
|
||||
#define UART011_FR_RXFF BIT(6)
|
||||
#define UART01x_FR_TXFF (1 << 5) /* used in ASM */
|
||||
#define UART01x_FR_RXFE BIT(4)
|
||||
#define UART01x_FR_BUSY (1 << 3) /* used in ASM */
|
||||
#define UART01x_FR_DCD BIT(2)
|
||||
#define UART01x_FR_DSR BIT(1)
|
||||
#define UART01x_FR_CTS BIT(0)
|
||||
#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
|
||||
|
||||
/*
|
||||
* Some bits of Flag Register on ZTE device have different position from
|
||||
* standard ones.
|
||||
*/
|
||||
#define ZX_UART01x_FR_BUSY BIT(8)
|
||||
#define ZX_UART01x_FR_DSR BIT(3)
|
||||
#define ZX_UART01x_FR_CTS BIT(1)
|
||||
#define ZX_UART011_FR_RI BIT(0)
|
||||
|
||||
#define UART011_CR_CTSEN BIT(15) /* CTS hardware flow control */
|
||||
#define UART011_CR_RTSEN BIT(14) /* RTS hardware flow control */
|
||||
#define UART011_CR_OUT2 BIT(13) /* OUT2 */
|
||||
#define UART011_CR_OUT1 BIT(12) /* OUT1 */
|
||||
#define UART011_CR_RTS BIT(11) /* RTS */
|
||||
#define UART011_CR_DTR BIT(10) /* DTR */
|
||||
#define UART011_CR_RXE BIT(9) /* receive enable */
|
||||
#define UART011_CR_TXE BIT(8) /* transmit enable */
|
||||
#define UART011_CR_LBE BIT(7) /* loopback enable */
|
||||
#define UART010_CR_RTIE BIT(6)
|
||||
#define UART010_CR_TIE BIT(5)
|
||||
#define UART010_CR_RIE BIT(4)
|
||||
#define UART010_CR_MSIE BIT(3)
|
||||
#define ST_UART011_CR_OVSFACT BIT(3) /* Oversampling factor */
|
||||
#define UART01x_CR_IIRLP BIT(2) /* SIR low power mode */
|
||||
#define UART01x_CR_SIREN BIT(1) /* SIR enable */
|
||||
#define UART01x_CR_UARTEN BIT(0) /* UART enable */
|
||||
|
||||
#define UART011_LCRH_SPS BIT(7)
|
||||
#define UART01x_LCRH_WLEN_8 0x60
|
||||
#define UART01x_LCRH_WLEN_7 0x40
|
||||
#define UART01x_LCRH_WLEN_6 0x20
|
||||
#define UART01x_LCRH_WLEN_5 0x00
|
||||
#define UART01x_LCRH_FEN BIT(4)
|
||||
#define UART01x_LCRH_STP2 BIT(3)
|
||||
#define UART01x_LCRH_EPS BIT(2)
|
||||
#define UART01x_LCRH_PEN BIT(1)
|
||||
#define UART01x_LCRH_BRK BIT(0)
|
||||
|
||||
#define ST_UART011_DMAWM_RX GENMASK(5, 3)
|
||||
#define ST_UART011_DMAWM_RX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 0)
|
||||
#define ST_UART011_DMAWM_RX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 1)
|
||||
#define ST_UART011_DMAWM_RX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 2)
|
||||
#define ST_UART011_DMAWM_RX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 3)
|
||||
#define ST_UART011_DMAWM_RX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 4)
|
||||
#define ST_UART011_DMAWM_RX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 5)
|
||||
#define ST_UART011_DMAWM_RX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 6)
|
||||
#define ST_UART011_DMAWM_TX GENMASK(2, 0)
|
||||
#define ST_UART011_DMAWM_TX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 0)
|
||||
#define ST_UART011_DMAWM_TX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 1)
|
||||
#define ST_UART011_DMAWM_TX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 2)
|
||||
#define ST_UART011_DMAWM_TX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 3)
|
||||
#define ST_UART011_DMAWM_TX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 4)
|
||||
#define ST_UART011_DMAWM_TX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 5)
|
||||
#define ST_UART011_DMAWM_TX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 6)
|
||||
|
||||
#define UART010_IIR_RTIS BIT(3)
|
||||
#define UART010_IIR_TIS BIT(2)
|
||||
#define UART010_IIR_RIS BIT(1)
|
||||
#define UART010_IIR_MIS BIT(0)
|
||||
|
||||
#define UART011_IFLS_RXIFLSEL GENMASK(5, 3)
|
||||
#define UART011_IFLS_RX1_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 0)
|
||||
#define UART011_IFLS_RX2_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 1)
|
||||
#define UART011_IFLS_RX4_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 2)
|
||||
#define UART011_IFLS_RX6_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 3)
|
||||
#define UART011_IFLS_RX7_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 4)
|
||||
#define UART011_IFLS_TXIFLSEL GENMASK(2, 0)
|
||||
#define UART011_IFLS_TX1_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 0)
|
||||
#define UART011_IFLS_TX2_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 1)
|
||||
#define UART011_IFLS_TX4_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 2)
|
||||
#define UART011_IFLS_TX6_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 3)
|
||||
#define UART011_IFLS_TX7_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 4)
|
||||
/* special values for ST vendor with deeper fifo */
|
||||
#define UART011_IFLS_RX_HALF FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 5)
|
||||
#define UART011_IFLS_TX_HALF FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 5)
|
||||
|
||||
#define UART011_OEIM BIT(10) /* overrun error interrupt mask */
|
||||
#define UART011_BEIM BIT(9) /* break error interrupt mask */
|
||||
#define UART011_PEIM BIT(8) /* parity error interrupt mask */
|
||||
#define UART011_FEIM BIT(7) /* framing error interrupt mask */
|
||||
#define UART011_RTIM BIT(6) /* receive timeout interrupt mask */
|
||||
#define UART011_TXIM BIT(5) /* transmit interrupt mask */
|
||||
#define UART011_RXIM BIT(4) /* receive interrupt mask */
|
||||
#define UART011_DSRMIM BIT(3) /* DSR interrupt mask */
|
||||
#define UART011_DCDMIM BIT(2) /* DCD interrupt mask */
|
||||
#define UART011_CTSMIM BIT(1) /* CTS interrupt mask */
|
||||
#define UART011_RIMIM BIT(0) /* RI interrupt mask */
|
||||
|
||||
#define UART011_OEIS BIT(10) /* overrun error interrupt status */
|
||||
#define UART011_BEIS BIT(9) /* break error interrupt status */
|
||||
#define UART011_PEIS BIT(8) /* parity error interrupt status */
|
||||
#define UART011_FEIS BIT(7) /* framing error interrupt status */
|
||||
#define UART011_RTIS BIT(6) /* receive timeout interrupt status */
|
||||
#define UART011_TXIS BIT(5) /* transmit interrupt status */
|
||||
#define UART011_RXIS BIT(4) /* receive interrupt status */
|
||||
#define UART011_DSRMIS BIT(3) /* DSR interrupt status */
|
||||
#define UART011_DCDMIS BIT(2) /* DCD interrupt status */
|
||||
#define UART011_CTSMIS BIT(1) /* CTS interrupt status */
|
||||
#define UART011_RIMIS BIT(0) /* RI interrupt status */
|
||||
|
||||
#define UART011_OEIC BIT(10) /* overrun error interrupt clear */
|
||||
#define UART011_BEIC BIT(9) /* break error interrupt clear */
|
||||
#define UART011_PEIC BIT(8) /* parity error interrupt clear */
|
||||
#define UART011_FEIC BIT(7) /* framing error interrupt clear */
|
||||
#define UART011_RTIC BIT(6) /* receive timeout interrupt clear */
|
||||
#define UART011_TXIC BIT(5) /* transmit interrupt clear */
|
||||
#define UART011_RXIC BIT(4) /* receive interrupt clear */
|
||||
#define UART011_DSRMIC BIT(3) /* DSR interrupt clear */
|
||||
#define UART011_DCDMIC BIT(2) /* DCD interrupt clear */
|
||||
#define UART011_CTSMIC BIT(1) /* CTS interrupt clear */
|
||||
#define UART011_RIMIC BIT(0) /* RI interrupt clear */
|
||||
|
||||
#define UART011_DMAONERR BIT(2) /* disable dma on error */
|
||||
#define UART011_TXDMAE BIT(1) /* enable transmit dma */
|
||||
#define UART011_RXDMAE BIT(0) /* enable receive dma */
|
||||
|
||||
#define UART01x_RSR_ANY (UART01x_RSR_OE | UART01x_RSR_BE | UART01x_RSR_PE | UART01x_RSR_FE)
|
||||
#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD | UART01x_FR_DSR | UART01x_FR_CTS)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct amba_device; /* in uncompress this is included but amba/bus.h is not */
|
||||
struct amba_pl010_data {
|
||||
void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
|
||||
};
|
||||
|
||||
struct dma_chan;
|
||||
struct amba_pl011_data {
|
||||
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
|
||||
void *dma_rx_param;
|
||||
void *dma_tx_param;
|
||||
bool dma_rx_poll_enable;
|
||||
unsigned int dma_rx_poll_rate;
|
||||
unsigned int dma_rx_poll_timeout;
|
||||
void (*init)(void);
|
||||
void (*exit)(void);
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
* ARM PrimeXsys System Controller SP810 header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar <vireshk@kernel.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __AMBA_SP810_H
|
||||
#define __AMBA_SP810_H
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
/* sysctl registers offset */
|
||||
#define SCCTRL 0x000
|
||||
#define SCSYSSTAT 0x004
|
||||
#define SCIMCTRL 0x008
|
||||
#define SCIMSTAT 0x00C
|
||||
#define SCXTALCTRL 0x010
|
||||
#define SCPLLCTRL 0x014
|
||||
#define SCPLLFCTRL 0x018
|
||||
#define SCPERCTRL0 0x01C
|
||||
#define SCPERCTRL1 0x020
|
||||
#define SCPEREN 0x024
|
||||
#define SCPERDIS 0x028
|
||||
#define SCPERCLKEN 0x02C
|
||||
#define SCPERSTAT 0x030
|
||||
#define SCSYSID0 0xEE0
|
||||
#define SCSYSID1 0xEE4
|
||||
#define SCSYSID2 0xEE8
|
||||
#define SCSYSID3 0xEEC
|
||||
#define SCITCR 0xF00
|
||||
#define SCITIR0 0xF04
|
||||
#define SCITIR1 0xF08
|
||||
#define SCITOR 0xF0C
|
||||
#define SCCNTCTRL 0xF10
|
||||
#define SCCNTDATA 0xF14
|
||||
#define SCCNTSTEP 0xF18
|
||||
#define SCPERIPHID0 0xFE0
|
||||
#define SCPERIPHID1 0xFE4
|
||||
#define SCPERIPHID2 0xFE8
|
||||
#define SCPERIPHID3 0xFEC
|
||||
#define SCPCELLID0 0xFF0
|
||||
#define SCPCELLID1 0xFF4
|
||||
#define SCPCELLID2 0xFF8
|
||||
#define SCPCELLID3 0xFFC
|
||||
|
||||
#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
|
||||
|
||||
static inline void sysctl_soft_reset(void __iomem *base)
|
||||
{
|
||||
/* switch to slow mode */
|
||||
writel(0x2, base + SCCTRL);
|
||||
|
||||
/* writing any value to SCSYSSTAT reg will reset system */
|
||||
writel(0, base + SCSYSSTAT);
|
||||
}
|
||||
|
||||
#endif /* __AMBA_SP810_H */
|
||||
Reference in New Issue
Block a user