diff --git a/src/arch/emulate.rs b/src/arch/emulate.rs
index 38b51c1e65..65db01049d 100644
--- a/src/arch/emulate.rs
+++ b/src/arch/emulate.rs
@@ -24,11 +24,11 @@ impl Arch for EmulateArch {
     const PAGE_LEVELS: usize = X8664Arch::PAGE_LEVELS;
 
     const ENTRY_ADDRESS_SHIFT: usize = X8664Arch::ENTRY_ADDRESS_SHIFT;
+    const ENTRY_FLAG_DEFAULT_PAGE: usize = X8664Arch::ENTRY_FLAG_DEFAULT_PAGE;
+    const ENTRY_FLAG_DEFAULT_TABLE: usize = X8664Arch::ENTRY_FLAG_DEFAULT_TABLE;
     const ENTRY_FLAG_PRESENT: usize = X8664Arch::ENTRY_FLAG_PRESENT;
     const ENTRY_FLAG_WRITABLE: usize = X8664Arch::ENTRY_FLAG_WRITABLE;
     const ENTRY_FLAG_USER: usize = X8664Arch::ENTRY_FLAG_USER;
-    const ENTRY_FLAG_HUGE: usize = X8664Arch::ENTRY_FLAG_HUGE;
-    const ENTRY_FLAG_GLOBAL: usize = X8664Arch::ENTRY_FLAG_GLOBAL;
     const ENTRY_FLAG_NO_EXEC: usize = X8664Arch::ENTRY_FLAG_NO_EXEC;
 
     const PHYS_OFFSET: usize = X8664Arch::PHYS_OFFSET;
diff --git a/src/arch/mod.rs b/src/arch/mod.rs
index 5825bdc987..72b8eef1c5 100644
--- a/src/arch/mod.rs
+++ b/src/arch/mod.rs
@@ -22,11 +22,11 @@ pub trait Arch: Clone + Copy {
     const PAGE_LEVELS: usize;
 
     const ENTRY_ADDRESS_SHIFT: usize;
+    const ENTRY_FLAG_DEFAULT_PAGE: usize;
+    const ENTRY_FLAG_DEFAULT_TABLE: usize;
     const ENTRY_FLAG_PRESENT: usize;
     const ENTRY_FLAG_WRITABLE: usize;
     const ENTRY_FLAG_USER: usize;
-    const ENTRY_FLAG_HUGE: usize;
-    const ENTRY_FLAG_GLOBAL: usize;
     const ENTRY_FLAG_NO_EXEC: usize;
 
     const PHYS_OFFSET: usize;
diff --git a/src/arch/x86_64.rs b/src/arch/x86_64.rs
index 9225ee8d0a..4768a2b9bd 100644
--- a/src/arch/x86_64.rs
+++ b/src/arch/x86_64.rs
@@ -14,11 +14,13 @@ impl Arch for X8664Arch {
     const PAGE_LEVELS: usize = 4; // PML4, PDP, PD, PT
 
     const ENTRY_ADDRESS_SHIFT: usize = 52;
+    const ENTRY_FLAG_DEFAULT_PAGE: usize = ENTRY_FLAG_PRESENT;
+    const ENTRY_FLAG_DEFAULT_TABLE: usize = ENTRY_FLAG_PRESENT;
     const ENTRY_FLAG_PRESENT: usize = 1 << 0;
     const ENTRY_FLAG_WRITABLE: usize = 1 << 1;
     const ENTRY_FLAG_USER: usize = 1 << 2;
-    const ENTRY_FLAG_HUGE: usize = 1 << 7;
-    const ENTRY_FLAG_GLOBAL: usize = 1 << 8;
+    // Not used: const ENTRY_FLAG_HUGE: usize = 1 << 7;
+    // Not used: const ENTRY_FLAG_GLOBAL: usize = 1 << 8;
     const ENTRY_FLAG_NO_EXEC: usize = 1 << 63;
 
     const PHYS_OFFSET: usize = Self::PAGE_NEGATIVE_MASK + (Self::PAGE_ADDRESS_SIZE >> 1); // PML4 slot 256 and onwards
diff --git a/src/page/mapper.rs b/src/page/mapper.rs
index 524e170719..ee9f7b9277 100644
--- a/src/page/mapper.rs
+++ b/src/page/mapper.rs
@@ -55,7 +55,7 @@ impl<'f, A: Arch, F: FrameAllocator> PageMapper<'f, A, F> {
     pub unsafe fn map_phys(&mut self, virt: VirtualAddress, phys: PhysicalAddress, flags: usize) -> Option<PageFlush<A>> {
         //TODO: verify virt and phys are aligned
         //TODO: verify flags have correct bits
-        let entry = PageEntry::new(phys.data() | flags | A::ENTRY_FLAG_PRESENT);
+        let entry = PageEntry::new(phys.data() | flags | A::ENTRY_FLAG_DEFAULT_PAGE);
         let mut table = self.table();
         loop {
             let i = table.index_of(virt)?;
@@ -70,7 +70,7 @@ impl<'f, A: Arch, F: FrameAllocator> PageMapper<'f, A, F> {
                     None => {
                         let next_phys = self.allocator.allocate_one()?;
                         //TODO: correct flags?
-                        table.set_entry(i, PageEntry::new(next_phys.data() | A::ENTRY_FLAG_WRITABLE | A::ENTRY_FLAG_PRESENT));
+                        table.set_entry(i, PageEntry::new(next_phys.data() | A::ENTRY_FLAG_WRITABLE | A::ENTRY_FLAG_DEFAULT_TABLE));
                         table.next(i)?
                     }
                 };