diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
index aaf5b11e5c..2634fec1b5 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
@@ -270,6 +270,10 @@ pub const VDBOX_CGCTL3F10: usize = 0xB0FC;
 pub const VDBOX_CGCTL3F1C: usize = 0xB100;
 pub const GEN12_FF_MODE2: usize = 0x6604;
 pub const XEHP_L3SQCREG5: usize = 0xB104;
+pub const XEHP_L3SCQREG7: usize = 0xB188;
+pub const BLEND_FILL_CACHING_OPT_DIS: u32 = 1 << 3;
+pub const XEHP_SQCM: usize = 0x8724;
+pub const EN_32B_ACCESS: u32 = 1 << 30;
 pub const XEHP_FF_MODE2: usize = 0xB108;
 pub const CHICKEN_RASTER_2: usize = 0xB10C;
 pub const XEHP_SLICE_COMMON_ECO_CHICKEN1: usize = 0x731C;
diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
index 5d7676539b..ef22f26f05 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
@@ -341,6 +341,8 @@ fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
     wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_vebx");
     wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE, "Wa_1509235366");
     wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE, "Wa_14010648519");
+    wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS, "GT_TUNING_BLEND_FILL_CACHING");
+    wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS, "GT_TUNING_EN_32B_ACCESS");
 
     if stepping == 0 {
         wa_write_or(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 1 << 8, "Wa_16012650089");
@@ -353,6 +355,8 @@ fn xelpg_gt_workarounds_init(wal: &mut WorkaroundList, _stepping: u8) {
     wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082");
     wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN, "Wa_14014830051");
     wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, "Wa_14015795083");
+    wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS, "GT_TUNING_BLEND_FILL_CACHING");
+    wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS, "GT_TUNING_EN_32B_ACCESS");
 }
 
 fn xelpmp_gt_workarounds_init(wal: &mut WorkaroundList) {