From cf38cff205da0dc7ef0d12606aaa6d49308098c3 Mon Sep 17 00:00:00 2001
From: Admin Pupkin <adminpupkin@gmail.com>
Date: Tue, 2 Jun 2026 05:46:53 +0300
Subject: [PATCH] =?UTF-8?q?intel:=20PCH=20detection=20module=20=E2=80=94?=
 =?UTF-8?q?=20platform=20configuration=20hub=20enumeration?=
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pch.rs: PchType enum spanning 12 PCH generations
  from_generation(): maps IntelGeneration to PchType automatically
  display_well_base(): per-PCH power well register base
  has_separate_ddi_wells(): Gen9+ PCH feature flag
  gmbus_base(): 0x5100 (pre-PCH) vs 0xC5100 (PCH-based)
  ddi_port_count(): 2-6 ports per PCH generation

This gates correct DDI buffer, power well, and GMBUS configuration
per platform. Previously all platforms used Gen9 hardcoded defaults.
---
 .../redox-drm/source/src/drivers/intel/mod.rs |  1 +
 .../redox-drm/source/src/drivers/intel/pch.rs | 74 +++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 local/recipes/gpu/redox-drm/source/src/drivers/intel/pch.rs

diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs
index d076fcc501..45ba4a89f4 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs
@@ -32,6 +32,7 @@ pub mod info;
 pub mod lmem;
 pub mod mocs;
 pub mod panel_pps;
+pub mod pch;
 pub mod psr2;
 pub mod regs;
 pub mod regs_gen4_7;
diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/pch.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/pch.rs
new file mode 100644
index 0000000000..9606a4b99b
--- /dev/null
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/pch.rs
@@ -0,0 +1,74 @@
+use super::info::IntelDeviceInfo;
+use super::info::IntelGeneration;
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum PchType {
+    None,
+    Ibx,
+    Cpt,
+    Lpt,
+    Spt,
+    Kbp,
+    Cnp,
+    Icp,
+    Tgp,
+    Adp,
+    Mtp,
+    Lnl,
+}
+
+impl PchType {
+    pub fn from_generation(gen: IntelGeneration) -> Self {
+        match gen {
+            IntelGeneration::Gen4 | IntelGeneration::Gen5 => PchType::None,
+            IntelGeneration::Gen6 => PchType::Ibx,
+            IntelGeneration::Gen7 => PchType::Cpt,
+            IntelGeneration::Gen8 => PchType::Lpt,
+            IntelGeneration::Gen9 => PchType::Spt,
+            IntelGeneration::Gen9_5 => PchType::Cnp,
+            IntelGeneration::Gen12 => PchType::Tgp,
+            IntelGeneration::Gen12_7 => PchType::Mtp,
+            IntelGeneration::GenXe2 => PchType::Lnl,
+            IntelGeneration::Unknown => PchType::None,
+        }
+    }
+
+    pub fn is_pch_present(&self) -> bool {
+        !matches!(self, PchType::None)
+    }
+
+    pub fn display_well_base(&self) -> usize {
+        match self {
+            PchType::None | PchType::Ibx | PchType::Cpt => 0,
+            PchType::Lpt => 0x45400,
+            PchType::Spt | PchType::Kbp | PchType::Cnp | PchType::Icp => 0x45400,
+            PchType::Tgp | PchType::Adp | PchType::Mtp => 0x45400,
+            PchType::Lnl => 0x45400,
+        }
+    }
+
+    pub fn has_separate_ddi_wells(&self) -> bool {
+        matches!(self,
+            PchType::Spt | PchType::Kbp | PchType::Cnp | PchType::Icp |
+            PchType::Tgp | PchType::Adp | PchType::Mtp
+        )
+    }
+
+    pub fn gmbus_base(&self) -> usize {
+        match self {
+            PchType::None | PchType::Ibx | PchType::Cpt => 0x5100,
+            _ => 0xC5100,
+        }
+    }
+
+    pub fn ddi_port_count(&self) -> u8 {
+        match self {
+            PchType::None => 2,
+            PchType::Ibx | PchType::Cpt => 3,
+            PchType::Lpt | PchType::Spt | PchType::Kbp => 4,
+            PchType::Cnp | PchType::Icp => 5,
+            PchType::Tgp | PchType::Adp | PchType::Mtp => 6,
+            PchType::Lnl => 6,
+        }
+    }
+}