From cea6ce7d7a07364b14ef34108e81c03609130e33 Mon Sep 17 00:00:00 2001
From: 4lDO2 <4lDO2@protonmail.com>
Date: Sat, 2 May 2020 00:05:04 +0200
Subject: [PATCH] Move the setrens to a later position, in nvmed.

---
 nvmed/src/main.rs                        | 4 ++--
 pcid/src/driver_interface/irq_helpers.rs | 3 +--
 pcid/src/pci/cap.rs                      | 2 +-
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/nvmed/src/main.rs b/nvmed/src/main.rs
index 1baf366ad6..3691cc9a2d 100644
--- a/nvmed/src/main.rs
+++ b/nvmed/src/main.rs
@@ -319,8 +319,6 @@ fn main() {
 
         let mut socket_file = unsafe { File::from_raw_fd(socket_fd as RawFd) };
 
-        syscall::setrens(0, 0).expect("nvmed: failed to enter null namespace");
-
         let (reactor_sender, reactor_receiver) = crossbeam_channel::unbounded();
         let (interrupt_method, interrupt_sources) =
             get_int_method(&mut pcid_handle, &pci_config.func, &allocated_bars)
@@ -332,6 +330,8 @@ fn main() {
         nvme::cq_reactor::start_cq_reactor_thread(Arc::clone(&nvme), interrupt_sources, reactor_receiver);
         let namespaces = futures::executor::block_on(nvme.init_with_queues());
 
+        syscall::setrens(0, 0).expect("nvmed: failed to enter null namespace");
+
         let mut scheme = DiskScheme::new(scheme_name, nvme, namespaces);
         let mut todo = Vec::new();
         'events: loop {
diff --git a/pcid/src/driver_interface/irq_helpers.rs b/pcid/src/driver_interface/irq_helpers.rs
index da928bf8d2..e0d63164e5 100644
--- a/pcid/src/driver_interface/irq_helpers.rs
+++ b/pcid/src/driver_interface/irq_helpers.rs
@@ -7,7 +7,6 @@ use std::convert::TryFrom;
 use std::fs::{self, File};
 use std::io::{self, prelude::*};
 use std::num::NonZeroU8;
-use std::ops;
 
 /// Read the local APIC ID of the bootstrap processor.
 pub fn read_bsp_apic_id() -> io::Result<usize> {
@@ -60,7 +59,7 @@ pub fn cpu_ids() -> io::Result<impl Iterator<Item = io::Result<usize>> + 'static
 /// Note that this count/alignment restriction is only mandatory for MSI; MSI-X allows for
 /// individually allocated vectors that might be spread out, even on multiple CPUs. Thus, multiple
 /// invocations with alignment 1 and count 1 are totally acceptable, although allocating in bulk
-/// minimizes the initialization overhead, even though it's negligible.
+/// minimizes the initialization overhead.
 pub fn allocate_aligned_interrupt_vectors(cpu_id: usize, alignment: NonZeroU8, count: u8) -> io::Result<Option<(u8, Vec<File>)>> {
     let cpu_id = u8::try_from(cpu_id).expect("usize cpu ids not implemented yet");
     if count == 0 { return Ok(None) }
diff --git a/pcid/src/pci/cap.rs b/pcid/src/pci/cap.rs
index dfbb6a1feb..15e2077305 100644
--- a/pcid/src/pci/cap.rs
+++ b/pcid/src/pci/cap.rs
@@ -25,7 +25,7 @@ where
 
             if self.offset == 0 { return None };
 
-            let first_dword = dbg!(self.reader.read_u32(dbg!(u16::from(self.offset))));
+            let first_dword = self.reader.read_u32(u16::from(self.offset));
             let next = ((first_dword >> 8) & 0xFF) as u8;
 
             let offset = self.offset;