Rework irqchip to support risc-v irqs, and add risc-v irq chips handling

src/context/arch/riscv64.rs

@@ -8,18 +8,14 @@ use crate::{
     percpu::PercpuBlock,
     syscall::FloatRegisters,
 };
-use alloc::sync::Arc;
 use core::{mem::offset_of, sync::atomic::AtomicBool};
 use rmm::{Arch, TableKind, VirtualAddress};
 use spin::Once;
-use spinning_top::RwSpinlock;
 use syscall::{error::*, EnvRegisters};
 
 pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
 
 pub const KFX_ALIGN: usize = 16;
-pub const KSTACK_SIZE: usize = 65536;
-pub const KSTACK_ALIGN: usize = 16;
 
 #[derive(Clone, Debug, Default)]
 pub struct Context {