From ca3b4d2b94c12d6d37a5cca8575dc8b2f81b92a4 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Tue, 4 May 2021 08:09:28 -0600
Subject: [PATCH] Add riscv64 syscall implementation and register stubs

---
 src/arch/riscv64.rs | 93 +++++++++++++++++++++++++++++++++++++++++++++
 src/lib.rs          |  4 ++
 2 files changed, 97 insertions(+)
 create mode 100644 src/arch/riscv64.rs

diff --git a/src/arch/riscv64.rs b/src/arch/riscv64.rs
new file mode 100644
index 0000000000..2a90260da4
--- /dev/null
+++ b/src/arch/riscv64.rs
@@ -0,0 +1,93 @@
+use core::{mem, slice};
+use core::ops::{Deref, DerefMut};
+
+use super::error::{Error, Result};
+
+macro_rules! syscall {
+    ($($name:ident($a:ident, $($b:ident, $($c:ident, $($d:ident, $($e:ident, $($f:ident, )?)?)?)?)?);)+) => {
+        $(
+            pub unsafe fn $name($a: usize, $($b: usize, $($c: usize, $($d: usize, $($e: usize, $($f: usize)?)?)?)?)?) -> Result<usize> {
+                let ret: usize;
+
+                asm!(
+                    "ecall",
+                    in("a7") $a,
+                    $(
+                        in("a0") $b,
+                        $(
+                            in("a1") $c,
+                            $(
+                                in("a2") $d,
+                                $(
+                                    in("a3") $e,
+                                    $(
+                                        in("a4") $f,
+                                    )?
+                                )?
+                            )?
+                        )?
+                    )?
+                    lateout("a0") ret,
+                    options(nostack),
+                );
+
+                Error::demux(ret)
+            }
+        )+
+    };
+}
+
+syscall! {
+    syscall0(a,);
+    syscall1(a, b,);
+    syscall2(a, b, c,);
+    syscall3(a, b, c, d,);
+    syscall4(a, b, c, d, e,);
+    syscall5(a, b, c, d, e, f,);
+}
+
+#[derive(Copy, Clone, Debug, Default)]
+#[repr(C)]
+pub struct IntRegisters {
+    //TODO
+}
+
+impl Deref for IntRegisters {
+    type Target = [u8];
+    fn deref(&self) -> &[u8] {
+        unsafe {
+            slice::from_raw_parts(self as *const IntRegisters as *const u8, mem::size_of::<IntRegisters>())
+        }
+    }
+}
+
+impl DerefMut for IntRegisters {
+    fn deref_mut(&mut self) -> &mut [u8] {
+        unsafe {
+            slice::from_raw_parts_mut(self as *mut IntRegisters as *mut u8, mem::size_of::<IntRegisters>())
+        }
+    }
+}
+
+#[derive(Clone, Copy, Debug, Default)]
+#[repr(packed)]
+pub struct FloatRegisters {
+    //TODO
+}
+
+impl Deref for FloatRegisters {
+    type Target = [u8];
+    fn deref(&self) -> &[u8] {
+        unsafe {
+            slice::from_raw_parts(self as *const FloatRegisters as *const u8, mem::size_of::<FloatRegisters>())
+        }
+    }
+}
+
+impl DerefMut for FloatRegisters {
+    fn deref_mut(&mut self) -> &mut [u8] {
+        unsafe {
+            slice::from_raw_parts_mut(self as *mut FloatRegisters as *mut u8, mem::size_of::<FloatRegisters>())
+        }
+    }
+}
diff --git a/src/lib.rs b/src/lib.rs
index fb382390ec..09ffda7578 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -23,6 +23,10 @@ mod arch;
 #[path="arch/aarch64.rs"]
 mod arch;
 
+#[cfg(all(any(target_os = "none", target_os = "redox"), target_arch = "riscv64"))]
+#[path="arch/riscv64.rs"]
+mod arch;
+
 #[cfg(all(any(target_os = "none", target_os = "redox"), target_arch = "x86"))]
 #[path="arch/x86.rs"]
 mod arch;