diff --git a/virtio-core/Cargo.toml b/virtio-core/Cargo.toml
index 9a8c197b5d..c060fabe78 100644
--- a/virtio-core/Cargo.toml
+++ b/virtio-core/Cargo.toml
@@ -16,4 +16,5 @@ crossbeam-queue = "0.3.8"
 redox-log = "0.1"
 redox_event = { git = "https://gitlab.redox-os.org/redox-os/event.git" }
 
+common = { path = "../common" }
 pcid = { path = "../pcid" }
diff --git a/virtio-core/src/probe.rs b/virtio-core/src/probe.rs
index 58e9466659..c9fad8427e 100644
--- a/virtio-core/src/probe.rs
+++ b/virtio-core/src/probe.rs
@@ -8,7 +8,7 @@ use pcid_interface::msi::x86_64::DeliveryMode;
 use pcid_interface::msi::{MsixCapability, MsixTableEntry};
 use pcid_interface::*;
 
-use syscall::{Io, PHYSMAP_NO_CACHE, PHYSMAP_WRITE};
+use syscall::Io;
 
 use crate::spec::*;
 use crate::transport::{Error, StandardTransport};
@@ -68,11 +68,12 @@ fn enable_msix(pcid_handle: &mut PcidServerHandle) -> Result<File, Error> {
     };
 
     let address = unsafe {
-        syscall::physmap(
+        common::physmap(
             bar_ptr as usize,
             bar_size as usize,
-            PHYSMAP_WRITE | PHYSMAP_NO_CACHE,
-        )?
+            common::Prot::RW,
+            common::MemoryType::Uncacheable,
+        )? as usize
     };
 
     // Ensure that the table and PBA are be within the BAR.
@@ -186,7 +187,7 @@ pub fn probe_device<'a>(pcid_handle: &mut PcidServerHandle) -> Result<Device<'a>
 
             let size = offset + capability.length as usize;
 
-            let addr = syscall::physmap(aligned_addr, size, PHYSMAP_WRITE | PHYSMAP_NO_CACHE)?;
+            let addr = common::physmap(aligned_addr, size, common::Prot::RW, common::MemoryType::Uncacheable)? as usize;
 
             addr + offset
         };
diff --git a/virtio-core/src/transport.rs b/virtio-core/src/transport.rs
index a1a913d3fd..2f049a1dab 100644
--- a/virtio-core/src/transport.rs
+++ b/virtio-core/src/transport.rs
@@ -2,7 +2,7 @@ use crate::spec::*;
 use crate::utils::align;
 
 use event::EventQueue;
-use syscall::{Dma, PHYSMAP_WRITE};
+use syscall::Dma;
 
 use core::mem::size_of;
 use core::sync::atomic::{AtomicU16, Ordering};
@@ -230,8 +230,9 @@ impl<'a> Available<'a> {
         let size = size.next_multiple_of(syscall::PAGE_SIZE); // align to page size
 
         let addr = unsafe { syscall::physalloc(size) }.map_err(Error::SyscallError)?;
-        let virt =
-            unsafe { syscall::physmap(addr, size, PHYSMAP_WRITE) }.map_err(Error::SyscallError)?;
+        let virt = unsafe {
+            common::physmap(addr, size, common::Prot::RW, common::MemoryType::default())
+        }.map_err(Error::SyscallError)?;
 
         let ring = unsafe { &mut *(virt as *mut AvailableRing) };
 
@@ -275,7 +276,7 @@ impl Drop for Available<'_> {
         log::warn!("virtio-core: dropping 'available' ring at {:#x}", self.addr);
 
         unsafe {
-            syscall::physunmap(self.addr).unwrap();
+            syscall::funmap(self.addr, self.size).unwrap();
             syscall::physfree(self.addr, self.size).unwrap();
         }
     }
@@ -297,7 +298,7 @@ impl<'a> Used<'a> {
 
         let addr = unsafe { syscall::physalloc(size) }.map_err(Error::SyscallError)?;
         let virt =
-            unsafe { syscall::physmap(addr, size, PHYSMAP_WRITE) }.map_err(Error::SyscallError)?;
+            unsafe { common::physmap(addr, size, common::Prot::RW, common::MemoryType::default()) }.map_err(Error::SyscallError)?;
 
         let ring = unsafe { &mut *(virt as *mut UsedRing) };
 
@@ -355,7 +356,7 @@ impl Drop for Used<'_> {
         log::warn!("virtio-core: dropping 'used' ring at {:#x}", self.addr);
 
         unsafe {
-            syscall::physunmap(self.addr).unwrap();
+            syscall::funmap(self.addr, self.size).unwrap();
             syscall::physfree(self.addr, self.size).unwrap();
         }
     }
diff --git a/virtio-gpud/Cargo.toml b/virtio-gpud/Cargo.toml
index c06c18d87e..8979a09873 100644
--- a/virtio-gpud/Cargo.toml
+++ b/virtio-gpud/Cargo.toml
@@ -11,6 +11,7 @@ futures = { version = "0.3.28", features = ["executor"] }
 anyhow = "1.0.71"
 paste = "1.0.13"
 
+common = { path = "../common" }
 virtio-core = { path = "../virtio-core" }
 pcid = { path = "../pcid" }
 inputd = { path = "../inputd" }
diff --git a/virtio-gpud/src/scheme.rs b/virtio-gpud/src/scheme.rs
index b0490c8cce..ed202693e3 100644
--- a/virtio-gpud/src/scheme.rs
+++ b/virtio-gpud/src/scheme.rs
@@ -113,12 +113,13 @@ impl<'a> Display<'a> {
             .next_multiple_of(syscall::PAGE_SIZE);
         let address = unsafe { syscall::physalloc(fb_size) }? as u64;
         let mapped = unsafe {
-            syscall::physmap(
+            common::physmap(
                 address as usize,
                 fb_size,
-                syscall::PhysmapFlags::PHYSMAP_WRITE,
+                common::Prot::RW,
+                common::MemoryType::default(),
             )
-        }?;
+        }? as usize;
 
         unsafe {
             core::ptr::write_bytes(mapped as *mut u8, 255, fb_size);