diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
index 2634fec1b5..17ae234ddc 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
@@ -83,6 +83,12 @@ pub const GAMT_CHKN_BIT_REG: usize = 0x4ABC;
 pub const GEN11_GT_SCRATCH: usize = 0xA18C;
 pub const GEN11_COMMON_SLICE_CHICKEN3: usize = 0x7304;
 pub const GEN11_CHICKEN_DCPR_2: usize = 0x46434;
+pub const GEN11_GACB_PERF_CTRL: usize = 0x4B80;
+pub const GEN11_HASH_CTRL_MASK: u32 = (0x3 << 12) | (0xF << 0);
+pub const GEN11_HASH_CTRL_BIT0: u32 = 1 << 0;
+pub const GEN11_HASH_CTRL_BIT4: u32 = 1 << 12;
+pub const GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC: u32 = 1 << 7;
+pub const GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC: u32 = 1 << 9;
 
 // ---------------------------------------------------------------------------
 // Gen12
diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
index ef22f26f05..038ea9ff07 100644
--- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
+++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
@@ -316,6 +316,30 @@ fn icl_gt_workarounds_init(wal: &mut WorkaroundList) {
     // Gen11 (ICL) inherits Gen9 workarounds.
     gen9_gt_workarounds_init(wal, 0);
 
+    /* WaModifyGamTlbPartitioning:icl */
+    wa_write_clr_set(wal, GEN11_GACB_PERF_CTRL, GEN11_HASH_CTRL_MASK, GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4, "WaModifyGamTlbPartitioning");
+
+    /* Wa_1405766107:icl */
+    wa_write_or(wal, GEN11_LSN_UNSLCVC, GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC, "Wa_1405766107");
+
+    /* Wa_220166154:icl */
+    wa_write_or(wal, GEN8_GAMW_ECO_DEV_RW_IA, GAMW_ECO_DEV_CTX_RELOAD_DISABLE, "Wa_220166154");
+
+    /* Wa_1406463099:icl */
+    wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE, "Wa_1406463099");
+
+    /* Wa_1408615072 / Wa_1407596294:icl */
+    wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS, "Wa_1408615072");
+
+    /* Wa_1407352427:icl */
+    wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS, "Wa_1407352427");
+
+    /* Wa_1406680159:icl */
+    wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, GWUNIT_CLKGATE_DIS, "Wa_1406680159");
+
+    /* Wa_1607087056:icl */
+    wa_write_or(wal, GEN11_SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS, "Wa_1607087056");
+
     /* WaForwardProgressSoftReset:icl */
     wa_write_or(wal, GEN11_GT_SCRATCH, GEN11_WA_FORWARD_PROGRESS_SOFT_RESET, "WaForwardProgressSoftReset");