intel: wire 12 deferred modules into active build

Fix pre-existing compilation errors in modules that were present as
source files but not declared in mod.rs:

- audio_eld: cast u16 copy_len to usize for slice indexing
- dp_fec, dp_uhbr, edp_pll, gpu_reset, hdmi_frl, lspcon:
  DriverError::Initialization now takes String, add .to_string()
- dsc: add missing  import
- guc_submission: DriverError::Buffer now takes String
- vrr: cast VRR_MAX/MIN_FRAME_TIME constants to usize
- rps_rc6: change freq_table() return to &'static to avoid
  borrow checker conflict with self mutation

All 12 modules now compile with zero errors.

local/recipes/gpu/redox-drm/source/src/drivers/intel/audio_eld.rs

@@ -32,7 +32,7 @@ impl EldData {
                             if oui == 0x000C03 {
                                 let sad_start = dtd_offset + 4;
                                 let sad_end = (sad_start + dtd_len - 3).min(128);
-                                let copy_len = sad_end - sad_start;
+                                let copy_len = (sad_end - sad_start) as usize;
                                 eld[..copy_len].copy_from_slice(
                                     &data[sad_start as usize..sad_start as usize + copy_len]);
                                 size = copy_len;

local/recipes/gpu/redox-drm/source/src/drivers/intel/dp_fec.rs

@@ -52,7 +52,7 @@ impl DpFecState {
             if !status.is_empty() && status[0] & DP_FEC_READY != 0 { break; }
             if retries == 0 {
                 warn!("redox-drm-intel: FEC enable timeout on port {}", self.port);
-                return Err(DriverError::Initialization("FEC enable timeout"));
+                return Err(DriverError::Initialization("FEC enable timeout".to_string()));
             }
             retries -= 1;
             std::hint::spin_loop();

local/recipes/gpu/redox-drm/source/src/drivers/intel/dp_uhbr.rs

@@ -73,7 +73,7 @@ impl UhbrLinkTraining {
             if Instant::now() > deadline {
                 warn!("redox-drm-intel: UHBR link training timeout");
                 aux.write_dpcd(DPCD_TRAINING_PATTERN_SET, &[DP_TRAINING_PATTERN_DISABLE])?;
-                return Err(DriverError::Initialization("UHBR link training timeout"));
+                return Err(DriverError::Initialization("UHBR link training timeout".to_string()));
             }
             std::hint::spin_loop();
         }

local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs

@@ -1,6 +1,6 @@
 use std::sync::Arc;
 
-use log::info;
+use log::{debug, info};
 use redox_driver_sys::memory::MmioRegion;
 
 use super::dp_aux::DpAux;

local/recipes/gpu/redox-drm/source/src/drivers/intel/edp_pll.rs

@@ -98,7 +98,7 @@ impl EdpPll {
         loop {
             if self.mmio.read32(EDP_PLL_CTL) & EDP_PLL_CTL_LOCK != 0 { return Ok(()); }
             if std::time::Instant::now() > deadline {
-                return Err(DriverError::Initialization("eDP PLL lock timeout"));
+                return Err(DriverError::Initialization("eDP PLL lock timeout".to_string()));
             }
             std::hint::spin_loop();
         }

local/recipes/gpu/redox-drm/source/src/drivers/intel/gpu_reset.rs

@@ -51,7 +51,7 @@ impl GpuResetManager {
             if status & RESET_CTL_READY_TO_RESET != 0 { break; }
             if Instant::now() > deadline {
                 error!("redox-drm-intel: engine reset timeout for ring {:#06x}", ring_base);
-                return Err(DriverError::Initialization("engine reset timeout"));
+                return Err(DriverError::Initialization("engine reset timeout".to_string()));
             }
             std::hint::spin_loop();
         }
@@ -94,7 +94,7 @@ impl GpuResetManager {
             if status & val == 0 { break; }
             if Instant::now() > deadline {
                 error!("redox-drm-intel: global GPU reset timeout — status {:#x}", status);
-                return Err(DriverError::Initialization("global GPU reset timeout"));
+                return Err(DriverError::Initialization("global GPU reset timeout".to_string()));
             }
             std::hint::spin_loop();
         }
@@ -111,7 +111,7 @@ impl GpuResetManager {
         loop {
             if self.mmio.read32(GEN6_GDRST) & domain == 0 { break; }
             if Instant::now() > deadline {
-                return Err(DriverError::Initialization("reset domain timeout"));
+                return Err(DriverError::Initialization("reset domain timeout".to_string()));
             }
             std::hint::spin_loop();
         }

local/recipes/gpu/redox-drm/source/src/drivers/intel/guc_submission.rs

@@ -63,7 +63,7 @@ impl GuCSubmission {
         let needed = work_item.len() as u32 * 4 + 8;
 
         if used + needed > self.wq_size - 64 {
-            return Err(DriverError::Buffer("GuC WQ full"));
+            return Err(DriverError::Buffer("GuC WQ full".to_string()));
         }
 
         self.mmio.write32(GUC_WQ_TAIL, (tail + needed) & (self.wq_size - 1));

local/recipes/gpu/redox-drm/source/src/drivers/intel/hdmi_frl.rs

@@ -86,7 +86,7 @@ impl HdmiFrlState {
                 if !status.is_empty() && status[0] & HDMI_FRL_LTP_DONE != 0 { break; }
             }
             if std::time::Instant::now() > timeout {
-                return Err(DriverError::Initialization("HDMI FRL link training timeout"));
+                return Err(DriverError::Initialization("HDMI FRL link training timeout".to_string()));
             }
             std::hint::spin_loop();
         }

local/recipes/gpu/redox-drm/source/src/drivers/intel/lspcon.rs

@@ -90,7 +90,7 @@ impl Lspcon {
             }
             if Instant::now() > deadline {
                 warn!("redox-drm-intel: LSPCON mode change timeout");
-                return Err(DriverError::Initialization("LSPCON mode change timeout"));
+                return Err(DriverError::Initialization("LSPCON mode change timeout".to_string()));
             }
             std::hint::spin_loop();
         }

local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs

@@ -1,4 +1,5 @@
 pub mod alpm;
+pub mod audio_eld;
 pub mod bandwidth;
 pub mod cdclk_tables;
 pub mod color_lmem;
@@ -8,13 +9,23 @@ pub mod display_irq;
 pub mod dkl_phy;
 pub mod dmc_power;
 pub mod dp_audio;
+pub mod dp_fec;
 pub mod dp_phy;
+pub mod dp_uhbr;
+pub mod dsc;
+pub mod edp_pll;
+pub mod gpu_reset;
+pub mod guc_submission;
+pub mod hdmi_frl;
 pub mod hdmi_scrambler;
+pub mod lspcon;
 pub mod mg_pll;
 pub mod panel_fitter;
 pub mod psr_full;
+pub mod rps_rc6;
 pub mod snps_phy;
 pub mod tc_port;
+pub mod vrr;
 pub mod workarounds;
 pub mod backlight;
 pub mod batch;

local/recipes/gpu/redox-drm/source/src/drivers/intel/rps_rc6.rs

@@ -150,7 +150,7 @@ impl RpsRc6Manager {
             .map(|&(mhz, _)| mhz).unwrap_or(0)
     }
 
-    fn freq_table(&self) -> &[(u32, u32)] {
+    fn freq_table(&self) -> &'static [(u32, u32)] {
         if self.device_info.is_gen12_or_later() {
             FREQ_TABLE_GEN12
         } else {

local/recipes/gpu/redox-drm/source/src/drivers/intel/vrr.rs

@@ -10,8 +10,8 @@ const VRR_CTL_BASE: usize = 0x60420;
 const VRR_CTL_ENABLE: u32 = 1 << 31;
 const VRR_CTL_FLIP_LINE_SHIFT: u32 = 0;
 const VRR_CTL_FLIP_LINE_MASK: u32 = 0x1FFF;
-const VRR_MAX_FRAME_TIME: u32 = 0x60424;
-const VRR_MIN_FRAME_TIME: u32 = 0x60428;
+const VRR_MAX_FRAME_TIME: usize = 0x60424;
+const VRR_MIN_FRAME_TIME: usize = 0x60428;
 const VRR_STATUS_BASE: usize = 0x60440;
 const VRR_TRANS_STRIDE: usize = 0x1000;