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milestone: desktop path Phases 1-5

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Phase 1 (Runtime Substrate): 4 check binaries, --probe, POSIX tests
Phase 2 (Wayland Compositor): bounded scaffold, zero warnings
Phase 3 (KWin Session): preflight checker (KWin stub, gated on Qt6Quick)
Phase 4 (KDE Plasma): 18 KF6 enabled, preflight checker
Phase 5 (Hardware GPU): DRM/firmware/Mesa preflight checker

Build: zero warnings, all scripts syntax-clean. Oracle-verified.
This commit is contained in:
Vasilito
2026-04-29 09:54:06 +01:00
parent b23714f542
commit 8acc73d774
508 changed files with 76526 additions and 396 deletions
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recipes/core/base/drivers/net/ixgbed/Cargo.toml
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[package]
name = "ixgbed"
description = "Intel 10 Gigabit ethernet driver"
version = "1.0.0"
edition = "2021"
[dependencies]
bitflags.workspace = true
libredox.workspace = true
redox_event.workspace = true
redox_syscall.workspace = true
common = { path = "../../common" }
daemon = { path = "../../../daemon" }
driver-network = { path = "../driver-network" }
pcid = { path = "../../pcid" }
[lints]
workspace = true
recipes/core/base/drivers/net/ixgbed/LICENSE
+661
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If your software can interact with users remotely through a computer
network, you should also make sure that it provides a way for users to
get its source. For example, if your program is a web application, its
interface could display a "Source" link that leads users to an archive
of the code. There are many ways you could offer source, and different
solutions will be better for different programs; see section 13 for the
specific requirements.
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU AGPL, see
<https://www.gnu.org/licenses/>.
recipes/core/base/drivers/net/ixgbed/README.md
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# ixgbed (a.k.a. ixy.rs on Redox)
ixgbed is the Redox port of [ixy.rs](https://github.com/ixy-languages/ixy.rs), a Rust rewrite of the [ixy](https://github.com/emmericp/ixy) userspace network driver.
It is designed to be readable, idiomatic Rust code.
It supports Intel 82599 10GbE NICs (`ixgbe` family).
## Features
* first 10 Gbit/s network driver on Redox
* transmitting 250 times faster than e1000 / rtl8168 driver
* MSI-X interrupts (not supported by Redox yet)
* less than 1000 lines of code for the driver
* documented code
## Build instructions
See the [Redox README](https://gitlab.redox-os.org/redox-os/redox/blob/master/README.md) for build instructions.
To run ixgbed on Redox (in case the driver is not shipped with Redox anymore)
* clone this project into `cookbook/recipes/drivers/source/`
* create an entry for ixgbed in `cookbook/recipes/drivers/source/Cargo.toml`
* check if your ixgbe device is included in `config.toml`
* touch `filesystem.toml` in Redox's root directory, build Redox and run it
## Usage
To test the driver's transmit and forwarding capabilities, have a look at [rheinfall](https://github.com/ackxolotl/rheinfall), a simple packet generator / forwarder application.
## Docs
ixgbed contains documentation that can be created and viewed by running
```
cargo doc --open
```
recipes/core/base/drivers/net/ixgbed/config.toml
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[[drivers]]
name = "Intel 10G NIC"
class = 0x02
ids = { 0x8086 = [0x10F7, 0x1514, 0x1517, 0x151C, 0x10F9, 0x10FB, 0x152a, 0x1529, 0x1507, 0x154D, 0x1557, 0x10FC, 0x10F8, 0x154F, 0x1528, 0x154A, 0x1558, 0x1560, 0x1563, 0x15D1, 0x15AA, 0x15AB, 0x15AC, 0x15AD, 0x15AE, 0x15B0, 0x15C2, 0x15C3, 0x15C4, 0x15C6, 0x15C7, 0x15C8, 0x15CE, 0x15E4, 0x15E5, 0x10ED, 0x1515, 0x1565, 0x15A8, 0x15C5] }
command = ["ixgbed"]
recipes/core/base/drivers/net/ixgbed/src/device.rs
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use std::convert::TryInto;
use std::time::{Duration, Instant};
use std::{cmp, mem, ptr, slice, thread};
use driver_network::NetworkAdapter;
use syscall::error::Result;
use common::dma::Dma;
use crate::ixgbe::*;
pub struct Intel8259x {
base: usize,
size: usize,
receive_buffer: [Dma<[u8; 16384]>; 32],
receive_ring: Dma<[ixgbe_adv_rx_desc; 32]>,
receive_index: usize,
transmit_buffer: [Dma<[u8; 16384]>; 32],
transmit_ring: Dma<[ixgbe_adv_tx_desc; 32]>,
transmit_ring_free: usize,
transmit_index: usize,
transmit_clean_index: usize,
mac_address: [u8; 6],
}
fn wrap_ring(index: usize, ring_size: usize) -> usize {
(index + 1) & (ring_size - 1)
}
impl NetworkAdapter for Intel8259x {
fn mac_address(&mut self) -> [u8; 6] {
self.mac_address
}
fn available_for_read(&mut self) -> usize {
self.next_read()
}
fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
let desc = unsafe {
&mut *(self.receive_ring.as_ptr().add(self.receive_index) as *mut ixgbe_adv_rx_desc)
};
let status = unsafe { desc.wb.upper.status_error };
if (status & IXGBE_RXDADV_STAT_DD) != 0 {
if (status & IXGBE_RXDADV_STAT_EOP) == 0 {
panic!("increase buffer size or decrease MTU")
}
let data = unsafe {
&self.receive_buffer[self.receive_index][..desc.wb.upper.length as usize]
};
let i = cmp::min(buf.len(), data.len());
buf[..i].copy_from_slice(&data[..i]);
desc.read.pkt_addr = self.receive_buffer[self.receive_index].physical() as u64;
desc.read.hdr_addr = 0;
self.write_reg(IXGBE_RDT(0), self.receive_index as u32);
self.receive_index = wrap_ring(self.receive_index, self.receive_ring.len());
return Ok(Some(i));
}
Ok(None)
}
fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
if self.transmit_ring_free == 0 {
loop {
let desc = unsafe {
&*(self.transmit_ring.as_ptr().add(self.transmit_clean_index)
as *const ixgbe_adv_tx_desc)
};
if (unsafe { desc.wb.status } & IXGBE_ADVTXD_STAT_DD) != 0 {
self.transmit_clean_index =
wrap_ring(self.transmit_clean_index, self.transmit_ring.len());
self.transmit_ring_free += 1;
} else if self.transmit_ring_free > 0 {
break;
}
if self.transmit_ring_free >= self.transmit_ring.len() {
break;
}
}
}
let desc = unsafe {
&mut *(self.transmit_ring.as_ptr().add(self.transmit_index) as *mut ixgbe_adv_tx_desc)
};
let data = unsafe {
slice::from_raw_parts_mut(
self.transmit_buffer[self.transmit_index].as_ptr() as *mut u8,
cmp::min(buf.len(), self.transmit_buffer[self.transmit_index].len()) as usize,
)
};
let i = cmp::min(buf.len(), data.len());
data[..i].copy_from_slice(&buf[..i]);
desc.read.cmd_type_len = IXGBE_ADVTXD_DCMD_EOP
| IXGBE_ADVTXD_DCMD_RS
| IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
| IXGBE_ADVTXD_DTYP_DATA
| buf.len() as u32;
desc.read.olinfo_status = (buf.len() as u32) << IXGBE_ADVTXD_PAYLEN_SHIFT;
self.transmit_index = wrap_ring(self.transmit_index, self.transmit_ring.len());
self.transmit_ring_free -= 1;
self.write_reg(IXGBE_TDT(0), self.transmit_index as u32);
Ok(i)
}
}
impl Intel8259x {
/// Returns an initialized `Intel8259x` on success.
pub fn new(base: usize, size: usize) -> Result<Self> {
#[rustfmt::skip]
let mut module = Intel8259x {
base,
size,
receive_buffer: (0..32)
.map(|_| Ok(unsafe { Dma::zeroed()?.assume_init() }))
.collect::<Result<Vec<_>>>()?
.try_into()
.unwrap_or_else(|_| unreachable!()),
receive_ring: unsafe { Dma::zeroed()?.assume_init() },
transmit_buffer: (0..32)
.map(|_| Ok(unsafe { Dma::zeroed()?.assume_init() }))
.collect::<Result<Vec<_>>>()?
.try_into()
.unwrap_or_else(|_| unreachable!()),
receive_index: 0,
transmit_ring: unsafe { Dma::zeroed()?.assume_init() },
transmit_ring_free: 32,
transmit_index: 0,
transmit_clean_index: 0,
mac_address: [0; 6],
};
module.init();
Ok(module)
}
pub fn irq(&self) -> bool {
let icr = self.read_reg(IXGBE_EICR);
icr != 0
}
pub fn next_read(&self) -> usize {
let desc = unsafe {
&*(self.receive_ring.as_ptr().add(self.receive_index) as *const ixgbe_adv_rx_desc)
};
let status = unsafe { desc.wb.upper.status_error };
if (status & IXGBE_RXDADV_STAT_DD) != 0 {
if (status & IXGBE_RXDADV_STAT_EOP) == 0 {
panic!("increase buffer size or decrease MTU")
}
return unsafe { desc.wb.upper.length as usize };
}
0
}
/// Returns the mac address of this device.
pub fn get_mac_addr(&self) -> [u8; 6] {
let low = self.read_reg(IXGBE_RAL(0));
let high = self.read_reg(IXGBE_RAH(0));
[
(low & 0xff) as u8,
(low >> 8 & 0xff) as u8,
(low >> 16 & 0xff) as u8,
(low >> 24) as u8,
(high & 0xff) as u8,
(high >> 8 & 0xff) as u8,
]
}
/// Sets the mac address of this device.
#[allow(dead_code)]
pub fn set_mac_addr(&mut self, mac: [u8; 6]) {
let low: u32 = u32::from(mac[0])
+ (u32::from(mac[1]) << 8)
+ (u32::from(mac[2]) << 16)
+ (u32::from(mac[3]) << 24);
let high: u32 = u32::from(mac[4]) + (u32::from(mac[5]) << 8);
self.write_reg(IXGBE_RAL(0), low);
self.write_reg(IXGBE_RAH(0), high);
self.mac_address = mac;
}
/// Returns the register at `self.base` + `register`.
///
/// # Panics
///
/// Panics if `self.base` + `register` does not belong to the mapped memory of the PCIe device.
fn read_reg(&self, register: u32) -> u32 {
assert!(
register as usize <= self.size - 4 as usize,
"MMIO access out of bounds"
);
unsafe { ptr::read_volatile((self.base + register as usize) as *mut u32) }
}
/// Sets the register at `self.base` + `register`.
///
/// # Panics
///
/// Panics if `self.base` + `register` does not belong to the mapped memory of the PCIe device.
fn write_reg(&self, register: u32, data: u32) -> u32 {
assert!(
register as usize <= self.size - 4 as usize,
"MMIO access out of bounds"
);
unsafe {
ptr::write_volatile((self.base + register as usize) as *mut u32, data);
ptr::read_volatile((self.base + register as usize) as *mut u32)
}
}
fn write_flag(&self, register: u32, flags: u32) {
self.write_reg(register, self.read_reg(register) | flags);
}
fn clear_flag(&self, register: u32, flags: u32) {
self.write_reg(register, self.read_reg(register) & !flags);
}
fn wait_clear_reg(&self, register: u32, value: u32) {
loop {
let current = self.read_reg(register);
if (current & value) == 0 {
break;
}
thread::sleep(Duration::from_millis(100));
}
}
fn wait_write_reg(&self, register: u32, value: u32) {
loop {
let current = self.read_reg(register);
if (current & value) == value {
break;
}
thread::sleep(Duration::from_millis(100));
}
}
/// Resets and initializes an ixgbe device.
fn init(&mut self) {
// section 4.6.3.1 - disable all interrupts
self.write_reg(IXGBE_EIMC, 0x7fff_ffff);
// section 4.6.3.2
self.write_reg(IXGBE_CTRL, IXGBE_CTRL_RST_MASK);
self.wait_clear_reg(IXGBE_CTRL, IXGBE_CTRL_RST_MASK);
thread::sleep(Duration::from_millis(10));
// section 4.6.3.1 - disable interrupts again after reset
self.write_reg(IXGBE_EIMC, 0x7fff_ffff);
let mac = self.get_mac_addr();
println!(
" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]
);
self.mac_address = mac;
// section 4.6.3 - wait for EEPROM auto read completion
self.wait_write_reg(IXGBE_EEC, IXGBE_EEC_ARD);
// section 4.6.3 - wait for dma initialization done
self.wait_write_reg(
IXGBE_RDRXCTL,
IXGBE_RDRXCTL_DMAIDONE | IXGBE_RDRXCTL_RESERVED_BITS,
);
// section 4.6.4 - initialize link (auto negotiation)
self.init_link();
// section 4.6.5 - statistical counters
// reset-on-read registers, just read them once
self.reset_stats();
// section 4.6.7 - init rx
self.init_rx();
// section 4.6.8 - init tx
self.init_tx();
// start a single receive queue/ring
self.start_rx_queue(0);
// start a single transmit queue/ring
self.start_tx_queue(0);
// section 4.6.3.9 - enable interrupts
self.enable_msix_interrupt(0);
// wait some time for the link to come up
self.wait_for_link();
}
/// Resets the stats of this device.
fn reset_stats(&self) {
self.read_reg(IXGBE_GPRC);
self.read_reg(IXGBE_GPTC);
self.read_reg(IXGBE_GORCL);
self.read_reg(IXGBE_GORCH);
self.read_reg(IXGBE_GOTCL);
self.read_reg(IXGBE_GOTCH);
}
// sections 4.6.7
/// Initializes the rx queues of this device.
fn init_rx(&mut self) {
// disable rx while re-configuring it
self.clear_flag(IXGBE_RXCTRL, IXGBE_RXCTRL_RXEN);
// section 4.6.11.3.4 - allocate all queues and traffic to PB0
self.write_reg(IXGBE_RXPBSIZE(0), IXGBE_RXPBSIZE_128KB);
for i in 1..8 {
self.write_reg(IXGBE_RXPBSIZE(i), 0);
}
// enable CRC offloading
self.write_flag(IXGBE_HLREG0, IXGBE_HLREG0_RXCRCSTRP);
self.write_flag(IXGBE_RDRXCTL, IXGBE_RDRXCTL_CRCSTRIP);
// accept broadcast packets
self.write_flag(IXGBE_FCTRL, IXGBE_FCTRL_BAM);
// configure a single receive queue/ring
let i: u32 = 0;
// enable advanced rx descriptors
self.write_reg(
IXGBE_SRRCTL(i),
(self.read_reg(IXGBE_SRRCTL(i)) & !IXGBE_SRRCTL_DESCTYPE_MASK)
| IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF,
);
// let nic drop packets if no rx descriptor is available instead of buffering them
self.write_flag(IXGBE_SRRCTL(i), IXGBE_SRRCTL_DROP_EN);
self.write_reg(IXGBE_RDBAL(i), self.receive_ring.physical() as u32);
self.write_reg(
IXGBE_RDBAH(i),
((self.receive_ring.physical() as u64) >> 32) as u32,
);
self.write_reg(
IXGBE_RDLEN(i),
(self.receive_ring.len() * mem::size_of::<ixgbe_adv_rx_desc>()) as u32,
);
// set ring to empty at start
self.write_reg(IXGBE_RDH(i), 0);
self.write_reg(IXGBE_RDT(i), 0);
// last sentence of section 4.6.7 - set some magic bits
self.write_flag(IXGBE_CTRL_EXT, IXGBE_CTRL_EXT_NS_DIS);
// probably a broken feature, this flag is initialized with 1 but has to be set to 0
self.clear_flag(IXGBE_DCA_RXCTRL(i), 1 << 12);
// enable promisc mode by default to make testing easier
// this has to be done when the rxctrl.rxen bit is not set
self.set_promisc(true);
// start rx
self.write_flag(IXGBE_RXCTRL, IXGBE_RXCTRL_RXEN);
}
// section 4.6.8
/// Initializes the tx queues of this device.
fn init_tx(&mut self) {
// crc offload and small packet padding
self.write_flag(IXGBE_HLREG0, IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
// section 4.6.11.3.4 - set default buffer size allocations
self.write_reg(IXGBE_TXPBSIZE(0), IXGBE_TXPBSIZE_40KB);
for i in 1..8 {
self.write_reg(IXGBE_TXPBSIZE(i), 0);
}
// required when not using DCB/VTd
self.write_reg(IXGBE_DTXMXSZRQ, 0xfff);
self.clear_flag(IXGBE_RTTDCS, IXGBE_RTTDCS_ARBDIS);
// configure a single transmit queue/ring
let i: u32 = 0;
// section 7.1.9 - setup descriptor ring
self.write_reg(IXGBE_TDBAL(i), self.transmit_ring.physical() as u32);
self.write_reg(
IXGBE_TDBAH(i),
((self.transmit_ring.physical() as u64) >> 32) as u32,
);
self.write_reg(
IXGBE_TDLEN(i),
(self.transmit_ring.len() * mem::size_of::<ixgbe_adv_tx_desc>()) as u32,
);
// descriptor writeback magic values, important to get good performance and low PCIe overhead
// see 7.2.3.4.1 and 7.2.3.5 for an explanation of these values and how to find good ones
// we just use the defaults from DPDK here, but this is a potentially interesting point for optimizations
let mut txdctl = self.read_reg(IXGBE_TXDCTL(i));
// there are no defines for this in ixgbe.rs for some reason
// pthresh: 6:0, hthresh: 14:8, wthresh: 22:16
txdctl &= !(0x3F | (0x3F << 8) | (0x3F << 16));
txdctl |= 36 | (8 << 8) | (4 << 16);
self.write_reg(IXGBE_TXDCTL(i), txdctl);
// final step: enable DMA
self.write_reg(IXGBE_DMATXCTL, IXGBE_DMATXCTL_TE);
}
/// Sets the rx queues` descriptors and enables the queues.
///
/// # Panics
/// Panics if length of `self.receive_ring` is not a power of 2.
fn start_rx_queue(&mut self, queue_id: u16) {
if self.receive_ring.len() & (self.receive_ring.len() - 1) != 0 {
panic!("number of receive queue entries must be a power of 2");
}
for i in 0..self.receive_ring.len() {
self.receive_ring[i].read.pkt_addr = self.receive_buffer[i].physical() as u64;
self.receive_ring[i].read.hdr_addr = 0;
}
// enable queue and wait if necessary
self.write_flag(IXGBE_RXDCTL(u32::from(queue_id)), IXGBE_RXDCTL_ENABLE);
self.wait_write_reg(IXGBE_RXDCTL(u32::from(queue_id)), IXGBE_RXDCTL_ENABLE);
// rx queue starts out full
self.write_reg(IXGBE_RDH(u32::from(queue_id)), 0);
// was set to 0 before in the init function
self.write_reg(
IXGBE_RDT(u32::from(queue_id)),
(self.receive_ring.len() - 1) as u32,
);
}
/// Enables the tx queues.
///
/// # Panics
/// Panics if length of `self.transmit_ring` is not a power of 2.
fn start_tx_queue(&mut self, queue_id: u16) {
if self.transmit_ring.len() & (self.transmit_ring.len() - 1) != 0 {
panic!("number of receive queue entries must be a power of 2");
}
for i in 0..self.transmit_ring.len() {
self.transmit_ring[i].read.buffer_addr = self.transmit_buffer[i].physical() as u64;
}
// tx queue starts out empty
self.write_reg(IXGBE_TDH(u32::from(queue_id)), 0);
self.write_reg(IXGBE_TDT(u32::from(queue_id)), 0);
// enable queue and wait if necessary
self.write_flag(IXGBE_TXDCTL(u32::from(queue_id)), IXGBE_TXDCTL_ENABLE);
self.wait_write_reg(IXGBE_TXDCTL(u32::from(queue_id)), IXGBE_TXDCTL_ENABLE);
}
// see section 4.6.4
/// Initializes the link of this device.
fn init_link(&self) {
// link auto-configuration register should already be set correctly, we're resetting it anyway
self.write_reg(
IXGBE_AUTOC,
(self.read_reg(IXGBE_AUTOC) & !IXGBE_AUTOC_LMS_MASK) | IXGBE_AUTOC_LMS_10G_SERIAL,
);
self.write_reg(
IXGBE_AUTOC,
(self.read_reg(IXGBE_AUTOC) & !IXGBE_AUTOC_10G_PMA_PMD_MASK) | IXGBE_AUTOC_10G_XAUI,
);
// negotiate link
self.write_flag(IXGBE_AUTOC, IXGBE_AUTOC_AN_RESTART);
// datasheet wants us to wait for the link here, but we can continue and wait afterwards
}
/// Waits for the link to come up.
fn wait_for_link(&self) {
println!(" - waiting for link");
let time = Instant::now();
let mut speed = self.get_link_speed();
while speed == 0 && time.elapsed().as_secs() < 10 {
thread::sleep(Duration::from_millis(100));
speed = self.get_link_speed();
}
println!(" - link speed is {} Mbit/s", self.get_link_speed());
}
/// Enables or disables promisc mode of this device.
fn set_promisc(&self, enabled: bool) {
if enabled {
self.write_flag(IXGBE_FCTRL, IXGBE_FCTRL_MPE | IXGBE_FCTRL_UPE);
} else {
self.clear_flag(IXGBE_FCTRL, IXGBE_FCTRL_MPE | IXGBE_FCTRL_UPE);
}
}
/// Set the IVAR registers, mapping interrupt causes to vectors.
fn set_ivar(&mut self, direction: i8, queue_id: u16, mut msix_vector: u8) {
let index = ((16 * (queue_id & 1)) as i16 + i16::from(8 * direction)) as u32;
msix_vector |= IXGBE_IVAR_ALLOC_VAL as u8;
let mut ivar = self.read_reg(IXGBE_IVAR(u32::from(queue_id >> 1)));
ivar &= !(0xFF << index);
ivar |= u32::from(msix_vector << index);
self.write_reg(IXGBE_IVAR(u32::from(queue_id >> 1)), ivar);
}
/// Enable MSI-X interrupt for a queue.
fn enable_msix_interrupt(&mut self, queue_id: u16) {
// Step 1: The software driver associates between interrupt causes and MSI-X vectors and the
//throttling timers EITR[n] by programming the IVAR[n] and IVAR_MISC registers.
self.set_ivar(0, queue_id, queue_id as u8);
// Step 2: Program SRRCTL[n].RDMTS (per receive queue) if software uses the receive
// descriptor minimum threshold interrupt
// Step 3: The EIAC[n] registers should be set to auto clear for transmit and receive interrupt
// causes (for best performance). The EIAC bits that control the other and TCP timer
// interrupt causes should be set to 0b (no auto clear).
self.write_reg(IXGBE_EIAC, IXGBE_EICR_RTX_QUEUE);
// Step 4: Set the auto mask in the EIAM register according to the preferred mode of operation.
// Step 5: Set the interrupt throttling in EITR[n] and GPIE according to the preferred mode of operation.
// Step 6: Software enables the required interrupt causes by setting the EIMS register
let mut mask: u32 = self.read_reg(IXGBE_EIMS);
mask |= 1 << queue_id;
self.write_reg(IXGBE_EIMS, mask);
}
/// Returns the link speed of this device.
fn get_link_speed(&self) -> u16 {
let speed = self.read_reg(IXGBE_LINKS);
if (speed & IXGBE_LINKS_UP) == 0 {
return 0;
}
match speed & IXGBE_LINKS_SPEED_82599 {
IXGBE_LINKS_SPEED_100_82599 => 100,
IXGBE_LINKS_SPEED_1G_82599 => 1000,
IXGBE_LINKS_SPEED_10G_82599 => 10000,
_ => 0,
}
}
}
recipes/core/base/drivers/net/ixgbed/src/ixgbe.rs
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#![allow(non_snake_case)]
#![allow(non_camel_case_types)]
#![allow(non_upper_case_globals)]
#![allow(clippy::unreadable_literal)]
pub const IXGBE_EIMC: u32 = 0x00888;
pub const IXGBE_CTRL: u32 = 0x00000;
pub const IXGBE_CTRL_LNK_RST: u32 = 0x00000008; /* Link Reset. Resets everything. */
pub const IXGBE_CTRL_RST: u32 = 0x04000000; /* Reset (SW) */
pub const IXGBE_CTRL_RST_MASK: u32 = IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST;
pub const IXGBE_EEC: u32 = 0x10010;
pub const IXGBE_EEC_ARD: u32 = 0x00000200; /* EEPROM Auto Read Done */
pub const IXGBE_RDRXCTL: u32 = 0x02F00;
pub const IXGBE_RDRXCTL_RESERVED_BITS: u32 = 1 << 25 | 1 << 26;
pub const IXGBE_RDRXCTL_DMAIDONE: u32 = 0x00000008; /* DMA init cycle done */
pub const IXGBE_AUTOC: u32 = 0x042A0;
pub const IXGBE_AUTOC_LMS_SHIFT: u32 = 13;
pub const IXGBE_AUTOC_LMS_MASK: u32 = 0x7 << IXGBE_AUTOC_LMS_SHIFT;
pub const IXGBE_AUTOC_LMS_10G_SERIAL: u32 = 0x3 << IXGBE_AUTOC_LMS_SHIFT;
pub const IXGBE_AUTOC_10G_PMA_PMD_MASK: u32 = 0x00000180;
pub const IXGBE_AUTOC_10G_PMA_PMD_SHIFT: u32 = 7;
pub const IXGBE_AUTOC_10G_XAUI: u32 = 0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT;
pub const IXGBE_AUTOC_AN_RESTART: u32 = 0x00001000;
pub const IXGBE_GPRC: u32 = 0x04074;
pub const IXGBE_GPTC: u32 = 0x04080;
pub const IXGBE_GORCL: u32 = 0x04088;
pub const IXGBE_GORCH: u32 = 0x0408C;
pub const IXGBE_GOTCL: u32 = 0x04090;
pub const IXGBE_GOTCH: u32 = 0x04094;
pub const IXGBE_RXCTRL: u32 = 0x03000;
pub const IXGBE_RXCTRL_RXEN: u32 = 0x00000001; /* Enable Receiver */
pub fn IXGBE_RXPBSIZE(i: u32) -> u32 {
0x03C00 + (i * 4)
}
pub const IXGBE_RXPBSIZE_128KB: u32 = 0x00020000; /* 128KB Packet Buffer */
pub const IXGBE_HLREG0: u32 = 0x04240;
pub const IXGBE_HLREG0_RXCRCSTRP: u32 = 0x00000002; /* bit 1 */
pub const IXGBE_RDRXCTL_CRCSTRIP: u32 = 0x00000002; /* CRC Strip */
pub const IXGBE_FCTRL: u32 = 0x05080;
pub const IXGBE_FCTRL_BAM: u32 = 0x00000400; /* Broadcast Accept Mode */
pub fn IXGBE_SRRCTL(i: u32) -> u32 {
if i <= 15 {
0x02100 + (i * 4)
} else if i < 64 {
0x01014 + (i * 0x40)
} else {
0x0D014 + ((i - 64) * 0x40)
}
}
pub const IXGBE_SRRCTL_DESCTYPE_MASK: u32 = 0x0E000000;
pub const IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF: u32 = 0x02000000;
pub const IXGBE_SRRCTL_DROP_EN: u32 = 0x10000000;
pub fn IXGBE_RDBAL(i: u32) -> u32 {
if i < 64 {
0x01000 + (i * 0x40)
} else {
0x0D000 + ((i - 64) * 0x40)
}
}
pub fn IXGBE_RDBAH(i: u32) -> u32 {
if i < 64 {
0x01004 + (i * 0x40)
} else {
0x0D004 + ((i - 64) * 0x40)
}
}
pub fn IXGBE_RDLEN(i: u32) -> u32 {
if i < 64 {
0x01008 + (i * 0x40)
} else {
0x0D008 + ((i - 64) * 0x40)
}
}
pub fn IXGBE_RDH(i: u32) -> u32 {
if i < 64 {
0x01010 + (i * 0x40)
} else {
0x0D010 + ((i - 64) * 0x40)
}
}
pub fn IXGBE_RDT(i: u32) -> u32 {
if i < 64 {
0x01018 + (i * 0x40)
} else {
0x0D018 + ((i - 64) * 0x40)
}
}
pub const IXGBE_CTRL_EXT: u32 = 0x00018;
pub const IXGBE_CTRL_EXT_NS_DIS: u32 = 0x00010000; /* No Snoop disable */
pub fn IXGBE_DCA_RXCTRL(i: u32) -> u32 {
if i <= 15 {
0x02200 + (i * 4)
} else if i < 64 {
0x0100C + (i * 0x40)
} else {
0x0D00C + ((i - 64) * 0x40)
}
}
pub const IXGBE_HLREG0_TXCRCEN: u32 = 0x00000001; /* bit 0 */
pub const IXGBE_HLREG0_TXPADEN: u32 = 0x00000400; /* bit 10 */
pub fn IXGBE_TXPBSIZE(i: u32) -> u32 {
0x0CC00 + (i * 4)
} /* 8 of these */
pub const IXGBE_TXPBSIZE_40KB: u32 = 0x0000A000; /* 40KB Packet Buffer */
pub const IXGBE_DTXMXSZRQ: u32 = 0x08100;
pub const IXGBE_RTTDCS: u32 = 0x04900;
pub const IXGBE_RTTDCS_ARBDIS: u32 = 0x00000040; /* DCB arbiter disable */
pub fn IXGBE_TDBAL(i: u32) -> u32 {
0x06000 + (i * 0x40)
} /* 32 of them (0-31)*/
pub fn IXGBE_TDBAH(i: u32) -> u32 {
0x06004 + (i * 0x40)
}
pub fn IXGBE_TDLEN(i: u32) -> u32 {
0x06008 + (i * 0x40)
}
pub fn IXGBE_TXDCTL(i: u32) -> u32 {
0x06028 + (i * 0x40)
}
pub const IXGBE_DMATXCTL: u32 = 0x04A80;
pub const IXGBE_DMATXCTL_TE: u32 = 0x1; /* Transmit Enable */
pub fn IXGBE_RXDCTL(i: u32) -> u32 {
if i < 64 {
0x01028 + (i * 0x40)
} else {
0x0D028 + ((i - 64) * 0x40)
}
}
pub const IXGBE_RXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Rx Queue */
pub const IXGBE_TXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Tx Queue */
pub fn IXGBE_TDH(i: u32) -> u32 {
0x06010 + (i * 0x40)
}
pub fn IXGBE_TDT(i: u32) -> u32 {
0x06018 + (i * 0x40)
}
pub const IXGBE_FCTRL_MPE: u32 = 0x00000100; /* Multicast Promiscuous Ena*/
pub const IXGBE_FCTRL_UPE: u32 = 0x00000200; /* Unicast Promiscuous Ena */
pub const IXGBE_LINKS: u32 = 0x042A4;
pub const IXGBE_LINKS_UP: u32 = 0x40000000;
pub const IXGBE_LINKS_SPEED_82599: u32 = 0x30000000;
pub const IXGBE_LINKS_SPEED_100_82599: u32 = 0x10000000;
pub const IXGBE_LINKS_SPEED_1G_82599: u32 = 0x20000000;
pub const IXGBE_LINKS_SPEED_10G_82599: u32 = 0x30000000;
pub fn IXGBE_RAL(i: u32) -> u32 {
if i <= 15 {
0x05400 + (i * 8)
} else {
0x0A200 + (i * 8)
}
}
pub fn IXGBE_RAH(i: u32) -> u32 {
if i <= 15 {
0x05404 + (i * 8)
} else {
0x0A204 + (i * 8)
}
}
pub const IXGBE_RXD_STAT_DD: u32 = 0x01; /* Descriptor Done */
pub const IXGBE_RXD_STAT_EOP: u32 = 0x02; /* End of Packet */
pub const IXGBE_RXDADV_STAT_DD: u32 = IXGBE_RXD_STAT_DD; /* Done */
pub const IXGBE_RXDADV_STAT_EOP: u32 = IXGBE_RXD_STAT_EOP; /* End of Packet */
pub const IXGBE_ADVTXD_PAYLEN_SHIFT: u32 = 14; /* Adv desc PAYLEN shift */
pub const IXGBE_TXD_CMD_EOP: u32 = 0x01000000; /* End of Packet */
pub const IXGBE_ADVTXD_DCMD_EOP: u32 = IXGBE_TXD_CMD_EOP; /* End of Packet */
pub const IXGBE_TXD_CMD_RS: u32 = 0x08000000; /* Report Status */
pub const IXGBE_ADVTXD_DCMD_RS: u32 = IXGBE_TXD_CMD_RS; /* Report Status */
pub const IXGBE_TXD_CMD_IFCS: u32 = 0x02000000; /* Insert FCS (Ethernet CRC) */
pub const IXGBE_ADVTXD_DCMD_IFCS: u32 = IXGBE_TXD_CMD_IFCS; /* Insert FCS */
pub const IXGBE_TXD_CMD_DEXT: u32 = 0x20000000; /* Desc extension (0 = legacy) */
pub const IXGBE_ADVTXD_DTYP_DATA: u32 = 0x00300000; /* Adv Data Descriptor */
pub const IXGBE_ADVTXD_DCMD_DEXT: u32 = IXGBE_TXD_CMD_DEXT; /* Desc ext 1=Adv */
pub const IXGBE_TXD_STAT_DD: u32 = 0x00000001; /* Descriptor Done */
pub const IXGBE_ADVTXD_STAT_DD: u32 = IXGBE_TXD_STAT_DD; /* Descriptor Done */
/* Interrupt Registers */
pub const IXGBE_EICR: u32 = 0x00800;
pub const IXGBE_EIAC: u32 = 0x00810;
pub const IXGBE_EIMS: u32 = 0x00880;
pub const IXGBE_IVAR_ALLOC_VAL: u32 = 0x80; /* Interrupt Allocation valid */
pub const IXGBE_EICR_RTX_QUEUE: u32 = 0x0000FFFF; /* RTx Queue Interrupt */
pub fn IXGBE_IVAR(i: u32) -> u32 {
0x00900 + (i * 4)
} /* 24 at 0x900-0x960 */
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_read {
pub pkt_addr: u64,
/* Packet buffer address */
pub hdr_addr: u64,
/* Header buffer address */
}
/* Receive Descriptor - Advanced */
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss {
pub pkt_info: u16,
/* RSS, Pkt type */
pub hdr_info: u16,
/* Splithdr, hdrlen */
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub union ixgbe_adv_rx_desc_wb_lower_lo_dword {
pub data: u32,
pub hs_rss: ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss,
}
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip {
pub ip_id: u16,
/* IP id */
pub csum: u16,
/* Packet Checksum */
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub union ixgbe_adv_rx_desc_wb_lower_hi_dword {
pub rss: u32,
/* RSS Hash */
pub csum_ip: ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip,
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_wb_lower {
pub lo_dword: ixgbe_adv_rx_desc_wb_lower_lo_dword,
pub hi_dword: ixgbe_adv_rx_desc_wb_lower_hi_dword,
}
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_wb_upper {
pub status_error: u32,
/* ext status/error */
pub length: u16,
/* Packet length */
pub vlan: u16,
/* VLAN tag */
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_rx_desc_wb {
pub lower: ixgbe_adv_rx_desc_wb_lower,
pub upper: ixgbe_adv_rx_desc_wb_upper,
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub union ixgbe_adv_rx_desc {
pub read: ixgbe_adv_rx_desc_read,
pub wb: ixgbe_adv_rx_desc_wb, /* writeback */
_union_align: [u64; 2],
}
/* Transmit Descriptor - Advanced */
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_tx_desc_read {
pub buffer_addr: u64,
/* Address of descriptor's data buf */
pub cmd_type_len: u32,
pub olinfo_status: u32,
}
#[derive(Debug, Copy, Clone)]
#[repr(C, packed)]
pub struct ixgbe_adv_tx_desc_wb {
pub rsvd: u64,
/* Reserved */
pub nxtseq_seed: u32,
pub status: u32,
}
#[derive(Copy, Clone)]
#[repr(C, packed)]
pub union ixgbe_adv_tx_desc {
pub read: ixgbe_adv_tx_desc_read,
pub wb: ixgbe_adv_tx_desc_wb,
_union_align: [u64; 2],
}
recipes/core/base/drivers/net/ixgbed/src/main.rs
+88
View File
@@ -0,0 +1,88 @@
use std::io::{Read, Write};
use std::os::unix::io::AsRawFd;
use driver_network::NetworkScheme;
use event::{user_data, EventQueue};
use pcid_interface::PciFunctionHandle;
pub mod device;
#[rustfmt::skip]
mod ixgbe;
fn main() {
pcid_interface::pci_daemon(daemon);
}
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
let pci_config = pcid_handle.config();
let mut name = pci_config.func.name();
name.push_str("_ixgbe");
let irq = pci_config
.func
.legacy_interrupt_line
.expect("ixgbed: no legacy interrupts supported");
println!(" + IXGBE {}", pci_config.func.display());
let mut irq_file = irq.irq_handle("ixgbed");
let mapped_bar = unsafe { pcid_handle.map_bar(0) };
let address = mapped_bar.ptr.as_ptr();
let size = mapped_bar.bar_size;
let mut scheme = NetworkScheme::new(
move || {
device::Intel8259x::new(address as usize, size)
.expect("ixgbed: failed to allocate device")
},
daemon,
format!("network.{name}"),
);
user_data! {
enum Source {
Irq,
Scheme,
}
}
let event_queue = EventQueue::<Source>::new().expect("ixgbed: Could not create event queue.");
event_queue
.subscribe(
irq_file.as_raw_fd() as usize,
Source::Irq,
event::EventFlags::READ,
)
.unwrap();
event_queue
.subscribe(
scheme.event_handle().raw(),
Source::Scheme,
event::EventFlags::READ,
)
.unwrap();
libredox::call::setrens(0, 0).expect("ixgbed: failed to enter null namespace");
scheme.tick().unwrap();
for event in event_queue.map(|e| e.expect("ixgbed: failed to get next event")) {
match event.user_data {
Source::Irq => {
let mut irq = [0; 8];
irq_file.read(&mut irq).unwrap();
if scheme.adapter().irq() {
irq_file.write(&mut irq).unwrap();
scheme.tick().unwrap();
}
}
Source::Scheme => {
scheme.tick().unwrap();
}
}
}
unreachable!()
}