milestone: desktop path Phases 1-5
Phase 1 (Runtime Substrate): 4 check binaries, --probe, POSIX tests Phase 2 (Wayland Compositor): bounded scaffold, zero warnings Phase 3 (KWin Session): preflight checker (KWin stub, gated on Qt6Quick) Phase 4 (KDE Plasma): 18 KF6 enabled, preflight checker Phase 5 (Hardware GPU): DRM/firmware/Mesa preflight checker Build: zero warnings, all scripts syntax-clean. Oracle-verified.
This commit is contained in:
@@ -0,0 +1,15 @@
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[package]
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name = "driver-network"
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description = "Shared networking code library"
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version = "0.1.0"
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edition = "2021"
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[dependencies]
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libredox.workspace = true
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daemon = { path = "../../../daemon" }
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redox-scheme.workspace = true
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scheme-utils = { path = "../../../scheme-utils" }
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redox_syscall = { workspace = true, features = ["std"] }
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[lints]
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workspace = true
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@@ -0,0 +1,354 @@
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use std::{cmp, io};
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use libredox::flag::O_NONBLOCK;
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use libredox::Fd;
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use redox_scheme::{
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scheme::{IntoTag, Op, SchemeResponse, SchemeState, SchemeSync},
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CallerCtx, OpenResult, RequestKind, Response, SignalBehavior, Socket,
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};
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use scheme_utils::{FpathWriter, HandleMap};
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use syscall::schemev2::NewFdFlags;
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use syscall::{
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Error, EventFlags, Result, Stat, EACCES, EAGAIN, EBADF, EINTR, EINVAL, EWOULDBLOCK, MODE_FILE,
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};
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pub trait NetworkAdapter {
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/// The [MAC address](https://en.wikipedia.org/wiki/MAC_address) of this
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/// network adapter.
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fn mac_address(&mut self) -> [u8; 6];
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/// The amount of network packets that can be read without blocking.
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fn available_for_read(&mut self) -> usize;
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/// Attempt to read a network packet without blocking.
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///
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/// Returns `Ok(None)` when there is no pending network packet.
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fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>>;
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/// Write a single network packet.
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// FIXME support back pressure on writes by returning EWOULDBLOCK or not
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// returning from the write syscall until there is room.
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fn write_packet(&mut self, buf: &[u8]) -> Result<usize>;
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}
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pub struct NetworkScheme<T: NetworkAdapter> {
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scheme: NetworkSchemeInner<T>,
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state: SchemeState,
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blocked: Vec<(Op, CallerCtx)>,
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socket: Socket,
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}
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fn post_fevent(socket: &Socket, id: usize, flags: usize) -> Result<()> {
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let fevent_response = Response::post_fevent(id, flags);
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match socket.write_response(fevent_response, SignalBehavior::Restart) {
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Ok(true) => Ok(()), // Write response success
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Ok(false) => Err(Error::new(syscall::EAGAIN)), // Write response failed, retry.
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Err(err) => Err(err), // Error writing response
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}
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}
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impl<T: NetworkAdapter> NetworkScheme<T> {
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pub fn new(
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adapter_fn: impl FnOnce() -> T,
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daemon: daemon::Daemon,
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scheme_name: String,
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) -> Self {
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assert!(scheme_name.starts_with("network"));
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let socket = Socket::nonblock().expect("failed to create network scheme");
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let adapter = adapter_fn();
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let mut scheme = NetworkSchemeInner::new(adapter, scheme_name.clone());
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redox_scheme::scheme::register_sync_scheme(&socket, &scheme_name, &mut scheme)
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.expect("failed to regitster network scheme");
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daemon.ready();
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Self {
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scheme,
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state: SchemeState::new(),
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blocked: Vec::new(),
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socket,
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}
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}
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pub fn event_handle(&self) -> &Fd {
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self.socket.inner()
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}
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pub fn adapter(&self) -> &T {
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&self.scheme.adapter
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}
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pub fn adapter_mut(&mut self) -> &mut T {
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&mut self.scheme.adapter
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}
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/// Process pending and new requests.
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///
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/// This needs to be called each time there is a new event on the scheme
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/// file and each time a new network packet has been received by the
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/// driver.
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// FIXME maybe split into one method for events on the scheme fd and one
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// to call when an irq is received to indicate that blocked requests can
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// be processed.
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pub fn tick(&mut self) -> io::Result<()> {
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// Handle any blocked requests
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let mut i = 0;
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while i < self.blocked.len() {
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let (op, caller) = &mut self.blocked[i];
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let res = op.handle_sync_dont_consume(caller, &mut self.scheme, &mut self.state);
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match res {
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SchemeResponse::Opened(Err(Error {
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errno: syscall::EWOULDBLOCK,
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}))
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| SchemeResponse::Regular(Err(Error {
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errno: syscall::EWOULDBLOCK,
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})) if !op.is_explicitly_nonblock() => {
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i += 1;
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}
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SchemeResponse::Regular(r) => {
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let (op, _) = self.blocked.remove(i);
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let _ = self
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.socket
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.write_response(Response::new(r, op), SignalBehavior::Restart)
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.expect("driver-network: failed to write scheme");
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}
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SchemeResponse::Opened(o) => {
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let (op, _) = self.blocked.remove(i);
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let _ = self
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.socket
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.write_response(Response::open_dup_like(o, op), SignalBehavior::Restart)
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.expect("driver-network: failed to write scheme");
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}
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SchemeResponse::RegularAndNotifyOnDetach(status) => {
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let (op, _) = self.blocked.remove(i);
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let _ = self
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.socket
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.write_response(
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Response::new_notify_on_detach(status, op),
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SignalBehavior::Restart,
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)
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.expect("driver-network: failed to write scheme");
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}
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}
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}
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// Handle new scheme requests
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loop {
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let request = match self.socket.next_request(SignalBehavior::Restart) {
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Ok(Some(request)) => request,
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Ok(None) => {
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// Scheme likely got unmounted
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std::process::exit(0);
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}
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Err(err) if err.errno == EAGAIN => break,
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Err(err) => return Err(err.into()),
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};
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let req = match request.kind() {
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RequestKind::Call(c) => c,
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RequestKind::OnClose { id } => {
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self.scheme.on_close(id);
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continue;
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}
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RequestKind::Cancellation(req) => {
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if let Some(i) = self.blocked.iter().position(|q| q.0.req_id() == req.id) {
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let (blocked_req, _) = self.blocked.remove(i);
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let resp = Response::new(Err(Error::new(EINTR)), blocked_req);
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self.socket.write_response(resp, SignalBehavior::Restart)?;
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}
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continue;
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}
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_ => {
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continue;
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}
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};
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let caller = req.caller();
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let mut op = match req.op() {
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Ok(op) => op,
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Err(req) => {
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self.socket.write_response(
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Response::err(syscall::EOPNOTSUPP, req),
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SignalBehavior::Restart,
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)?;
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continue;
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}
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};
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let resp = match op.handle_sync_dont_consume(&caller, &mut self.scheme, &mut self.state)
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{
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SchemeResponse::Opened(Err(Error {
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errno: syscall::EWOULDBLOCK,
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}))
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| SchemeResponse::Regular(Err(Error {
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errno: syscall::EWOULDBLOCK,
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})) if !op.is_explicitly_nonblock() => {
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self.blocked.push((op, caller));
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continue;
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}
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SchemeResponse::Regular(r) => Response::new(r, op),
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SchemeResponse::Opened(o) => Response::open_dup_like(o, op),
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SchemeResponse::RegularAndNotifyOnDetach(status) => {
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Response::new_notify_on_detach(status, op)
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}
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};
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let _ = self.socket.write_response(resp, SignalBehavior::Restart)?;
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}
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// Notify readers about incoming events
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let available_for_read = self.scheme.adapter.available_for_read();
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if available_for_read > 0 {
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for &handle_id in self.scheme.handles.keys() {
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post_fevent(&self.socket, handle_id, syscall::flag::EVENT_READ.bits())?;
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}
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return Ok(());
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}
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Ok(())
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}
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}
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struct NetworkSchemeInner<T: NetworkAdapter> {
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adapter: T,
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scheme_name: String,
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handles: HandleMap<Handle>,
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}
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enum Handle {
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Data,
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Mac,
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SchemeRoot,
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}
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impl<T: NetworkAdapter> NetworkSchemeInner<T> {
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pub fn new(adapter: T, scheme_name: String) -> Self {
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Self {
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adapter,
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scheme_name,
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handles: HandleMap::new(),
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}
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}
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}
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impl<T: NetworkAdapter> SchemeSync for NetworkSchemeInner<T> {
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fn scheme_root(&mut self) -> Result<usize> {
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Ok(self.handles.insert(Handle::SchemeRoot))
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}
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fn openat(
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&mut self,
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fd: usize,
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path: &str,
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_flags: usize,
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_fcntl_flags: u32,
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ctx: &CallerCtx,
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) -> Result<OpenResult> {
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if !matches!(self.handles.get(fd)?, Handle::SchemeRoot) {
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return Err(Error::new(EACCES));
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}
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if ctx.uid != 0 {
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return Err(Error::new(EACCES));
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}
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let (handle, flags) = match path {
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"" => (Handle::Data, NewFdFlags::empty()),
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"mac" => (Handle::Mac, NewFdFlags::POSITIONED),
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_ => return Err(Error::new(EINVAL)),
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};
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let id = self.handles.insert(handle);
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Ok(OpenResult::ThisScheme { number: id, flags })
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}
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fn read(
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&mut self,
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id: usize,
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buf: &mut [u8],
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offset: u64,
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fcntl_flags: u32,
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_ctx: &CallerCtx,
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) -> Result<usize> {
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let handle = self.handles.get_mut(id)?;
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match *handle {
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Handle::Data => {}
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Handle::Mac => {
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let data = &self.adapter.mac_address()[offset as usize..];
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let i = cmp::min(buf.len(), data.len());
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buf[..i].copy_from_slice(&data[..i]);
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return Ok(i);
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}
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_ => return Err(Error::new(EBADF)),
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};
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match self.adapter.read_packet(buf)? {
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Some(count) => Ok(count),
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None => {
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if fcntl_flags & O_NONBLOCK as u32 != 0 {
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Err(Error::new(EAGAIN))
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} else {
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Err(Error::new(EWOULDBLOCK))
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}
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}
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}
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}
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fn write(
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&mut self,
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id: usize,
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buf: &[u8],
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_offset: u64,
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_fcntl_flags: u32,
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_ctx: &CallerCtx,
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) -> Result<usize> {
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let handle = self.handles.get(id)?;
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match handle {
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Handle::Data => {}
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Handle::Mac { .. } => return Err(Error::new(EINVAL)),
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_ => return Err(Error::new(EBADF)),
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}
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Ok(self.adapter.write_packet(buf)?)
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}
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fn fevent(&mut self, id: usize, _flags: EventFlags, _ctx: &CallerCtx) -> Result<EventFlags> {
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let _handle = self.handles.get(id)?;
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Ok(EventFlags::empty())
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}
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|
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fn fpath(&mut self, id: usize, buf: &mut [u8], _ctx: &CallerCtx) -> Result<usize> {
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FpathWriter::with(buf, &self.scheme_name, |w| {
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let path = match self.handles.get(id)? {
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Handle::Data { .. } => "",
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Handle::Mac { .. } => "mac",
|
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_ => "",
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||||
};
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write!(w, "{path}").unwrap();
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Ok(())
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})
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}
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|
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fn fstat(&mut self, id: usize, stat: &mut Stat, _ctx: &CallerCtx) -> Result<()> {
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let handle = self.handles.get(id)?;
|
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|
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match handle {
|
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Handle::Data { .. } => {
|
||||
stat.st_mode = MODE_FILE | 0o700;
|
||||
}
|
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Handle::Mac { .. } => {
|
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stat.st_mode = MODE_FILE | 0o400;
|
||||
stat.st_size = 6;
|
||||
}
|
||||
_ => return Err(Error::new(EBADF)),
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn fsync(&mut self, id: usize, _ctx: &CallerCtx) -> Result<()> {
|
||||
let _handle = self.handles.get(id)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn on_close(&mut self, id: usize) {
|
||||
self.handles.remove(id);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
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[package]
|
||||
name = "e1000d"
|
||||
description = "Intel Gigabit ethernet driver"
|
||||
version = "0.1.0"
|
||||
edition = "2018"
|
||||
|
||||
[dependencies]
|
||||
bitflags.workspace = true
|
||||
log.workspace = true
|
||||
libredox.workspace = true
|
||||
redox_event.workspace = true
|
||||
redox_syscall.workspace = true
|
||||
|
||||
common = { path = "../../common" }
|
||||
daemon = { path = "../../../daemon" }
|
||||
driver-network = { path = "../driver-network" }
|
||||
pcid = { path = "../../pcid" }
|
||||
|
||||
[lints]
|
||||
workspace = true
|
||||
@@ -0,0 +1,5 @@
|
||||
[[drivers]]
|
||||
name = "E1000 NIC"
|
||||
class = 0x02
|
||||
ids = { 0x8086 = [0x1004, 0x100e, 0x100f, 0x109a, 0x1503] }
|
||||
command = ["e1000d"]
|
||||
@@ -0,0 +1,368 @@
|
||||
use std::convert::TryInto;
|
||||
use std::{cmp, mem, ptr, slice, thread, time};
|
||||
|
||||
use driver_network::NetworkAdapter;
|
||||
|
||||
use syscall::error::Result;
|
||||
|
||||
use common::dma::Dma;
|
||||
|
||||
const CTRL: u32 = 0x00;
|
||||
const CTRL_LRST: u32 = 1 << 3;
|
||||
const CTRL_ASDE: u32 = 1 << 5;
|
||||
const CTRL_SLU: u32 = 1 << 6;
|
||||
const CTRL_ILOS: u32 = 1 << 7;
|
||||
const CTRL_RST: u32 = 1 << 26;
|
||||
const CTRL_VME: u32 = 1 << 30;
|
||||
const CTRL_PHY_RST: u32 = 1 << 31;
|
||||
|
||||
const STATUS: u32 = 0x08;
|
||||
|
||||
const FCAL: u32 = 0x28;
|
||||
const FCAH: u32 = 0x2C;
|
||||
const FCT: u32 = 0x30;
|
||||
const FCTTV: u32 = 0x170;
|
||||
|
||||
const ICR: u32 = 0xC0;
|
||||
|
||||
const IMS: u32 = 0xD0;
|
||||
const IMS_TXDW: u32 = 1;
|
||||
const IMS_TXQE: u32 = 1 << 1;
|
||||
const IMS_LSC: u32 = 1 << 2;
|
||||
const IMS_RXSEQ: u32 = 1 << 3;
|
||||
const IMS_RXDMT: u32 = 1 << 4;
|
||||
const IMS_RX: u32 = 1 << 6;
|
||||
const IMS_RXT: u32 = 1 << 7;
|
||||
|
||||
const RCTL: u32 = 0x100;
|
||||
const RCTL_EN: u32 = 1 << 1;
|
||||
const RCTL_UPE: u32 = 1 << 3;
|
||||
const RCTL_MPE: u32 = 1 << 4;
|
||||
const RCTL_LPE: u32 = 1 << 5;
|
||||
const RCTL_LBM: u32 = 1 << 6 | 1 << 7;
|
||||
const RCTL_BAM: u32 = 1 << 15;
|
||||
const RCTL_BSIZE1: u32 = 1 << 16;
|
||||
const RCTL_BSIZE2: u32 = 1 << 17;
|
||||
const RCTL_BSEX: u32 = 1 << 25;
|
||||
const RCTL_SECRC: u32 = 1 << 26;
|
||||
|
||||
const RDBAL: u32 = 0x2800;
|
||||
const RDBAH: u32 = 0x2804;
|
||||
const RDLEN: u32 = 0x2808;
|
||||
const RDH: u32 = 0x2810;
|
||||
const RDT: u32 = 0x2818;
|
||||
|
||||
const RAL0: u32 = 0x5400;
|
||||
const RAH0: u32 = 0x5404;
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
struct Rd {
|
||||
buffer: u64,
|
||||
length: u16,
|
||||
checksum: u16,
|
||||
status: u8,
|
||||
error: u8,
|
||||
special: u16,
|
||||
}
|
||||
const RD_DD: u8 = 1;
|
||||
const RD_EOP: u8 = 1 << 1;
|
||||
|
||||
const TCTL: u32 = 0x400;
|
||||
const TCTL_EN: u32 = 1 << 1;
|
||||
const TCTL_PSP: u32 = 1 << 3;
|
||||
|
||||
const TDBAL: u32 = 0x3800;
|
||||
const TDBAH: u32 = 0x3804;
|
||||
const TDLEN: u32 = 0x3808;
|
||||
const TDH: u32 = 0x3810;
|
||||
const TDT: u32 = 0x3818;
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
struct Td {
|
||||
buffer: u64,
|
||||
length: u16,
|
||||
cso: u8,
|
||||
command: u8,
|
||||
status: u8,
|
||||
css: u8,
|
||||
special: u16,
|
||||
}
|
||||
const TD_CMD_EOP: u8 = 1;
|
||||
const TD_CMD_IFCS: u8 = 1 << 1;
|
||||
const TD_CMD_RS: u8 = 1 << 3;
|
||||
const TD_DD: u8 = 1;
|
||||
|
||||
pub struct Intel8254x {
|
||||
base: usize,
|
||||
mac_address: [u8; 6],
|
||||
receive_buffer: [Dma<[u8; 16384]>; 16],
|
||||
receive_ring: Dma<[Rd; 16]>,
|
||||
receive_index: usize,
|
||||
transmit_buffer: [Dma<[u8; 16384]>; 16],
|
||||
transmit_ring: Dma<[Td; 16]>,
|
||||
transmit_ring_free: usize,
|
||||
transmit_index: usize,
|
||||
transmit_clean_index: usize,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum Handle {
|
||||
Data { flags: usize },
|
||||
Mac { offset: usize },
|
||||
}
|
||||
|
||||
fn wrap_ring(index: usize, ring_size: usize) -> usize {
|
||||
(index + 1) & (ring_size - 1)
|
||||
}
|
||||
|
||||
impl NetworkAdapter for Intel8254x {
|
||||
fn mac_address(&mut self) -> [u8; 6] {
|
||||
self.mac_address
|
||||
}
|
||||
|
||||
fn available_for_read(&mut self) -> usize {
|
||||
let desc = unsafe { &*(self.receive_ring.as_ptr().add(self.receive_index) as *const Rd) };
|
||||
|
||||
if desc.status & RD_DD == RD_DD {
|
||||
return desc.length as usize;
|
||||
}
|
||||
|
||||
0
|
||||
}
|
||||
|
||||
fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
|
||||
let desc = unsafe { &mut *(self.receive_ring.as_ptr().add(self.receive_index) as *mut Rd) };
|
||||
|
||||
if desc.status & RD_DD == RD_DD {
|
||||
desc.status = 0;
|
||||
|
||||
let data = &self.receive_buffer[self.receive_index][..desc.length as usize];
|
||||
|
||||
let i = cmp::min(buf.len(), data.len());
|
||||
buf[..i].copy_from_slice(&data[..i]);
|
||||
|
||||
unsafe { self.write_reg(RDT, self.receive_index as u32) };
|
||||
self.receive_index = wrap_ring(self.receive_index, self.receive_ring.len());
|
||||
|
||||
return Ok(Some(i));
|
||||
}
|
||||
|
||||
Ok(None)
|
||||
}
|
||||
|
||||
fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
|
||||
if self.transmit_ring_free == 0 {
|
||||
loop {
|
||||
let desc = unsafe {
|
||||
&*(self.transmit_ring.as_ptr().add(self.transmit_clean_index) as *const Td)
|
||||
};
|
||||
|
||||
if desc.status != 0 {
|
||||
self.transmit_clean_index =
|
||||
wrap_ring(self.transmit_clean_index, self.transmit_ring.len());
|
||||
self.transmit_ring_free += 1;
|
||||
} else if self.transmit_ring_free > 0 {
|
||||
break;
|
||||
}
|
||||
|
||||
if self.transmit_ring_free >= self.transmit_ring.len() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let desc =
|
||||
unsafe { &mut *(self.transmit_ring.as_ptr().add(self.transmit_index) as *mut Td) };
|
||||
|
||||
let data = unsafe {
|
||||
slice::from_raw_parts_mut(
|
||||
self.transmit_buffer[self.transmit_index].as_ptr() as *mut u8,
|
||||
cmp::min(buf.len(), self.transmit_buffer[self.transmit_index].len()) as usize,
|
||||
)
|
||||
};
|
||||
|
||||
let i = cmp::min(buf.len(), data.len());
|
||||
data[..i].copy_from_slice(&buf[..i]);
|
||||
|
||||
desc.cso = 0;
|
||||
desc.command = TD_CMD_EOP | TD_CMD_IFCS | TD_CMD_RS;
|
||||
desc.status = 0;
|
||||
desc.css = 0;
|
||||
desc.special = 0;
|
||||
|
||||
desc.length = (cmp::min(
|
||||
buf.len(),
|
||||
self.transmit_buffer[self.transmit_index].len() - 1,
|
||||
)) as u16;
|
||||
|
||||
self.transmit_index = wrap_ring(self.transmit_index, self.transmit_ring.len());
|
||||
self.transmit_ring_free -= 1;
|
||||
|
||||
unsafe { self.write_reg(TDT, self.transmit_index as u32) };
|
||||
|
||||
Ok(i)
|
||||
}
|
||||
}
|
||||
|
||||
fn dma_array<T, const N: usize>() -> Result<[Dma<T>; N]> {
|
||||
Ok((0..N)
|
||||
.map(|_| Ok(unsafe { Dma::zeroed()?.assume_init() }))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()))
|
||||
}
|
||||
impl Intel8254x {
|
||||
pub unsafe fn new(base: usize) -> Result<Self> {
|
||||
#[rustfmt::skip]
|
||||
let mut module = Intel8254x {
|
||||
base,
|
||||
mac_address: [0; 6],
|
||||
receive_buffer: dma_array()?,
|
||||
receive_ring: Dma::zeroed()?.assume_init(),
|
||||
transmit_buffer: dma_array()?,
|
||||
receive_index: 0,
|
||||
transmit_ring: Dma::zeroed()?.assume_init(),
|
||||
transmit_ring_free: 16,
|
||||
transmit_index: 0,
|
||||
transmit_clean_index: 0,
|
||||
};
|
||||
|
||||
module.init();
|
||||
|
||||
Ok(module)
|
||||
}
|
||||
|
||||
pub unsafe fn irq(&self) -> bool {
|
||||
let icr = self.read_reg(ICR);
|
||||
icr != 0
|
||||
}
|
||||
|
||||
pub unsafe fn read_reg(&self, register: u32) -> u32 {
|
||||
ptr::read_volatile((self.base + register as usize) as *mut u32)
|
||||
}
|
||||
|
||||
pub unsafe fn write_reg(&self, register: u32, data: u32) -> u32 {
|
||||
ptr::write_volatile((self.base + register as usize) as *mut u32, data);
|
||||
ptr::read_volatile((self.base + register as usize) as *mut u32)
|
||||
}
|
||||
|
||||
pub unsafe fn flag(&self, register: u32, flag: u32, value: bool) {
|
||||
if value {
|
||||
self.write_reg(register, self.read_reg(register) | flag);
|
||||
} else {
|
||||
self.write_reg(register, self.read_reg(register) & !flag);
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(&mut self) {
|
||||
self.flag(CTRL, CTRL_RST, true);
|
||||
while self.read_reg(CTRL) & CTRL_RST == CTRL_RST {
|
||||
log::trace!("Waiting for reset: {:X}", self.read_reg(CTRL));
|
||||
}
|
||||
|
||||
// Enable auto negotiate, link, clear reset, do not Invert Loss-Of Signal
|
||||
self.flag(CTRL, CTRL_ASDE | CTRL_SLU, true);
|
||||
self.flag(CTRL, CTRL_LRST | CTRL_PHY_RST | CTRL_ILOS, false);
|
||||
|
||||
// No flow control
|
||||
self.write_reg(FCAH, 0);
|
||||
self.write_reg(FCAL, 0);
|
||||
self.write_reg(FCT, 0);
|
||||
self.write_reg(FCTTV, 0);
|
||||
|
||||
// Do not use VLANs
|
||||
self.flag(CTRL, CTRL_VME, false);
|
||||
|
||||
// TODO: Clear statistical counters
|
||||
|
||||
let mac_low = self.read_reg(RAL0);
|
||||
let mac_high = self.read_reg(RAH0);
|
||||
let mac = [
|
||||
mac_low as u8,
|
||||
(mac_low >> 8) as u8,
|
||||
(mac_low >> 16) as u8,
|
||||
(mac_low >> 24) as u8,
|
||||
mac_high as u8,
|
||||
(mac_high >> 8) as u8,
|
||||
];
|
||||
log::debug!(
|
||||
"MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
|
||||
mac[0],
|
||||
mac[1],
|
||||
mac[2],
|
||||
mac[3],
|
||||
mac[4],
|
||||
mac[5]
|
||||
);
|
||||
self.mac_address = mac;
|
||||
|
||||
//
|
||||
// MTA => 0;
|
||||
//
|
||||
|
||||
// Receive Buffer
|
||||
for i in 0..self.receive_ring.len() {
|
||||
self.receive_ring[i].buffer = self.receive_buffer[i].physical() as u64;
|
||||
}
|
||||
|
||||
self.write_reg(RDBAH, ((self.receive_ring.physical() as u64) >> 32) as u32);
|
||||
self.write_reg(RDBAL, self.receive_ring.physical() as u32);
|
||||
self.write_reg(
|
||||
RDLEN,
|
||||
(self.receive_ring.len() * mem::size_of::<Rd>()) as u32,
|
||||
);
|
||||
self.write_reg(RDH, 0);
|
||||
self.write_reg(RDT, self.receive_ring.len() as u32 - 1);
|
||||
|
||||
// Transmit Buffer
|
||||
for i in 0..self.transmit_ring.len() {
|
||||
self.transmit_ring[i].buffer = self.transmit_buffer[i].physical() as u64;
|
||||
}
|
||||
|
||||
self.write_reg(TDBAH, ((self.transmit_ring.physical() as u64) >> 32) as u32);
|
||||
self.write_reg(TDBAL, self.transmit_ring.physical() as u32);
|
||||
self.write_reg(
|
||||
TDLEN,
|
||||
(self.transmit_ring.len() * mem::size_of::<Td>()) as u32,
|
||||
);
|
||||
self.write_reg(TDH, 0);
|
||||
self.write_reg(TDT, 0);
|
||||
|
||||
self.write_reg(IMS, IMS_RXT | IMS_RX | IMS_RXDMT | IMS_RXSEQ); // | IMS_LSC | IMS_TXQE | IMS_TXDW
|
||||
|
||||
self.flag(RCTL, RCTL_EN, true);
|
||||
self.flag(RCTL, RCTL_UPE, true);
|
||||
// self.flag(RCTL, RCTL_MPE, true);
|
||||
self.flag(RCTL, RCTL_LPE, true);
|
||||
self.flag(RCTL, RCTL_LBM, false);
|
||||
// RCTL.RDMTS = Minimum threshold size ???
|
||||
// RCTL.MO = Multicast offset
|
||||
self.flag(RCTL, RCTL_BAM, true);
|
||||
self.flag(RCTL, RCTL_BSIZE1, true);
|
||||
self.flag(RCTL, RCTL_BSIZE2, false);
|
||||
self.flag(RCTL, RCTL_BSEX, true);
|
||||
self.flag(RCTL, RCTL_SECRC, true);
|
||||
|
||||
self.flag(TCTL, TCTL_EN, true);
|
||||
self.flag(TCTL, TCTL_PSP, true);
|
||||
// TCTL.CT = Collision threshold
|
||||
// TCTL.COLD = Collision distance
|
||||
// TIPG Packet Gap
|
||||
// TODO ...
|
||||
|
||||
log::debug!("Waiting for link up: {:X}", self.read_reg(STATUS));
|
||||
while self.read_reg(STATUS) & 2 != 2 {
|
||||
thread::sleep(time::Duration::from_millis(100));
|
||||
}
|
||||
log::debug!(
|
||||
"Link is up with speed {}",
|
||||
match (self.read_reg(STATUS) >> 6) & 0b11 {
|
||||
0b00 => "10 Mb/s",
|
||||
0b01 => "100 Mb/s",
|
||||
_ => "1000 Mb/s",
|
||||
}
|
||||
);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,90 @@
|
||||
use std::io::{Read, Write};
|
||||
use std::os::unix::io::AsRawFd;
|
||||
|
||||
use driver_network::NetworkScheme;
|
||||
use event::{user_data, EventQueue};
|
||||
use pcid_interface::PciFunctionHandle;
|
||||
|
||||
pub mod device;
|
||||
|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon);
|
||||
}
|
||||
|
||||
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
|
||||
let pci_config = pcid_handle.config();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_e1000");
|
||||
|
||||
common::setup_logging(
|
||||
"net",
|
||||
"pci",
|
||||
&name,
|
||||
common::output_level(),
|
||||
common::file_level(),
|
||||
);
|
||||
|
||||
let irq = pci_config
|
||||
.func
|
||||
.legacy_interrupt_line
|
||||
.expect("e1000d: no legacy interrupts supported");
|
||||
|
||||
log::info!("E1000 {}", pci_config.func.display());
|
||||
|
||||
let mut irq_file = irq.irq_handle("e1000d");
|
||||
|
||||
let address = unsafe { pcid_handle.map_bar(0) }.ptr.as_ptr() as usize;
|
||||
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || unsafe {
|
||||
device::Intel8254x::new(address).expect("e1000d: failed to allocate device")
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
user_data! {
|
||||
enum Source {
|
||||
Irq,
|
||||
Scheme,
|
||||
}
|
||||
}
|
||||
|
||||
let event_queue = EventQueue::<Source>::new().expect("e1000d: failed to create event queue");
|
||||
|
||||
event_queue
|
||||
.subscribe(
|
||||
irq_file.as_raw_fd() as usize,
|
||||
Source::Irq,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.expect("e1000d: failed to subscribe to IRQ fd");
|
||||
event_queue
|
||||
.subscribe(
|
||||
scheme.event_handle().raw(),
|
||||
Source::Scheme,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.expect("e1000d: failed to subscribe to scheme fd");
|
||||
|
||||
libredox::call::setrens(0, 0).expect("e1000d: failed to enter null namespace");
|
||||
|
||||
scheme.tick().unwrap();
|
||||
|
||||
for event in event_queue.map(|e| e.expect("e1000d: failed to get event")) {
|
||||
match event.user_data {
|
||||
Source::Irq => {
|
||||
let mut irq = [0; 8];
|
||||
irq_file.read(&mut irq).unwrap();
|
||||
if unsafe { scheme.adapter().irq() } {
|
||||
irq_file.write(&mut irq).unwrap();
|
||||
|
||||
scheme.tick().expect("e1000d: failed to handle IRQ")
|
||||
}
|
||||
}
|
||||
Source::Scheme => scheme.tick().expect("e1000d: failed to handle scheme op"),
|
||||
}
|
||||
}
|
||||
unreachable!()
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
[package]
|
||||
name = "ixgbed"
|
||||
description = "Intel 10 Gigabit ethernet driver"
|
||||
version = "1.0.0"
|
||||
edition = "2021"
|
||||
|
||||
[dependencies]
|
||||
bitflags.workspace = true
|
||||
libredox.workspace = true
|
||||
redox_event.workspace = true
|
||||
redox_syscall.workspace = true
|
||||
|
||||
common = { path = "../../common" }
|
||||
daemon = { path = "../../../daemon" }
|
||||
driver-network = { path = "../driver-network" }
|
||||
pcid = { path = "../../pcid" }
|
||||
|
||||
[lints]
|
||||
workspace = true
|
||||
@@ -0,0 +1,661 @@
|
||||
GNU AFFERO GENERAL PUBLIC LICENSE
|
||||
Version 3, 19 November 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU Affero General Public License is a free, copyleft license for
|
||||
software and other kinds of works, specifically designed to ensure
|
||||
cooperation with the community in the case of network server software.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
our General Public Licenses are intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
Developers that use our General Public Licenses protect your rights
|
||||
with two steps: (1) assert copyright on the software, and (2) offer
|
||||
you this License which gives you legal permission to copy, distribute
|
||||
and/or modify the software.
|
||||
|
||||
A secondary benefit of defending all users' freedom is that
|
||||
improvements made in alternate versions of the program, if they
|
||||
receive widespread use, become available for other developers to
|
||||
incorporate. Many developers of free software are heartened and
|
||||
encouraged by the resulting cooperation. However, in the case of
|
||||
software used on network servers, this result may fail to come about.
|
||||
The GNU General Public License permits making a modified version and
|
||||
letting the public access it on a server without ever releasing its
|
||||
source code to the public.
|
||||
|
||||
The GNU Affero General Public License is designed specifically to
|
||||
ensure that, in such cases, the modified source code becomes available
|
||||
to the community. It requires the operator of a network server to
|
||||
provide the source code of the modified version running there to the
|
||||
users of that server. Therefore, public use of a modified version, on
|
||||
a publicly accessible server, gives the public access to the source
|
||||
code of the modified version.
|
||||
|
||||
An older license, called the Affero General Public License and
|
||||
published by Affero, was designed to accomplish similar goals. This is
|
||||
a different license, not a version of the Affero GPL, but Affero has
|
||||
released a new version of the Affero GPL which permits relicensing under
|
||||
this license.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU Affero General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
License. Each licensee is addressed as "you". "Licensees" and
|
||||
"recipients" may be individuals or organizations.
|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
in a fashion requiring copyright permission, other than the making of an
|
||||
exact copy. The resulting work is called a "modified version" of the
|
||||
earlier work or a work "based on" the earlier work.
|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
feature that (1) displays an appropriate copyright notice, and (2)
|
||||
tells the user that there is no warranty for the work (except to the
|
||||
extent that warranties are provided), that licensees may convey the
|
||||
work under this License, and how to view a copy of this License. If
|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
programs which are used unmodified in performing those activities but
|
||||
which are not part of the work. For example, Corresponding Source
|
||||
includes interface definition files associated with source files for
|
||||
the work, and the source code for shared libraries and dynamically
|
||||
linked subprograms that the work is specifically designed to require,
|
||||
such as by intimate data communication or control flow between those
|
||||
subprograms and other parts of the work.
|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Remote Network Interaction; Use with the GNU General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, if you modify the
|
||||
Program, your modified version must prominently offer all users
|
||||
interacting with it remotely through a computer network (if your version
|
||||
supports such interaction) an opportunity to receive the Corresponding
|
||||
Source of your version by providing access to the Corresponding Source
|
||||
from a network server at no charge, through some standard or customary
|
||||
means of facilitating copying of software. This Corresponding Source
|
||||
shall include the Corresponding Source for any work covered by version 3
|
||||
of the GNU General Public License that is incorporated pursuant to the
|
||||
following paragraph.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the work with which it is combined will remain governed by version
|
||||
3 of the GNU General Public License.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU Affero General Public License from time to time. Such new versions
|
||||
will be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU Affero General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU Affero General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU Affero General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU Affero General Public License as published
|
||||
by the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU Affero General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Affero General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If your software can interact with users remotely through a computer
|
||||
network, you should also make sure that it provides a way for users to
|
||||
get its source. For example, if your program is a web application, its
|
||||
interface could display a "Source" link that leads users to an archive
|
||||
of the code. There are many ways you could offer source, and different
|
||||
solutions will be better for different programs; see section 13 for the
|
||||
specific requirements.
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU AGPL, see
|
||||
<https://www.gnu.org/licenses/>.
|
||||
@@ -0,0 +1,37 @@
|
||||
# ixgbed (a.k.a. ixy.rs on Redox)
|
||||
|
||||
ixgbed is the Redox port of [ixy.rs](https://github.com/ixy-languages/ixy.rs), a Rust rewrite of the [ixy](https://github.com/emmericp/ixy) userspace network driver.
|
||||
It is designed to be readable, idiomatic Rust code.
|
||||
It supports Intel 82599 10GbE NICs (`ixgbe` family).
|
||||
|
||||
## Features
|
||||
|
||||
* first 10 Gbit/s network driver on Redox
|
||||
* transmitting 250 times faster than e1000 / rtl8168 driver
|
||||
* MSI-X interrupts (not supported by Redox yet)
|
||||
* less than 1000 lines of code for the driver
|
||||
* documented code
|
||||
|
||||
## Build instructions
|
||||
|
||||
See the [Redox README](https://gitlab.redox-os.org/redox-os/redox/blob/master/README.md) for build instructions.
|
||||
|
||||
To run ixgbed on Redox (in case the driver is not shipped with Redox anymore)
|
||||
|
||||
* clone this project into `cookbook/recipes/drivers/source/`
|
||||
* create an entry for ixgbed in `cookbook/recipes/drivers/source/Cargo.toml`
|
||||
* check if your ixgbe device is included in `config.toml`
|
||||
* touch `filesystem.toml` in Redox's root directory, build Redox and run it
|
||||
|
||||
## Usage
|
||||
|
||||
To test the driver's transmit and forwarding capabilities, have a look at [rheinfall](https://github.com/ackxolotl/rheinfall), a simple packet generator / forwarder application.
|
||||
|
||||
## Docs
|
||||
|
||||
ixgbed contains documentation that can be created and viewed by running
|
||||
|
||||
```
|
||||
cargo doc --open
|
||||
```
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
[[drivers]]
|
||||
name = "Intel 10G NIC"
|
||||
class = 0x02
|
||||
ids = { 0x8086 = [0x10F7, 0x1514, 0x1517, 0x151C, 0x10F9, 0x10FB, 0x152a, 0x1529, 0x1507, 0x154D, 0x1557, 0x10FC, 0x10F8, 0x154F, 0x1528, 0x154A, 0x1558, 0x1560, 0x1563, 0x15D1, 0x15AA, 0x15AB, 0x15AC, 0x15AD, 0x15AE, 0x15B0, 0x15C2, 0x15C3, 0x15C4, 0x15C6, 0x15C7, 0x15C8, 0x15CE, 0x15E4, 0x15E5, 0x10ED, 0x1515, 0x1565, 0x15A8, 0x15C5] }
|
||||
command = ["ixgbed"]
|
||||
@@ -0,0 +1,579 @@
|
||||
use std::convert::TryInto;
|
||||
use std::time::{Duration, Instant};
|
||||
use std::{cmp, mem, ptr, slice, thread};
|
||||
|
||||
use driver_network::NetworkAdapter;
|
||||
use syscall::error::Result;
|
||||
|
||||
use common::dma::Dma;
|
||||
|
||||
use crate::ixgbe::*;
|
||||
|
||||
pub struct Intel8259x {
|
||||
base: usize,
|
||||
size: usize,
|
||||
receive_buffer: [Dma<[u8; 16384]>; 32],
|
||||
receive_ring: Dma<[ixgbe_adv_rx_desc; 32]>,
|
||||
receive_index: usize,
|
||||
transmit_buffer: [Dma<[u8; 16384]>; 32],
|
||||
transmit_ring: Dma<[ixgbe_adv_tx_desc; 32]>,
|
||||
transmit_ring_free: usize,
|
||||
transmit_index: usize,
|
||||
transmit_clean_index: usize,
|
||||
mac_address: [u8; 6],
|
||||
}
|
||||
|
||||
fn wrap_ring(index: usize, ring_size: usize) -> usize {
|
||||
(index + 1) & (ring_size - 1)
|
||||
}
|
||||
|
||||
impl NetworkAdapter for Intel8259x {
|
||||
fn mac_address(&mut self) -> [u8; 6] {
|
||||
self.mac_address
|
||||
}
|
||||
|
||||
fn available_for_read(&mut self) -> usize {
|
||||
self.next_read()
|
||||
}
|
||||
|
||||
fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
|
||||
let desc = unsafe {
|
||||
&mut *(self.receive_ring.as_ptr().add(self.receive_index) as *mut ixgbe_adv_rx_desc)
|
||||
};
|
||||
|
||||
let status = unsafe { desc.wb.upper.status_error };
|
||||
|
||||
if (status & IXGBE_RXDADV_STAT_DD) != 0 {
|
||||
if (status & IXGBE_RXDADV_STAT_EOP) == 0 {
|
||||
panic!("increase buffer size or decrease MTU")
|
||||
}
|
||||
|
||||
let data = unsafe {
|
||||
&self.receive_buffer[self.receive_index][..desc.wb.upper.length as usize]
|
||||
};
|
||||
|
||||
let i = cmp::min(buf.len(), data.len());
|
||||
buf[..i].copy_from_slice(&data[..i]);
|
||||
|
||||
desc.read.pkt_addr = self.receive_buffer[self.receive_index].physical() as u64;
|
||||
desc.read.hdr_addr = 0;
|
||||
|
||||
self.write_reg(IXGBE_RDT(0), self.receive_index as u32);
|
||||
self.receive_index = wrap_ring(self.receive_index, self.receive_ring.len());
|
||||
|
||||
return Ok(Some(i));
|
||||
}
|
||||
|
||||
Ok(None)
|
||||
}
|
||||
|
||||
fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
|
||||
if self.transmit_ring_free == 0 {
|
||||
loop {
|
||||
let desc = unsafe {
|
||||
&*(self.transmit_ring.as_ptr().add(self.transmit_clean_index)
|
||||
as *const ixgbe_adv_tx_desc)
|
||||
};
|
||||
|
||||
if (unsafe { desc.wb.status } & IXGBE_ADVTXD_STAT_DD) != 0 {
|
||||
self.transmit_clean_index =
|
||||
wrap_ring(self.transmit_clean_index, self.transmit_ring.len());
|
||||
self.transmit_ring_free += 1;
|
||||
} else if self.transmit_ring_free > 0 {
|
||||
break;
|
||||
}
|
||||
|
||||
if self.transmit_ring_free >= self.transmit_ring.len() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let desc = unsafe {
|
||||
&mut *(self.transmit_ring.as_ptr().add(self.transmit_index) as *mut ixgbe_adv_tx_desc)
|
||||
};
|
||||
|
||||
let data = unsafe {
|
||||
slice::from_raw_parts_mut(
|
||||
self.transmit_buffer[self.transmit_index].as_ptr() as *mut u8,
|
||||
cmp::min(buf.len(), self.transmit_buffer[self.transmit_index].len()) as usize,
|
||||
)
|
||||
};
|
||||
|
||||
let i = cmp::min(buf.len(), data.len());
|
||||
data[..i].copy_from_slice(&buf[..i]);
|
||||
|
||||
desc.read.cmd_type_len = IXGBE_ADVTXD_DCMD_EOP
|
||||
| IXGBE_ADVTXD_DCMD_RS
|
||||
| IXGBE_ADVTXD_DCMD_IFCS
|
||||
| IXGBE_ADVTXD_DCMD_DEXT
|
||||
| IXGBE_ADVTXD_DTYP_DATA
|
||||
| buf.len() as u32;
|
||||
|
||||
desc.read.olinfo_status = (buf.len() as u32) << IXGBE_ADVTXD_PAYLEN_SHIFT;
|
||||
|
||||
self.transmit_index = wrap_ring(self.transmit_index, self.transmit_ring.len());
|
||||
self.transmit_ring_free -= 1;
|
||||
|
||||
self.write_reg(IXGBE_TDT(0), self.transmit_index as u32);
|
||||
|
||||
Ok(i)
|
||||
}
|
||||
}
|
||||
|
||||
impl Intel8259x {
|
||||
/// Returns an initialized `Intel8259x` on success.
|
||||
pub fn new(base: usize, size: usize) -> Result<Self> {
|
||||
#[rustfmt::skip]
|
||||
let mut module = Intel8259x {
|
||||
base,
|
||||
size,
|
||||
receive_buffer: (0..32)
|
||||
.map(|_| Ok(unsafe { Dma::zeroed()?.assume_init() }))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()),
|
||||
receive_ring: unsafe { Dma::zeroed()?.assume_init() },
|
||||
transmit_buffer: (0..32)
|
||||
.map(|_| Ok(unsafe { Dma::zeroed()?.assume_init() }))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()),
|
||||
receive_index: 0,
|
||||
transmit_ring: unsafe { Dma::zeroed()?.assume_init() },
|
||||
transmit_ring_free: 32,
|
||||
transmit_index: 0,
|
||||
transmit_clean_index: 0,
|
||||
mac_address: [0; 6],
|
||||
};
|
||||
|
||||
module.init();
|
||||
|
||||
Ok(module)
|
||||
}
|
||||
|
||||
pub fn irq(&self) -> bool {
|
||||
let icr = self.read_reg(IXGBE_EICR);
|
||||
icr != 0
|
||||
}
|
||||
|
||||
pub fn next_read(&self) -> usize {
|
||||
let desc = unsafe {
|
||||
&*(self.receive_ring.as_ptr().add(self.receive_index) as *const ixgbe_adv_rx_desc)
|
||||
};
|
||||
|
||||
let status = unsafe { desc.wb.upper.status_error };
|
||||
|
||||
if (status & IXGBE_RXDADV_STAT_DD) != 0 {
|
||||
if (status & IXGBE_RXDADV_STAT_EOP) == 0 {
|
||||
panic!("increase buffer size or decrease MTU")
|
||||
}
|
||||
|
||||
return unsafe { desc.wb.upper.length as usize };
|
||||
}
|
||||
|
||||
0
|
||||
}
|
||||
|
||||
/// Returns the mac address of this device.
|
||||
pub fn get_mac_addr(&self) -> [u8; 6] {
|
||||
let low = self.read_reg(IXGBE_RAL(0));
|
||||
let high = self.read_reg(IXGBE_RAH(0));
|
||||
|
||||
[
|
||||
(low & 0xff) as u8,
|
||||
(low >> 8 & 0xff) as u8,
|
||||
(low >> 16 & 0xff) as u8,
|
||||
(low >> 24) as u8,
|
||||
(high & 0xff) as u8,
|
||||
(high >> 8 & 0xff) as u8,
|
||||
]
|
||||
}
|
||||
|
||||
/// Sets the mac address of this device.
|
||||
#[allow(dead_code)]
|
||||
pub fn set_mac_addr(&mut self, mac: [u8; 6]) {
|
||||
let low: u32 = u32::from(mac[0])
|
||||
+ (u32::from(mac[1]) << 8)
|
||||
+ (u32::from(mac[2]) << 16)
|
||||
+ (u32::from(mac[3]) << 24);
|
||||
let high: u32 = u32::from(mac[4]) + (u32::from(mac[5]) << 8);
|
||||
|
||||
self.write_reg(IXGBE_RAL(0), low);
|
||||
self.write_reg(IXGBE_RAH(0), high);
|
||||
|
||||
self.mac_address = mac;
|
||||
}
|
||||
|
||||
/// Returns the register at `self.base` + `register`.
|
||||
///
|
||||
/// # Panics
|
||||
///
|
||||
/// Panics if `self.base` + `register` does not belong to the mapped memory of the PCIe device.
|
||||
fn read_reg(&self, register: u32) -> u32 {
|
||||
assert!(
|
||||
register as usize <= self.size - 4 as usize,
|
||||
"MMIO access out of bounds"
|
||||
);
|
||||
|
||||
unsafe { ptr::read_volatile((self.base + register as usize) as *mut u32) }
|
||||
}
|
||||
|
||||
/// Sets the register at `self.base` + `register`.
|
||||
///
|
||||
/// # Panics
|
||||
///
|
||||
/// Panics if `self.base` + `register` does not belong to the mapped memory of the PCIe device.
|
||||
fn write_reg(&self, register: u32, data: u32) -> u32 {
|
||||
assert!(
|
||||
register as usize <= self.size - 4 as usize,
|
||||
"MMIO access out of bounds"
|
||||
);
|
||||
|
||||
unsafe {
|
||||
ptr::write_volatile((self.base + register as usize) as *mut u32, data);
|
||||
ptr::read_volatile((self.base + register as usize) as *mut u32)
|
||||
}
|
||||
}
|
||||
|
||||
fn write_flag(&self, register: u32, flags: u32) {
|
||||
self.write_reg(register, self.read_reg(register) | flags);
|
||||
}
|
||||
|
||||
fn clear_flag(&self, register: u32, flags: u32) {
|
||||
self.write_reg(register, self.read_reg(register) & !flags);
|
||||
}
|
||||
|
||||
fn wait_clear_reg(&self, register: u32, value: u32) {
|
||||
loop {
|
||||
let current = self.read_reg(register);
|
||||
if (current & value) == 0 {
|
||||
break;
|
||||
}
|
||||
thread::sleep(Duration::from_millis(100));
|
||||
}
|
||||
}
|
||||
|
||||
fn wait_write_reg(&self, register: u32, value: u32) {
|
||||
loop {
|
||||
let current = self.read_reg(register);
|
||||
if (current & value) == value {
|
||||
break;
|
||||
}
|
||||
thread::sleep(Duration::from_millis(100));
|
||||
}
|
||||
}
|
||||
|
||||
/// Resets and initializes an ixgbe device.
|
||||
fn init(&mut self) {
|
||||
// section 4.6.3.1 - disable all interrupts
|
||||
self.write_reg(IXGBE_EIMC, 0x7fff_ffff);
|
||||
|
||||
// section 4.6.3.2
|
||||
self.write_reg(IXGBE_CTRL, IXGBE_CTRL_RST_MASK);
|
||||
self.wait_clear_reg(IXGBE_CTRL, IXGBE_CTRL_RST_MASK);
|
||||
thread::sleep(Duration::from_millis(10));
|
||||
|
||||
// section 4.6.3.1 - disable interrupts again after reset
|
||||
self.write_reg(IXGBE_EIMC, 0x7fff_ffff);
|
||||
|
||||
let mac = self.get_mac_addr();
|
||||
|
||||
println!(
|
||||
" - MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]
|
||||
);
|
||||
|
||||
self.mac_address = mac;
|
||||
|
||||
// section 4.6.3 - wait for EEPROM auto read completion
|
||||
self.wait_write_reg(IXGBE_EEC, IXGBE_EEC_ARD);
|
||||
|
||||
// section 4.6.3 - wait for dma initialization done
|
||||
self.wait_write_reg(
|
||||
IXGBE_RDRXCTL,
|
||||
IXGBE_RDRXCTL_DMAIDONE | IXGBE_RDRXCTL_RESERVED_BITS,
|
||||
);
|
||||
|
||||
// section 4.6.4 - initialize link (auto negotiation)
|
||||
self.init_link();
|
||||
|
||||
// section 4.6.5 - statistical counters
|
||||
// reset-on-read registers, just read them once
|
||||
self.reset_stats();
|
||||
|
||||
// section 4.6.7 - init rx
|
||||
self.init_rx();
|
||||
|
||||
// section 4.6.8 - init tx
|
||||
self.init_tx();
|
||||
|
||||
// start a single receive queue/ring
|
||||
self.start_rx_queue(0);
|
||||
|
||||
// start a single transmit queue/ring
|
||||
self.start_tx_queue(0);
|
||||
|
||||
// section 4.6.3.9 - enable interrupts
|
||||
self.enable_msix_interrupt(0);
|
||||
|
||||
// wait some time for the link to come up
|
||||
self.wait_for_link();
|
||||
}
|
||||
|
||||
/// Resets the stats of this device.
|
||||
fn reset_stats(&self) {
|
||||
self.read_reg(IXGBE_GPRC);
|
||||
self.read_reg(IXGBE_GPTC);
|
||||
self.read_reg(IXGBE_GORCL);
|
||||
self.read_reg(IXGBE_GORCH);
|
||||
self.read_reg(IXGBE_GOTCL);
|
||||
self.read_reg(IXGBE_GOTCH);
|
||||
}
|
||||
|
||||
// sections 4.6.7
|
||||
/// Initializes the rx queues of this device.
|
||||
fn init_rx(&mut self) {
|
||||
// disable rx while re-configuring it
|
||||
self.clear_flag(IXGBE_RXCTRL, IXGBE_RXCTRL_RXEN);
|
||||
|
||||
// section 4.6.11.3.4 - allocate all queues and traffic to PB0
|
||||
self.write_reg(IXGBE_RXPBSIZE(0), IXGBE_RXPBSIZE_128KB);
|
||||
for i in 1..8 {
|
||||
self.write_reg(IXGBE_RXPBSIZE(i), 0);
|
||||
}
|
||||
|
||||
// enable CRC offloading
|
||||
self.write_flag(IXGBE_HLREG0, IXGBE_HLREG0_RXCRCSTRP);
|
||||
self.write_flag(IXGBE_RDRXCTL, IXGBE_RDRXCTL_CRCSTRIP);
|
||||
|
||||
// accept broadcast packets
|
||||
self.write_flag(IXGBE_FCTRL, IXGBE_FCTRL_BAM);
|
||||
|
||||
// configure a single receive queue/ring
|
||||
let i: u32 = 0;
|
||||
|
||||
// enable advanced rx descriptors
|
||||
self.write_reg(
|
||||
IXGBE_SRRCTL(i),
|
||||
(self.read_reg(IXGBE_SRRCTL(i)) & !IXGBE_SRRCTL_DESCTYPE_MASK)
|
||||
| IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF,
|
||||
);
|
||||
// let nic drop packets if no rx descriptor is available instead of buffering them
|
||||
self.write_flag(IXGBE_SRRCTL(i), IXGBE_SRRCTL_DROP_EN);
|
||||
|
||||
self.write_reg(IXGBE_RDBAL(i), self.receive_ring.physical() as u32);
|
||||
|
||||
self.write_reg(
|
||||
IXGBE_RDBAH(i),
|
||||
((self.receive_ring.physical() as u64) >> 32) as u32,
|
||||
);
|
||||
self.write_reg(
|
||||
IXGBE_RDLEN(i),
|
||||
(self.receive_ring.len() * mem::size_of::<ixgbe_adv_rx_desc>()) as u32,
|
||||
);
|
||||
|
||||
// set ring to empty at start
|
||||
self.write_reg(IXGBE_RDH(i), 0);
|
||||
self.write_reg(IXGBE_RDT(i), 0);
|
||||
|
||||
// last sentence of section 4.6.7 - set some magic bits
|
||||
self.write_flag(IXGBE_CTRL_EXT, IXGBE_CTRL_EXT_NS_DIS);
|
||||
|
||||
// probably a broken feature, this flag is initialized with 1 but has to be set to 0
|
||||
self.clear_flag(IXGBE_DCA_RXCTRL(i), 1 << 12);
|
||||
|
||||
// enable promisc mode by default to make testing easier
|
||||
// this has to be done when the rxctrl.rxen bit is not set
|
||||
self.set_promisc(true);
|
||||
|
||||
// start rx
|
||||
self.write_flag(IXGBE_RXCTRL, IXGBE_RXCTRL_RXEN);
|
||||
}
|
||||
|
||||
// section 4.6.8
|
||||
/// Initializes the tx queues of this device.
|
||||
fn init_tx(&mut self) {
|
||||
// crc offload and small packet padding
|
||||
self.write_flag(IXGBE_HLREG0, IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
|
||||
|
||||
// section 4.6.11.3.4 - set default buffer size allocations
|
||||
self.write_reg(IXGBE_TXPBSIZE(0), IXGBE_TXPBSIZE_40KB);
|
||||
for i in 1..8 {
|
||||
self.write_reg(IXGBE_TXPBSIZE(i), 0);
|
||||
}
|
||||
|
||||
// required when not using DCB/VTd
|
||||
self.write_reg(IXGBE_DTXMXSZRQ, 0xfff);
|
||||
self.clear_flag(IXGBE_RTTDCS, IXGBE_RTTDCS_ARBDIS);
|
||||
|
||||
// configure a single transmit queue/ring
|
||||
let i: u32 = 0;
|
||||
|
||||
// section 7.1.9 - setup descriptor ring
|
||||
|
||||
self.write_reg(IXGBE_TDBAL(i), self.transmit_ring.physical() as u32);
|
||||
self.write_reg(
|
||||
IXGBE_TDBAH(i),
|
||||
((self.transmit_ring.physical() as u64) >> 32) as u32,
|
||||
);
|
||||
self.write_reg(
|
||||
IXGBE_TDLEN(i),
|
||||
(self.transmit_ring.len() * mem::size_of::<ixgbe_adv_tx_desc>()) as u32,
|
||||
);
|
||||
|
||||
// descriptor writeback magic values, important to get good performance and low PCIe overhead
|
||||
// see 7.2.3.4.1 and 7.2.3.5 for an explanation of these values and how to find good ones
|
||||
// we just use the defaults from DPDK here, but this is a potentially interesting point for optimizations
|
||||
let mut txdctl = self.read_reg(IXGBE_TXDCTL(i));
|
||||
// there are no defines for this in ixgbe.rs for some reason
|
||||
// pthresh: 6:0, hthresh: 14:8, wthresh: 22:16
|
||||
txdctl &= !(0x3F | (0x3F << 8) | (0x3F << 16));
|
||||
txdctl |= 36 | (8 << 8) | (4 << 16);
|
||||
|
||||
self.write_reg(IXGBE_TXDCTL(i), txdctl);
|
||||
|
||||
// final step: enable DMA
|
||||
self.write_reg(IXGBE_DMATXCTL, IXGBE_DMATXCTL_TE);
|
||||
}
|
||||
|
||||
/// Sets the rx queues` descriptors and enables the queues.
|
||||
///
|
||||
/// # Panics
|
||||
/// Panics if length of `self.receive_ring` is not a power of 2.
|
||||
fn start_rx_queue(&mut self, queue_id: u16) {
|
||||
if self.receive_ring.len() & (self.receive_ring.len() - 1) != 0 {
|
||||
panic!("number of receive queue entries must be a power of 2");
|
||||
}
|
||||
|
||||
for i in 0..self.receive_ring.len() {
|
||||
self.receive_ring[i].read.pkt_addr = self.receive_buffer[i].physical() as u64;
|
||||
self.receive_ring[i].read.hdr_addr = 0;
|
||||
}
|
||||
|
||||
// enable queue and wait if necessary
|
||||
self.write_flag(IXGBE_RXDCTL(u32::from(queue_id)), IXGBE_RXDCTL_ENABLE);
|
||||
self.wait_write_reg(IXGBE_RXDCTL(u32::from(queue_id)), IXGBE_RXDCTL_ENABLE);
|
||||
|
||||
// rx queue starts out full
|
||||
self.write_reg(IXGBE_RDH(u32::from(queue_id)), 0);
|
||||
|
||||
// was set to 0 before in the init function
|
||||
self.write_reg(
|
||||
IXGBE_RDT(u32::from(queue_id)),
|
||||
(self.receive_ring.len() - 1) as u32,
|
||||
);
|
||||
}
|
||||
|
||||
/// Enables the tx queues.
|
||||
///
|
||||
/// # Panics
|
||||
/// Panics if length of `self.transmit_ring` is not a power of 2.
|
||||
fn start_tx_queue(&mut self, queue_id: u16) {
|
||||
if self.transmit_ring.len() & (self.transmit_ring.len() - 1) != 0 {
|
||||
panic!("number of receive queue entries must be a power of 2");
|
||||
}
|
||||
|
||||
for i in 0..self.transmit_ring.len() {
|
||||
self.transmit_ring[i].read.buffer_addr = self.transmit_buffer[i].physical() as u64;
|
||||
}
|
||||
|
||||
// tx queue starts out empty
|
||||
self.write_reg(IXGBE_TDH(u32::from(queue_id)), 0);
|
||||
self.write_reg(IXGBE_TDT(u32::from(queue_id)), 0);
|
||||
|
||||
// enable queue and wait if necessary
|
||||
self.write_flag(IXGBE_TXDCTL(u32::from(queue_id)), IXGBE_TXDCTL_ENABLE);
|
||||
self.wait_write_reg(IXGBE_TXDCTL(u32::from(queue_id)), IXGBE_TXDCTL_ENABLE);
|
||||
}
|
||||
|
||||
// see section 4.6.4
|
||||
/// Initializes the link of this device.
|
||||
fn init_link(&self) {
|
||||
// link auto-configuration register should already be set correctly, we're resetting it anyway
|
||||
self.write_reg(
|
||||
IXGBE_AUTOC,
|
||||
(self.read_reg(IXGBE_AUTOC) & !IXGBE_AUTOC_LMS_MASK) | IXGBE_AUTOC_LMS_10G_SERIAL,
|
||||
);
|
||||
self.write_reg(
|
||||
IXGBE_AUTOC,
|
||||
(self.read_reg(IXGBE_AUTOC) & !IXGBE_AUTOC_10G_PMA_PMD_MASK) | IXGBE_AUTOC_10G_XAUI,
|
||||
);
|
||||
// negotiate link
|
||||
self.write_flag(IXGBE_AUTOC, IXGBE_AUTOC_AN_RESTART);
|
||||
// datasheet wants us to wait for the link here, but we can continue and wait afterwards
|
||||
}
|
||||
|
||||
/// Waits for the link to come up.
|
||||
fn wait_for_link(&self) {
|
||||
println!(" - waiting for link");
|
||||
let time = Instant::now();
|
||||
let mut speed = self.get_link_speed();
|
||||
while speed == 0 && time.elapsed().as_secs() < 10 {
|
||||
thread::sleep(Duration::from_millis(100));
|
||||
speed = self.get_link_speed();
|
||||
}
|
||||
println!(" - link speed is {} Mbit/s", self.get_link_speed());
|
||||
}
|
||||
|
||||
/// Enables or disables promisc mode of this device.
|
||||
fn set_promisc(&self, enabled: bool) {
|
||||
if enabled {
|
||||
self.write_flag(IXGBE_FCTRL, IXGBE_FCTRL_MPE | IXGBE_FCTRL_UPE);
|
||||
} else {
|
||||
self.clear_flag(IXGBE_FCTRL, IXGBE_FCTRL_MPE | IXGBE_FCTRL_UPE);
|
||||
}
|
||||
}
|
||||
|
||||
/// Set the IVAR registers, mapping interrupt causes to vectors.
|
||||
fn set_ivar(&mut self, direction: i8, queue_id: u16, mut msix_vector: u8) {
|
||||
let index = ((16 * (queue_id & 1)) as i16 + i16::from(8 * direction)) as u32;
|
||||
|
||||
msix_vector |= IXGBE_IVAR_ALLOC_VAL as u8;
|
||||
|
||||
let mut ivar = self.read_reg(IXGBE_IVAR(u32::from(queue_id >> 1)));
|
||||
ivar &= !(0xFF << index);
|
||||
ivar |= u32::from(msix_vector << index);
|
||||
|
||||
self.write_reg(IXGBE_IVAR(u32::from(queue_id >> 1)), ivar);
|
||||
}
|
||||
|
||||
/// Enable MSI-X interrupt for a queue.
|
||||
fn enable_msix_interrupt(&mut self, queue_id: u16) {
|
||||
// Step 1: The software driver associates between interrupt causes and MSI-X vectors and the
|
||||
//throttling timers EITR[n] by programming the IVAR[n] and IVAR_MISC registers.
|
||||
self.set_ivar(0, queue_id, queue_id as u8);
|
||||
|
||||
// Step 2: Program SRRCTL[n].RDMTS (per receive queue) if software uses the receive
|
||||
// descriptor minimum threshold interrupt
|
||||
|
||||
// Step 3: The EIAC[n] registers should be set to auto clear for transmit and receive interrupt
|
||||
// causes (for best performance). The EIAC bits that control the other and TCP timer
|
||||
// interrupt causes should be set to 0b (no auto clear).
|
||||
self.write_reg(IXGBE_EIAC, IXGBE_EICR_RTX_QUEUE);
|
||||
|
||||
// Step 4: Set the auto mask in the EIAM register according to the preferred mode of operation.
|
||||
|
||||
// Step 5: Set the interrupt throttling in EITR[n] and GPIE according to the preferred mode of operation.
|
||||
|
||||
// Step 6: Software enables the required interrupt causes by setting the EIMS register
|
||||
let mut mask: u32 = self.read_reg(IXGBE_EIMS);
|
||||
mask |= 1 << queue_id;
|
||||
|
||||
self.write_reg(IXGBE_EIMS, mask);
|
||||
}
|
||||
|
||||
/// Returns the link speed of this device.
|
||||
fn get_link_speed(&self) -> u16 {
|
||||
let speed = self.read_reg(IXGBE_LINKS);
|
||||
if (speed & IXGBE_LINKS_UP) == 0 {
|
||||
return 0;
|
||||
}
|
||||
match speed & IXGBE_LINKS_SPEED_82599 {
|
||||
IXGBE_LINKS_SPEED_100_82599 => 100,
|
||||
IXGBE_LINKS_SPEED_1G_82599 => 1000,
|
||||
IXGBE_LINKS_SPEED_10G_82599 => 10000,
|
||||
_ => 0,
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,315 @@
|
||||
#![allow(non_snake_case)]
|
||||
#![allow(non_camel_case_types)]
|
||||
#![allow(non_upper_case_globals)]
|
||||
#![allow(clippy::unreadable_literal)]
|
||||
|
||||
pub const IXGBE_EIMC: u32 = 0x00888;
|
||||
|
||||
pub const IXGBE_CTRL: u32 = 0x00000;
|
||||
pub const IXGBE_CTRL_LNK_RST: u32 = 0x00000008; /* Link Reset. Resets everything. */
|
||||
pub const IXGBE_CTRL_RST: u32 = 0x04000000; /* Reset (SW) */
|
||||
pub const IXGBE_CTRL_RST_MASK: u32 = IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST;
|
||||
|
||||
pub const IXGBE_EEC: u32 = 0x10010;
|
||||
pub const IXGBE_EEC_ARD: u32 = 0x00000200; /* EEPROM Auto Read Done */
|
||||
|
||||
pub const IXGBE_RDRXCTL: u32 = 0x02F00;
|
||||
pub const IXGBE_RDRXCTL_RESERVED_BITS: u32 = 1 << 25 | 1 << 26;
|
||||
pub const IXGBE_RDRXCTL_DMAIDONE: u32 = 0x00000008; /* DMA init cycle done */
|
||||
|
||||
pub const IXGBE_AUTOC: u32 = 0x042A0;
|
||||
pub const IXGBE_AUTOC_LMS_SHIFT: u32 = 13;
|
||||
pub const IXGBE_AUTOC_LMS_MASK: u32 = 0x7 << IXGBE_AUTOC_LMS_SHIFT;
|
||||
pub const IXGBE_AUTOC_LMS_10G_SERIAL: u32 = 0x3 << IXGBE_AUTOC_LMS_SHIFT;
|
||||
pub const IXGBE_AUTOC_10G_PMA_PMD_MASK: u32 = 0x00000180;
|
||||
pub const IXGBE_AUTOC_10G_PMA_PMD_SHIFT: u32 = 7;
|
||||
pub const IXGBE_AUTOC_10G_XAUI: u32 = 0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT;
|
||||
pub const IXGBE_AUTOC_AN_RESTART: u32 = 0x00001000;
|
||||
|
||||
pub const IXGBE_GPRC: u32 = 0x04074;
|
||||
pub const IXGBE_GPTC: u32 = 0x04080;
|
||||
pub const IXGBE_GORCL: u32 = 0x04088;
|
||||
pub const IXGBE_GORCH: u32 = 0x0408C;
|
||||
pub const IXGBE_GOTCL: u32 = 0x04090;
|
||||
pub const IXGBE_GOTCH: u32 = 0x04094;
|
||||
|
||||
pub const IXGBE_RXCTRL: u32 = 0x03000;
|
||||
pub const IXGBE_RXCTRL_RXEN: u32 = 0x00000001; /* Enable Receiver */
|
||||
|
||||
pub fn IXGBE_RXPBSIZE(i: u32) -> u32 {
|
||||
0x03C00 + (i * 4)
|
||||
}
|
||||
|
||||
pub const IXGBE_RXPBSIZE_128KB: u32 = 0x00020000; /* 128KB Packet Buffer */
|
||||
pub const IXGBE_HLREG0: u32 = 0x04240;
|
||||
pub const IXGBE_HLREG0_RXCRCSTRP: u32 = 0x00000002; /* bit 1 */
|
||||
pub const IXGBE_RDRXCTL_CRCSTRIP: u32 = 0x00000002; /* CRC Strip */
|
||||
|
||||
pub const IXGBE_FCTRL: u32 = 0x05080;
|
||||
pub const IXGBE_FCTRL_BAM: u32 = 0x00000400; /* Broadcast Accept Mode */
|
||||
|
||||
pub fn IXGBE_SRRCTL(i: u32) -> u32 {
|
||||
if i <= 15 {
|
||||
0x02100 + (i * 4)
|
||||
} else if i < 64 {
|
||||
0x01014 + (i * 0x40)
|
||||
} else {
|
||||
0x0D014 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
|
||||
pub const IXGBE_SRRCTL_DESCTYPE_MASK: u32 = 0x0E000000;
|
||||
pub const IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF: u32 = 0x02000000;
|
||||
pub const IXGBE_SRRCTL_DROP_EN: u32 = 0x10000000;
|
||||
|
||||
pub fn IXGBE_RDBAL(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01000 + (i * 0x40)
|
||||
} else {
|
||||
0x0D000 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
pub fn IXGBE_RDBAH(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01004 + (i * 0x40)
|
||||
} else {
|
||||
0x0D004 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
pub fn IXGBE_RDLEN(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01008 + (i * 0x40)
|
||||
} else {
|
||||
0x0D008 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
pub fn IXGBE_RDH(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01010 + (i * 0x40)
|
||||
} else {
|
||||
0x0D010 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
pub fn IXGBE_RDT(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01018 + (i * 0x40)
|
||||
} else {
|
||||
0x0D018 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
|
||||
pub const IXGBE_CTRL_EXT: u32 = 0x00018;
|
||||
pub const IXGBE_CTRL_EXT_NS_DIS: u32 = 0x00010000; /* No Snoop disable */
|
||||
|
||||
pub fn IXGBE_DCA_RXCTRL(i: u32) -> u32 {
|
||||
if i <= 15 {
|
||||
0x02200 + (i * 4)
|
||||
} else if i < 64 {
|
||||
0x0100C + (i * 0x40)
|
||||
} else {
|
||||
0x0D00C + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
|
||||
pub const IXGBE_HLREG0_TXCRCEN: u32 = 0x00000001; /* bit 0 */
|
||||
pub const IXGBE_HLREG0_TXPADEN: u32 = 0x00000400; /* bit 10 */
|
||||
|
||||
pub fn IXGBE_TXPBSIZE(i: u32) -> u32 {
|
||||
0x0CC00 + (i * 4)
|
||||
} /* 8 of these */
|
||||
|
||||
pub const IXGBE_TXPBSIZE_40KB: u32 = 0x0000A000; /* 40KB Packet Buffer */
|
||||
pub const IXGBE_DTXMXSZRQ: u32 = 0x08100;
|
||||
pub const IXGBE_RTTDCS: u32 = 0x04900;
|
||||
pub const IXGBE_RTTDCS_ARBDIS: u32 = 0x00000040; /* DCB arbiter disable */
|
||||
|
||||
pub fn IXGBE_TDBAL(i: u32) -> u32 {
|
||||
0x06000 + (i * 0x40)
|
||||
} /* 32 of them (0-31)*/
|
||||
pub fn IXGBE_TDBAH(i: u32) -> u32 {
|
||||
0x06004 + (i * 0x40)
|
||||
}
|
||||
pub fn IXGBE_TDLEN(i: u32) -> u32 {
|
||||
0x06008 + (i * 0x40)
|
||||
}
|
||||
pub fn IXGBE_TXDCTL(i: u32) -> u32 {
|
||||
0x06028 + (i * 0x40)
|
||||
}
|
||||
|
||||
pub const IXGBE_DMATXCTL: u32 = 0x04A80;
|
||||
pub const IXGBE_DMATXCTL_TE: u32 = 0x1; /* Transmit Enable */
|
||||
|
||||
pub fn IXGBE_RXDCTL(i: u32) -> u32 {
|
||||
if i < 64 {
|
||||
0x01028 + (i * 0x40)
|
||||
} else {
|
||||
0x0D028 + ((i - 64) * 0x40)
|
||||
}
|
||||
}
|
||||
pub const IXGBE_RXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Rx Queue */
|
||||
pub const IXGBE_TXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Tx Queue */
|
||||
|
||||
pub fn IXGBE_TDH(i: u32) -> u32 {
|
||||
0x06010 + (i * 0x40)
|
||||
}
|
||||
pub fn IXGBE_TDT(i: u32) -> u32 {
|
||||
0x06018 + (i * 0x40)
|
||||
}
|
||||
|
||||
pub const IXGBE_FCTRL_MPE: u32 = 0x00000100; /* Multicast Promiscuous Ena*/
|
||||
pub const IXGBE_FCTRL_UPE: u32 = 0x00000200; /* Unicast Promiscuous Ena */
|
||||
|
||||
pub const IXGBE_LINKS: u32 = 0x042A4;
|
||||
pub const IXGBE_LINKS_UP: u32 = 0x40000000;
|
||||
pub const IXGBE_LINKS_SPEED_82599: u32 = 0x30000000;
|
||||
pub const IXGBE_LINKS_SPEED_100_82599: u32 = 0x10000000;
|
||||
pub const IXGBE_LINKS_SPEED_1G_82599: u32 = 0x20000000;
|
||||
pub const IXGBE_LINKS_SPEED_10G_82599: u32 = 0x30000000;
|
||||
|
||||
pub fn IXGBE_RAL(i: u32) -> u32 {
|
||||
if i <= 15 {
|
||||
0x05400 + (i * 8)
|
||||
} else {
|
||||
0x0A200 + (i * 8)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn IXGBE_RAH(i: u32) -> u32 {
|
||||
if i <= 15 {
|
||||
0x05404 + (i * 8)
|
||||
} else {
|
||||
0x0A204 + (i * 8)
|
||||
}
|
||||
}
|
||||
|
||||
pub const IXGBE_RXD_STAT_DD: u32 = 0x01; /* Descriptor Done */
|
||||
pub const IXGBE_RXD_STAT_EOP: u32 = 0x02; /* End of Packet */
|
||||
pub const IXGBE_RXDADV_STAT_DD: u32 = IXGBE_RXD_STAT_DD; /* Done */
|
||||
pub const IXGBE_RXDADV_STAT_EOP: u32 = IXGBE_RXD_STAT_EOP; /* End of Packet */
|
||||
|
||||
pub const IXGBE_ADVTXD_PAYLEN_SHIFT: u32 = 14; /* Adv desc PAYLEN shift */
|
||||
pub const IXGBE_TXD_CMD_EOP: u32 = 0x01000000; /* End of Packet */
|
||||
pub const IXGBE_ADVTXD_DCMD_EOP: u32 = IXGBE_TXD_CMD_EOP; /* End of Packet */
|
||||
pub const IXGBE_TXD_CMD_RS: u32 = 0x08000000; /* Report Status */
|
||||
pub const IXGBE_ADVTXD_DCMD_RS: u32 = IXGBE_TXD_CMD_RS; /* Report Status */
|
||||
pub const IXGBE_TXD_CMD_IFCS: u32 = 0x02000000; /* Insert FCS (Ethernet CRC) */
|
||||
pub const IXGBE_ADVTXD_DCMD_IFCS: u32 = IXGBE_TXD_CMD_IFCS; /* Insert FCS */
|
||||
pub const IXGBE_TXD_CMD_DEXT: u32 = 0x20000000; /* Desc extension (0 = legacy) */
|
||||
pub const IXGBE_ADVTXD_DTYP_DATA: u32 = 0x00300000; /* Adv Data Descriptor */
|
||||
pub const IXGBE_ADVTXD_DCMD_DEXT: u32 = IXGBE_TXD_CMD_DEXT; /* Desc ext 1=Adv */
|
||||
pub const IXGBE_TXD_STAT_DD: u32 = 0x00000001; /* Descriptor Done */
|
||||
pub const IXGBE_ADVTXD_STAT_DD: u32 = IXGBE_TXD_STAT_DD; /* Descriptor Done */
|
||||
|
||||
/* Interrupt Registers */
|
||||
pub const IXGBE_EICR: u32 = 0x00800;
|
||||
pub const IXGBE_EIAC: u32 = 0x00810;
|
||||
pub const IXGBE_EIMS: u32 = 0x00880;
|
||||
pub const IXGBE_IVAR_ALLOC_VAL: u32 = 0x80; /* Interrupt Allocation valid */
|
||||
pub const IXGBE_EICR_RTX_QUEUE: u32 = 0x0000FFFF; /* RTx Queue Interrupt */
|
||||
|
||||
pub fn IXGBE_IVAR(i: u32) -> u32 {
|
||||
0x00900 + (i * 4)
|
||||
} /* 24 at 0x900-0x960 */
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_read {
|
||||
pub pkt_addr: u64,
|
||||
/* Packet buffer address */
|
||||
pub hdr_addr: u64,
|
||||
/* Header buffer address */
|
||||
}
|
||||
|
||||
/* Receive Descriptor - Advanced */
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss {
|
||||
pub pkt_info: u16,
|
||||
/* RSS, Pkt type */
|
||||
pub hdr_info: u16,
|
||||
/* Splithdr, hdrlen */
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub union ixgbe_adv_rx_desc_wb_lower_lo_dword {
|
||||
pub data: u32,
|
||||
pub hs_rss: ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip {
|
||||
pub ip_id: u16,
|
||||
/* IP id */
|
||||
pub csum: u16,
|
||||
/* Packet Checksum */
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub union ixgbe_adv_rx_desc_wb_lower_hi_dword {
|
||||
pub rss: u32,
|
||||
/* RSS Hash */
|
||||
pub csum_ip: ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_wb_lower {
|
||||
pub lo_dword: ixgbe_adv_rx_desc_wb_lower_lo_dword,
|
||||
pub hi_dword: ixgbe_adv_rx_desc_wb_lower_hi_dword,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_wb_upper {
|
||||
pub status_error: u32,
|
||||
/* ext status/error */
|
||||
pub length: u16,
|
||||
/* Packet length */
|
||||
pub vlan: u16,
|
||||
/* VLAN tag */
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_rx_desc_wb {
|
||||
pub lower: ixgbe_adv_rx_desc_wb_lower,
|
||||
pub upper: ixgbe_adv_rx_desc_wb_upper,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub union ixgbe_adv_rx_desc {
|
||||
pub read: ixgbe_adv_rx_desc_read,
|
||||
pub wb: ixgbe_adv_rx_desc_wb, /* writeback */
|
||||
_union_align: [u64; 2],
|
||||
}
|
||||
|
||||
/* Transmit Descriptor - Advanced */
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_tx_desc_read {
|
||||
pub buffer_addr: u64,
|
||||
/* Address of descriptor's data buf */
|
||||
pub cmd_type_len: u32,
|
||||
pub olinfo_status: u32,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub struct ixgbe_adv_tx_desc_wb {
|
||||
pub rsvd: u64,
|
||||
/* Reserved */
|
||||
pub nxtseq_seed: u32,
|
||||
pub status: u32,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(C, packed)]
|
||||
pub union ixgbe_adv_tx_desc {
|
||||
pub read: ixgbe_adv_tx_desc_read,
|
||||
pub wb: ixgbe_adv_tx_desc_wb,
|
||||
_union_align: [u64; 2],
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
use std::io::{Read, Write};
|
||||
use std::os::unix::io::AsRawFd;
|
||||
|
||||
use driver_network::NetworkScheme;
|
||||
use event::{user_data, EventQueue};
|
||||
use pcid_interface::PciFunctionHandle;
|
||||
|
||||
pub mod device;
|
||||
#[rustfmt::skip]
|
||||
mod ixgbe;
|
||||
|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon);
|
||||
}
|
||||
|
||||
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
|
||||
let pci_config = pcid_handle.config();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_ixgbe");
|
||||
|
||||
let irq = pci_config
|
||||
.func
|
||||
.legacy_interrupt_line
|
||||
.expect("ixgbed: no legacy interrupts supported");
|
||||
|
||||
println!(" + IXGBE {}", pci_config.func.display());
|
||||
|
||||
let mut irq_file = irq.irq_handle("ixgbed");
|
||||
|
||||
let mapped_bar = unsafe { pcid_handle.map_bar(0) };
|
||||
let address = mapped_bar.ptr.as_ptr();
|
||||
let size = mapped_bar.bar_size;
|
||||
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || {
|
||||
device::Intel8259x::new(address as usize, size)
|
||||
.expect("ixgbed: failed to allocate device")
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
user_data! {
|
||||
enum Source {
|
||||
Irq,
|
||||
Scheme,
|
||||
}
|
||||
}
|
||||
|
||||
let event_queue = EventQueue::<Source>::new().expect("ixgbed: Could not create event queue.");
|
||||
event_queue
|
||||
.subscribe(
|
||||
irq_file.as_raw_fd() as usize,
|
||||
Source::Irq,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
event_queue
|
||||
.subscribe(
|
||||
scheme.event_handle().raw(),
|
||||
Source::Scheme,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
libredox::call::setrens(0, 0).expect("ixgbed: failed to enter null namespace");
|
||||
|
||||
scheme.tick().unwrap();
|
||||
|
||||
for event in event_queue.map(|e| e.expect("ixgbed: failed to get next event")) {
|
||||
match event.user_data {
|
||||
Source::Irq => {
|
||||
let mut irq = [0; 8];
|
||||
irq_file.read(&mut irq).unwrap();
|
||||
if scheme.adapter().irq() {
|
||||
irq_file.write(&mut irq).unwrap();
|
||||
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
Source::Scheme => {
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
unreachable!()
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
[package]
|
||||
name = "rtl8139d"
|
||||
description = "Realtek 8139 ethernet driver"
|
||||
version = "0.1.0"
|
||||
edition = "2018"
|
||||
|
||||
[dependencies]
|
||||
bitflags.workspace = true
|
||||
libredox.workspace = true
|
||||
log.workspace = true
|
||||
redox_event.workspace = true
|
||||
redox_syscall.workspace = true
|
||||
|
||||
common = { path = "../../common" }
|
||||
daemon = { path = "../../../daemon" }
|
||||
driver-network = { path = "../driver-network" }
|
||||
pcid = { path = "../../pcid" }
|
||||
|
||||
[lints]
|
||||
workspace = true
|
||||
@@ -0,0 +1,5 @@
|
||||
[[drivers]]
|
||||
name = "RTL8139 NIC"
|
||||
class = 0x02
|
||||
ids = { 0x10ec = [0x8139] }
|
||||
command = ["rtl8139d"]
|
||||
@@ -0,0 +1,309 @@
|
||||
use std::convert::TryInto;
|
||||
use std::mem;
|
||||
|
||||
use driver_network::NetworkAdapter;
|
||||
use syscall::error::{Error, Result, EIO, EMSGSIZE};
|
||||
|
||||
use common::dma::Dma;
|
||||
use common::io::{Io, Mmio, ReadOnly};
|
||||
use common::timeout::Timeout;
|
||||
|
||||
const RX_BUFFER_SIZE: usize = 64 * 1024;
|
||||
|
||||
const RXSTS_ROK: u16 = 1 << 0;
|
||||
|
||||
const TSD_TOK: u32 = 1 << 15;
|
||||
const TSD_OWN: u32 = 1 << 13;
|
||||
const TSD_SIZE_MASK: u32 = 0x1FFF;
|
||||
|
||||
const CR_RST: u8 = 1 << 4;
|
||||
const CR_RE: u8 = 1 << 3;
|
||||
const CR_TE: u8 = 1 << 2;
|
||||
const CR_BUFE: u8 = 1 << 0;
|
||||
|
||||
const IMR_TOK: u16 = 1 << 2;
|
||||
const IMR_ROK: u16 = 1 << 0;
|
||||
|
||||
const RCR_RBLEN_8K: u32 = 0b00 << 11;
|
||||
const RCR_RBLEN_16K: u32 = 0b01 << 11;
|
||||
const RCR_RBLEN_32K: u32 = 0b10 << 11;
|
||||
const RCR_RBLEN_64K: u32 = 0b11 << 11;
|
||||
const RCR_RBLEN_MASK: u32 = 0b11 << 11;
|
||||
const RCR_AER: u32 = 1 << 5;
|
||||
const RCR_AR: u32 = 1 << 4;
|
||||
const RCR_AB: u32 = 1 << 3;
|
||||
const RCR_AM: u32 = 1 << 2;
|
||||
const RCR_APM: u32 = 1 << 1;
|
||||
const RCR_AAP: u32 = 1 << 0;
|
||||
|
||||
#[repr(C, packed)]
|
||||
struct Regs {
|
||||
mac: [Mmio<u32>; 2],
|
||||
mar: [Mmio<u32>; 2],
|
||||
tsd: [Mmio<u32>; 4],
|
||||
tsad: [Mmio<u32>; 4],
|
||||
rbstart: Mmio<u32>,
|
||||
erbcr: ReadOnly<Mmio<u16>>,
|
||||
ersr: ReadOnly<Mmio<u8>>,
|
||||
cr: Mmio<u8>,
|
||||
capr: Mmio<u16>,
|
||||
cbr: ReadOnly<Mmio<u16>>,
|
||||
imr: Mmio<u16>,
|
||||
isr: Mmio<u16>,
|
||||
tcr: Mmio<u32>,
|
||||
rcr: Mmio<u32>,
|
||||
tctr: Mmio<u32>,
|
||||
mpc: Mmio<u32>,
|
||||
cr_9346: Mmio<u8>,
|
||||
config0: Mmio<u8>,
|
||||
config1: Mmio<u8>,
|
||||
rsvd_53: ReadOnly<Mmio<u8>>,
|
||||
timer_int: Mmio<u32>,
|
||||
msr: Mmio<u8>,
|
||||
config2: Mmio<u8>,
|
||||
config3: Mmio<u8>,
|
||||
rsvd_5b: ReadOnly<Mmio<u8>>,
|
||||
mulint: Mmio<u16>,
|
||||
rerid: ReadOnly<Mmio<u8>>,
|
||||
rsvd_5f: ReadOnly<Mmio<u8>>,
|
||||
tsts: ReadOnly<Mmio<u16>>,
|
||||
_todo: [ReadOnly<Mmio<u8>>; 158],
|
||||
}
|
||||
|
||||
impl Regs {
|
||||
unsafe fn from_base(base: usize) -> &'static mut Self {
|
||||
assert_eq!(mem::size_of::<Regs>(), 256);
|
||||
|
||||
let regs = &mut *(base as *mut Regs);
|
||||
|
||||
assert_eq!(®s.mac[0] as *const _ as usize - base, 0x00);
|
||||
assert_eq!(®s.mac[1] as *const _ as usize - base, 0x04);
|
||||
assert_eq!(®s.mar[0] as *const _ as usize - base, 0x08);
|
||||
assert_eq!(®s.mar[1] as *const _ as usize - base, 0x0C);
|
||||
assert_eq!(®s.tsd[0] as *const _ as usize - base, 0x10);
|
||||
assert_eq!(®s.tsd[1] as *const _ as usize - base, 0x14);
|
||||
assert_eq!(®s.tsd[2] as *const _ as usize - base, 0x18);
|
||||
assert_eq!(®s.tsd[3] as *const _ as usize - base, 0x1C);
|
||||
assert_eq!(®s.tsad[0] as *const _ as usize - base, 0x20);
|
||||
assert_eq!(®s.tsad[1] as *const _ as usize - base, 0x24);
|
||||
assert_eq!(®s.tsad[2] as *const _ as usize - base, 0x28);
|
||||
assert_eq!(®s.tsad[3] as *const _ as usize - base, 0x2C);
|
||||
assert_eq!(®s.rbstart as *const _ as usize - base, 0x30);
|
||||
assert_eq!(®s.erbcr as *const _ as usize - base, 0x34);
|
||||
assert_eq!(®s.ersr as *const _ as usize - base, 0x36);
|
||||
assert_eq!(®s.cr as *const _ as usize - base, 0x37);
|
||||
assert_eq!(®s.capr as *const _ as usize - base, 0x38);
|
||||
assert_eq!(®s.cbr as *const _ as usize - base, 0x3A);
|
||||
assert_eq!(®s.imr as *const _ as usize - base, 0x3C);
|
||||
assert_eq!(®s.isr as *const _ as usize - base, 0x3E);
|
||||
assert_eq!(®s.tcr as *const _ as usize - base, 0x40);
|
||||
assert_eq!(®s.rcr as *const _ as usize - base, 0x44);
|
||||
assert_eq!(®s.tctr as *const _ as usize - base, 0x48);
|
||||
assert_eq!(®s.mpc as *const _ as usize - base, 0x4C);
|
||||
assert_eq!(®s.cr_9346 as *const _ as usize - base, 0x50);
|
||||
assert_eq!(®s.config0 as *const _ as usize - base, 0x51);
|
||||
assert_eq!(®s.config1 as *const _ as usize - base, 0x52);
|
||||
assert_eq!(®s.rsvd_53 as *const _ as usize - base, 0x53);
|
||||
assert_eq!(®s.timer_int as *const _ as usize - base, 0x54);
|
||||
assert_eq!(®s.msr as *const _ as usize - base, 0x58);
|
||||
assert_eq!(®s.config2 as *const _ as usize - base, 0x59);
|
||||
assert_eq!(®s.config3 as *const _ as usize - base, 0x5A);
|
||||
assert_eq!(®s.rsvd_5b as *const _ as usize - base, 0x5B);
|
||||
assert_eq!(®s.mulint as *const _ as usize - base, 0x5C);
|
||||
assert_eq!(®s.rerid as *const _ as usize - base, 0x5E);
|
||||
assert_eq!(®s.rsvd_5f as *const _ as usize - base, 0x5F);
|
||||
assert_eq!(®s.tsts as *const _ as usize - base, 0x60);
|
||||
|
||||
regs
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Rtl8139 {
|
||||
regs: &'static mut Regs,
|
||||
receive_buffer: Dma<[Mmio<u8>; RX_BUFFER_SIZE + 16]>,
|
||||
receive_i: usize,
|
||||
transmit_buffer: [Dma<[Mmio<u8>; 1792]>; 4],
|
||||
transmit_i: usize,
|
||||
mac_address: [u8; 6],
|
||||
}
|
||||
|
||||
impl NetworkAdapter for Rtl8139 {
|
||||
fn mac_address(&mut self) -> [u8; 6] {
|
||||
self.mac_address
|
||||
}
|
||||
|
||||
fn available_for_read(&mut self) -> usize {
|
||||
self.next_read()
|
||||
}
|
||||
|
||||
fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
|
||||
if !self.regs.cr.readf(CR_BUFE) {
|
||||
let rxsts = (self.rx(0) as u16) | (self.rx(1) as u16) << 8;
|
||||
|
||||
let size_with_crc = (self.rx(2) as usize) | (self.rx(3) as usize) << 8;
|
||||
|
||||
let res = if (rxsts & RXSTS_ROK) == RXSTS_ROK {
|
||||
let mut i = 0;
|
||||
while i < buf.len() && i < size_with_crc.saturating_sub(4) {
|
||||
buf[i] = self.rx(4 + i as u16);
|
||||
i += 1;
|
||||
}
|
||||
Ok(Some(i))
|
||||
} else {
|
||||
//TODO: better error types
|
||||
log::error!("invalid receive status 0x{:X}", rxsts);
|
||||
Err(Error::new(EIO))
|
||||
};
|
||||
|
||||
self.receive_i =
|
||||
(self.receive_i + 4 + size_with_crc).next_multiple_of(4) % RX_BUFFER_SIZE;
|
||||
let capr = self.receive_i.wrapping_sub(16) as u16;
|
||||
self.regs.capr.write(capr);
|
||||
|
||||
res
|
||||
} else {
|
||||
Ok(None)
|
||||
}
|
||||
}
|
||||
|
||||
fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
|
||||
loop {
|
||||
if self.transmit_i >= 4 {
|
||||
self.transmit_i = 0;
|
||||
}
|
||||
|
||||
if self.regs.tsd[self.transmit_i].readf(TSD_OWN) {
|
||||
let data = &mut self.transmit_buffer[self.transmit_i];
|
||||
|
||||
if buf.len() > data.len() {
|
||||
return Err(Error::new(EMSGSIZE));
|
||||
}
|
||||
|
||||
let mut i = 0;
|
||||
while i < buf.len() && i < data.len() {
|
||||
data[i].write(buf[i]);
|
||||
i += 1;
|
||||
}
|
||||
|
||||
self.regs.tsad[self.transmit_i].write(data.physical() as u32);
|
||||
assert_eq!(i as u32, i as u32 & TSD_SIZE_MASK);
|
||||
self.regs.tsd[self.transmit_i].write(i as u32 & TSD_SIZE_MASK);
|
||||
|
||||
//TODO: wait for TSD_TOK or error
|
||||
|
||||
self.transmit_i += 1;
|
||||
|
||||
return Ok(i);
|
||||
}
|
||||
|
||||
std::hint::spin_loop();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Rtl8139 {
|
||||
pub unsafe fn new(base: usize) -> Result<Self> {
|
||||
let regs = Regs::from_base(base);
|
||||
|
||||
let mut module = Rtl8139 {
|
||||
regs,
|
||||
//TODO: limit to 32-bit
|
||||
receive_buffer: Dma::zeroed().map(|dma| dma.assume_init())?,
|
||||
receive_i: 0,
|
||||
//TODO: limit to 32-bit
|
||||
transmit_buffer: (0..4)
|
||||
.map(|_| Ok(Dma::zeroed()?.assume_init()))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()),
|
||||
transmit_i: 0,
|
||||
mac_address: [0; 6],
|
||||
};
|
||||
|
||||
module.init()?;
|
||||
|
||||
Ok(module)
|
||||
}
|
||||
|
||||
pub unsafe fn irq(&mut self) -> bool {
|
||||
// Read and then clear the ISR
|
||||
let isr = self.regs.isr.read();
|
||||
self.regs.isr.write(isr);
|
||||
let imr = self.regs.imr.read();
|
||||
(isr & imr) != 0
|
||||
}
|
||||
|
||||
fn rx(&self, offset: u16) -> u8 {
|
||||
let index = (self.receive_i + offset as usize) % RX_BUFFER_SIZE;
|
||||
self.receive_buffer[index].read()
|
||||
}
|
||||
|
||||
pub fn next_read(&self) -> usize {
|
||||
if !self.regs.cr.readf(CR_BUFE) {
|
||||
let rxsts = (self.rx(0) as u16) | (self.rx(1) as u16) << 8;
|
||||
|
||||
let size_with_crc = (self.rx(2) as usize) | (self.rx(3) as usize) << 8;
|
||||
|
||||
if (rxsts & RXSTS_ROK) == RXSTS_ROK {
|
||||
size_with_crc.saturating_sub(4)
|
||||
} else {
|
||||
0
|
||||
}
|
||||
} else {
|
||||
0
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(&mut self) -> Result<()> {
|
||||
let mac_low = self.regs.mac[0].read();
|
||||
let mac_high = self.regs.mac[1].read();
|
||||
let mac = [
|
||||
mac_low as u8,
|
||||
(mac_low >> 8) as u8,
|
||||
(mac_low >> 16) as u8,
|
||||
(mac_low >> 24) as u8,
|
||||
mac_high as u8,
|
||||
(mac_high >> 8) as u8,
|
||||
];
|
||||
log::debug!(
|
||||
"MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
|
||||
mac[0],
|
||||
mac[1],
|
||||
mac[2],
|
||||
mac[3],
|
||||
mac[4],
|
||||
mac[5]
|
||||
);
|
||||
self.mac_address = mac;
|
||||
|
||||
// Reset - this will disable tx and rx, reinitialize FIFOs, and set the system buffer pointer to the initial value
|
||||
{
|
||||
log::debug!("Reset");
|
||||
let timeout = Timeout::from_secs(1);
|
||||
self.regs.cr.writef(CR_RST, true);
|
||||
while self.regs.cr.readf(CR_RST) {
|
||||
timeout.run().map_err(|()| Error::new(EIO))?;
|
||||
}
|
||||
}
|
||||
|
||||
// Set up rx buffer
|
||||
log::debug!("Receive buffer");
|
||||
self.regs
|
||||
.rbstart
|
||||
.write(self.receive_buffer.physical() as u32);
|
||||
|
||||
log::debug!("Interrupt mask");
|
||||
self.regs.imr.write(IMR_TOK | IMR_ROK);
|
||||
|
||||
log::debug!("Receive configuration");
|
||||
self.regs
|
||||
.rcr
|
||||
.write(RCR_RBLEN_64K | RCR_AB | RCR_AM | RCR_APM | RCR_AAP);
|
||||
|
||||
log::debug!("Enable RX and TX");
|
||||
self.regs.cr.writef(CR_RE | CR_TE, true);
|
||||
|
||||
log::debug!("Complete!");
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
use std::io::{Read, Write};
|
||||
use std::os::unix::io::AsRawFd;
|
||||
|
||||
use driver_network::NetworkScheme;
|
||||
use event::{user_data, EventQueue};
|
||||
use pcid_interface::irq_helpers::pci_allocate_interrupt_vector;
|
||||
use pcid_interface::PciFunctionHandle;
|
||||
|
||||
pub mod device;
|
||||
|
||||
use std::ops::{Add, Div, Rem};
|
||||
pub fn div_round_up<T>(a: T, b: T) -> T
|
||||
where
|
||||
T: Add<Output = T> + Div<Output = T> + Rem<Output = T> + PartialEq + From<u8> + Copy,
|
||||
{
|
||||
if a % b != T::from(0u8) {
|
||||
a / b + T::from(1u8)
|
||||
} else {
|
||||
a / b
|
||||
}
|
||||
}
|
||||
|
||||
fn map_bar(pcid_handle: &mut PciFunctionHandle) -> *mut u8 {
|
||||
let config = pcid_handle.config();
|
||||
|
||||
// RTL8139 uses BAR2, RTL8169 uses BAR1, search in that order
|
||||
for &barnum in &[2, 1] {
|
||||
match config.func.bars[usize::from(barnum)] {
|
||||
pcid_interface::PciBar::Memory32 { .. } | pcid_interface::PciBar::Memory64 { .. } => unsafe {
|
||||
return pcid_handle.map_bar(barnum).ptr.as_ptr();
|
||||
},
|
||||
other => log::warn!("BAR {} is {:?} instead of memory BAR", barnum, other),
|
||||
}
|
||||
}
|
||||
panic!("rtl8139d: failed to find BAR");
|
||||
}
|
||||
|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon);
|
||||
}
|
||||
|
||||
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
|
||||
let pci_config = pcid_handle.config();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_rtl8139");
|
||||
|
||||
common::setup_logging(
|
||||
"net",
|
||||
"pci",
|
||||
&name,
|
||||
common::output_level(),
|
||||
common::file_level(),
|
||||
);
|
||||
|
||||
log::info!(" + RTL8139 {}", pci_config.func.display());
|
||||
|
||||
let bar = map_bar(&mut pcid_handle);
|
||||
|
||||
let irq_file = pci_allocate_interrupt_vector(&mut pcid_handle, "rtl8139d");
|
||||
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || unsafe {
|
||||
device::Rtl8139::new(bar as usize).expect("rtl8139d: failed to allocate device")
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
user_data! {
|
||||
enum Source {
|
||||
Irq,
|
||||
Scheme,
|
||||
}
|
||||
}
|
||||
|
||||
let event_queue = EventQueue::<Source>::new().expect("rtl8139d: Could not create event queue.");
|
||||
event_queue
|
||||
.subscribe(
|
||||
irq_file.irq_handle().as_raw_fd() as usize,
|
||||
Source::Irq,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
event_queue
|
||||
.subscribe(
|
||||
scheme.event_handle().raw(),
|
||||
Source::Scheme,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
libredox::call::setrens(0, 0).expect("rtl8139d: failed to enter null namespace");
|
||||
|
||||
scheme.tick().unwrap();
|
||||
|
||||
for event in event_queue.map(|e| e.expect("rtl8139d: failed to get next event")) {
|
||||
match event.user_data {
|
||||
Source::Irq => {
|
||||
let mut irq = [0; 8];
|
||||
irq_file.irq_handle().read(&mut irq).unwrap();
|
||||
//TODO: This may be causing spurious interrupts
|
||||
if unsafe { scheme.adapter_mut().irq() } {
|
||||
irq_file.irq_handle().write(&mut irq).unwrap();
|
||||
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
Source::Scheme => {
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
unreachable!()
|
||||
}
|
||||
@@ -0,0 +1,20 @@
|
||||
[package]
|
||||
name = "rtl8168d"
|
||||
description = "Realtek 8168 ethernet driver"
|
||||
version = "0.1.0"
|
||||
edition = "2018"
|
||||
|
||||
[dependencies]
|
||||
bitflags.workspace = true
|
||||
libredox.workspace = true
|
||||
log.workspace = true
|
||||
redox_event.workspace = true
|
||||
redox_syscall.workspace = true
|
||||
|
||||
common = { path = "../../common" }
|
||||
daemon = { path = "../../../daemon" }
|
||||
driver-network = { path = "../driver-network" }
|
||||
pcid = { path = "../../pcid" }
|
||||
|
||||
[lints]
|
||||
workspace = true
|
||||
@@ -0,0 +1,5 @@
|
||||
[[drivers]]
|
||||
name = "RTL8168 NIC"
|
||||
class = 0x02
|
||||
ids = { 0x10ec = [0x8168, 0x8169] }
|
||||
command = ["rtl8168d"]
|
||||
@@ -0,0 +1,345 @@
|
||||
use std::convert::TryInto;
|
||||
use std::mem;
|
||||
|
||||
use common::dma::Dma;
|
||||
use common::io::{Io, Mmio, ReadOnly};
|
||||
use common::timeout::Timeout;
|
||||
use driver_network::NetworkAdapter;
|
||||
use syscall::error::{Error, Result, EIO, EMSGSIZE};
|
||||
|
||||
#[repr(C, packed)]
|
||||
struct Regs {
|
||||
mac: [Mmio<u32>; 2],
|
||||
_mar: [Mmio<u32>; 2],
|
||||
_dtccr: [Mmio<u32>; 2],
|
||||
_rsv0: [Mmio<u32>; 2],
|
||||
tnpds: [Mmio<u32>; 2],
|
||||
thpds: [Mmio<u32>; 2],
|
||||
_rsv1: [Mmio<u8>; 7],
|
||||
cmd: Mmio<u8>,
|
||||
tppoll: Mmio<u8>,
|
||||
_rsv2: [Mmio<u8>; 3],
|
||||
imr: Mmio<u16>,
|
||||
isr: Mmio<u16>,
|
||||
tcr: Mmio<u32>,
|
||||
rcr: Mmio<u32>,
|
||||
_tctr: Mmio<u32>,
|
||||
_rsv3: Mmio<u32>,
|
||||
cmd_9346: Mmio<u8>,
|
||||
_config: [Mmio<u8>; 6],
|
||||
_rsv4: Mmio<u8>,
|
||||
timer_int: Mmio<u32>,
|
||||
_rsv5: Mmio<u32>,
|
||||
_phys_ar: Mmio<u32>,
|
||||
_rsv6: [Mmio<u32>; 2],
|
||||
phys_sts: ReadOnly<Mmio<u8>>,
|
||||
_rsv7: [Mmio<u8>; 23],
|
||||
_wakeup: [Mmio<u32>; 16],
|
||||
_crc: [Mmio<u16>; 5],
|
||||
_rsv8: [Mmio<u8>; 12],
|
||||
rms: Mmio<u16>,
|
||||
_rsv9: Mmio<u32>,
|
||||
_c_plus_cr: Mmio<u16>,
|
||||
_rsv10: Mmio<u16>,
|
||||
rdsar: [Mmio<u32>; 2],
|
||||
mtps: Mmio<u8>,
|
||||
_rsv11: [Mmio<u8>; 19],
|
||||
}
|
||||
|
||||
const OWN: u32 = 1 << 31;
|
||||
const EOR: u32 = 1 << 30;
|
||||
const FS: u32 = 1 << 29;
|
||||
const LS: u32 = 1 << 28;
|
||||
|
||||
#[repr(C, packed)]
|
||||
struct Rd {
|
||||
ctrl: Mmio<u32>,
|
||||
_vlan: Mmio<u32>,
|
||||
buffer_low: Mmio<u32>,
|
||||
buffer_high: Mmio<u32>,
|
||||
}
|
||||
|
||||
#[repr(C, packed)]
|
||||
struct Td {
|
||||
ctrl: Mmio<u32>,
|
||||
_vlan: Mmio<u32>,
|
||||
buffer_low: Mmio<u32>,
|
||||
buffer_high: Mmio<u32>,
|
||||
}
|
||||
|
||||
pub struct Rtl8168 {
|
||||
regs: &'static mut Regs,
|
||||
receive_buffer: [Dma<[Mmio<u8>; 0x1FF8]>; 64],
|
||||
receive_ring: Dma<[Rd; 64]>,
|
||||
receive_i: usize,
|
||||
transmit_buffer: [Dma<[Mmio<u8>; 7552]>; 16],
|
||||
transmit_ring: Dma<[Td; 16]>,
|
||||
transmit_i: usize,
|
||||
transmit_buffer_h: [Dma<[Mmio<u8>; 7552]>; 1],
|
||||
transmit_ring_h: Dma<[Td; 1]>,
|
||||
mac_address: [u8; 6],
|
||||
}
|
||||
|
||||
impl NetworkAdapter for Rtl8168 {
|
||||
fn mac_address(&mut self) -> [u8; 6] {
|
||||
self.mac_address
|
||||
}
|
||||
|
||||
fn available_for_read(&mut self) -> usize {
|
||||
self.next_read()
|
||||
}
|
||||
|
||||
fn read_packet(&mut self, buf: &mut [u8]) -> Result<Option<usize>> {
|
||||
if self.receive_i >= self.receive_ring.len() {
|
||||
self.receive_i = 0;
|
||||
}
|
||||
|
||||
let rd = &mut self.receive_ring[self.receive_i];
|
||||
if !rd.ctrl.readf(OWN) {
|
||||
let rd_len = rd.ctrl.read() & 0x3FFF;
|
||||
|
||||
let data = &self.receive_buffer[self.receive_i];
|
||||
|
||||
let mut i = 0;
|
||||
while i < buf.len() && i < rd_len as usize {
|
||||
buf[i] = data[i].read();
|
||||
i += 1;
|
||||
}
|
||||
|
||||
let eor = rd.ctrl.read() & EOR;
|
||||
rd.ctrl.write(OWN | eor | data.len() as u32);
|
||||
|
||||
self.receive_i += 1;
|
||||
|
||||
Ok(Some(i))
|
||||
} else {
|
||||
Ok(None)
|
||||
}
|
||||
}
|
||||
|
||||
fn write_packet(&mut self, buf: &[u8]) -> Result<usize> {
|
||||
loop {
|
||||
if self.transmit_i >= self.transmit_ring.len() {
|
||||
self.transmit_i = 0;
|
||||
}
|
||||
|
||||
let td = &mut self.transmit_ring[self.transmit_i];
|
||||
if !td.ctrl.readf(OWN) {
|
||||
let data = &mut self.transmit_buffer[self.transmit_i];
|
||||
|
||||
if buf.len() > data.len() {
|
||||
return Err(Error::new(EMSGSIZE));
|
||||
}
|
||||
|
||||
let mut i = 0;
|
||||
while i < buf.len() && i < data.len() {
|
||||
data[i].write(buf[i]);
|
||||
i += 1;
|
||||
}
|
||||
|
||||
let eor = td.ctrl.read() & EOR;
|
||||
td.ctrl.write(OWN | eor | FS | LS | i as u32);
|
||||
|
||||
self.regs.tppoll.writef(1 << 6, true); //Notify of normal priority packet
|
||||
|
||||
while self.regs.tppoll.readf(1 << 6) {
|
||||
std::hint::spin_loop();
|
||||
}
|
||||
|
||||
self.transmit_i += 1;
|
||||
|
||||
return Ok(i);
|
||||
}
|
||||
|
||||
std::hint::spin_loop();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Rtl8168 {
|
||||
pub unsafe fn new(base: usize) -> Result<Self> {
|
||||
assert_eq!(mem::size_of::<Regs>(), 256);
|
||||
|
||||
let regs = &mut *(base as *mut Regs);
|
||||
assert_eq!(®s.tnpds as *const _ as usize - base, 0x20);
|
||||
assert_eq!(®s.cmd as *const _ as usize - base, 0x37);
|
||||
assert_eq!(®s.tcr as *const _ as usize - base, 0x40);
|
||||
assert_eq!(®s.rcr as *const _ as usize - base, 0x44);
|
||||
assert_eq!(®s.cmd_9346 as *const _ as usize - base, 0x50);
|
||||
assert_eq!(®s.phys_sts as *const _ as usize - base, 0x6C);
|
||||
assert_eq!(®s.rms as *const _ as usize - base, 0xDA);
|
||||
assert_eq!(®s.rdsar as *const _ as usize - base, 0xE4);
|
||||
assert_eq!(®s.mtps as *const _ as usize - base, 0xEC);
|
||||
|
||||
let mut module = Rtl8168 {
|
||||
regs,
|
||||
receive_buffer: (0..64)
|
||||
.map(|_| Ok(Dma::zeroed()?.assume_init()))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()),
|
||||
|
||||
receive_ring: Dma::zeroed()?.assume_init(),
|
||||
receive_i: 0,
|
||||
transmit_buffer: (0..16)
|
||||
.map(|_| Ok(Dma::zeroed()?.assume_init()))
|
||||
.collect::<Result<Vec<_>>>()?
|
||||
.try_into()
|
||||
.unwrap_or_else(|_| unreachable!()),
|
||||
transmit_ring: Dma::zeroed()?.assume_init(),
|
||||
transmit_i: 0,
|
||||
transmit_buffer_h: [Dma::zeroed()?.assume_init()],
|
||||
transmit_ring_h: Dma::zeroed()?.assume_init(),
|
||||
mac_address: [0; 6],
|
||||
};
|
||||
|
||||
module.init()?;
|
||||
|
||||
Ok(module)
|
||||
}
|
||||
|
||||
pub unsafe fn irq(&mut self) -> bool {
|
||||
// Read and then clear the ISR
|
||||
let isr = self.regs.isr.read();
|
||||
self.regs.isr.write(isr);
|
||||
let imr = self.regs.imr.read();
|
||||
(isr & imr) != 0
|
||||
}
|
||||
|
||||
pub fn next_read(&self) -> usize {
|
||||
let mut receive_i = self.receive_i;
|
||||
if receive_i >= self.receive_ring.len() {
|
||||
receive_i = 0;
|
||||
}
|
||||
|
||||
let rd = &self.receive_ring[receive_i];
|
||||
if !rd.ctrl.readf(OWN) {
|
||||
(rd.ctrl.read() & 0x3FFF) as usize
|
||||
} else {
|
||||
0
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(&mut self) -> Result<()> {
|
||||
let mac_low = self.regs.mac[0].read();
|
||||
let mac_high = self.regs.mac[1].read();
|
||||
let mac = [
|
||||
mac_low as u8,
|
||||
(mac_low >> 8) as u8,
|
||||
(mac_low >> 16) as u8,
|
||||
(mac_low >> 24) as u8,
|
||||
mac_high as u8,
|
||||
(mac_high >> 8) as u8,
|
||||
];
|
||||
log::debug!(
|
||||
"MAC: {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
|
||||
mac[0],
|
||||
mac[1],
|
||||
mac[2],
|
||||
mac[3],
|
||||
mac[4],
|
||||
mac[5]
|
||||
);
|
||||
self.mac_address = mac;
|
||||
|
||||
// Reset - this will disable tx and rx, reinitialize FIFOs, and set the system buffer pointer to the initial value
|
||||
{
|
||||
log::debug!("Reset");
|
||||
let timeout = Timeout::from_secs(1);
|
||||
self.regs.cmd.writef(1 << 4, true);
|
||||
while self.regs.cmd.readf(1 << 4) {
|
||||
timeout.run().map_err(|()| Error::new(EIO))?;
|
||||
}
|
||||
}
|
||||
|
||||
// Set up rx buffers
|
||||
log::debug!("Receive buffers");
|
||||
for i in 0..self.receive_ring.len() {
|
||||
let rd = &mut self.receive_ring[i];
|
||||
let data = &mut self.receive_buffer[i];
|
||||
rd.buffer_low.write(data.physical() as u32);
|
||||
rd.buffer_high.write((data.physical() as u64 >> 32) as u32);
|
||||
rd.ctrl.write(OWN | data.len() as u32);
|
||||
}
|
||||
if let Some(rd) = self.receive_ring.last_mut() {
|
||||
rd.ctrl.writef(EOR, true);
|
||||
}
|
||||
|
||||
// Set up normal priority tx buffers
|
||||
log::debug!("Transmit buffers (normal priority)");
|
||||
for i in 0..self.transmit_ring.len() {
|
||||
self.transmit_ring[i]
|
||||
.buffer_low
|
||||
.write(self.transmit_buffer[i].physical() as u32);
|
||||
self.transmit_ring[i]
|
||||
.buffer_high
|
||||
.write((self.transmit_buffer[i].physical() as u64 >> 32) as u32);
|
||||
}
|
||||
if let Some(td) = self.transmit_ring.last_mut() {
|
||||
td.ctrl.writef(EOR, true);
|
||||
}
|
||||
|
||||
// Set up high priority tx buffers
|
||||
log::debug!("Transmit buffers (high priority)");
|
||||
for i in 0..self.transmit_ring_h.len() {
|
||||
self.transmit_ring_h[i]
|
||||
.buffer_low
|
||||
.write(self.transmit_buffer_h[i].physical() as u32);
|
||||
self.transmit_ring_h[i]
|
||||
.buffer_high
|
||||
.write((self.transmit_buffer_h[i].physical() as u64 >> 32) as u32);
|
||||
}
|
||||
if let Some(td) = self.transmit_ring_h.last_mut() {
|
||||
td.ctrl.writef(EOR, true);
|
||||
}
|
||||
|
||||
log::debug!("Set config");
|
||||
// Unlock config
|
||||
self.regs.cmd_9346.write(1 << 7 | 1 << 6);
|
||||
|
||||
// Enable rx (bit 3) and tx (bit 2)
|
||||
self.regs.cmd.writef(1 << 3 | 1 << 2, true);
|
||||
|
||||
// Max RX packet size
|
||||
self.regs.rms.write(0x1FF8);
|
||||
|
||||
// Max TX packet size
|
||||
self.regs.mtps.write(0x3B);
|
||||
|
||||
// Set tx low priority buffer address
|
||||
self.regs.tnpds[0].write(self.transmit_ring.physical() as u32);
|
||||
self.regs.tnpds[1].write(((self.transmit_ring.physical() as u64) >> 32) as u32);
|
||||
|
||||
// Set tx high priority buffer address
|
||||
self.regs.thpds[0].write(self.transmit_ring_h.physical() as u32);
|
||||
self.regs.thpds[1].write(((self.transmit_ring_h.physical() as u64) >> 32) as u32);
|
||||
|
||||
// Set rx buffer address
|
||||
self.regs.rdsar[0].write(self.receive_ring.physical() as u32);
|
||||
self.regs.rdsar[1].write(((self.receive_ring.physical() as u64) >> 32) as u32);
|
||||
|
||||
// Disable timer interrupt
|
||||
self.regs.timer_int.write(0);
|
||||
|
||||
//Clear ISR
|
||||
let isr = self.regs.isr.read();
|
||||
self.regs.isr.write(isr);
|
||||
|
||||
// Interrupt on tx error (bit 3), tx ok (bit 2), rx error(bit 1), and rx ok (bit 0)
|
||||
self.regs.imr.write(
|
||||
1 << 15 | 1 << 14 | 1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1,
|
||||
);
|
||||
|
||||
// Set TX config
|
||||
self.regs.tcr.write(0b11 << 24 | 0b111 << 8);
|
||||
|
||||
// Set RX config - Accept broadcast (bit 3), multicast (bit 2), and unicast (bit 1)
|
||||
self.regs.rcr.write(0xE70E);
|
||||
|
||||
// Lock config
|
||||
self.regs.cmd_9346.write(0);
|
||||
|
||||
log::debug!("Complete!");
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
use std::io::{Read, Write};
|
||||
use std::os::unix::io::AsRawFd;
|
||||
|
||||
use driver_network::NetworkScheme;
|
||||
use event::{user_data, EventQueue};
|
||||
use pcid_interface::irq_helpers::pci_allocate_interrupt_vector;
|
||||
use pcid_interface::PciFunctionHandle;
|
||||
|
||||
pub mod device;
|
||||
|
||||
use std::ops::{Add, Div, Rem};
|
||||
pub fn div_round_up<T>(a: T, b: T) -> T
|
||||
where
|
||||
T: Add<Output = T> + Div<Output = T> + Rem<Output = T> + PartialEq + From<u8> + Copy,
|
||||
{
|
||||
if a % b != T::from(0u8) {
|
||||
a / b + T::from(1u8)
|
||||
} else {
|
||||
a / b
|
||||
}
|
||||
}
|
||||
|
||||
fn map_bar(pcid_handle: &mut PciFunctionHandle) -> *mut u8 {
|
||||
let config = pcid_handle.config();
|
||||
|
||||
// RTL8168 uses BAR2, RTL8169 uses BAR1, search in that order
|
||||
for &barnum in &[2, 1] {
|
||||
match config.func.bars[usize::from(barnum)] {
|
||||
pcid_interface::PciBar::Memory32 { .. } | pcid_interface::PciBar::Memory64 { .. } => unsafe {
|
||||
return pcid_handle.map_bar(barnum).ptr.as_ptr();
|
||||
},
|
||||
other => log::warn!("BAR {} is {:?} instead of memory BAR", barnum, other),
|
||||
}
|
||||
}
|
||||
panic!("rtl8168d: failed to find BAR");
|
||||
}
|
||||
|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon);
|
||||
}
|
||||
|
||||
fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
|
||||
let pci_config = pcid_handle.config();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_rtl8168");
|
||||
|
||||
common::setup_logging(
|
||||
"net",
|
||||
"pci",
|
||||
&name,
|
||||
common::output_level(),
|
||||
common::file_level(),
|
||||
);
|
||||
|
||||
log::info!("RTL8168 {}", pci_config.func.display());
|
||||
|
||||
let bar = map_bar(&mut pcid_handle);
|
||||
|
||||
let irq_file = pci_allocate_interrupt_vector(&mut pcid_handle, "rtl8168d");
|
||||
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || unsafe {
|
||||
device::Rtl8168::new(bar as usize).expect("rtl8168d: failed to allocate device")
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
user_data! {
|
||||
enum Source {
|
||||
Irq,
|
||||
Scheme,
|
||||
}
|
||||
}
|
||||
|
||||
let event_queue = EventQueue::<Source>::new().expect("rtl8168d: Could not create event queue.");
|
||||
event_queue
|
||||
.subscribe(
|
||||
irq_file.irq_handle().as_raw_fd() as usize,
|
||||
Source::Irq,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
event_queue
|
||||
.subscribe(
|
||||
scheme.event_handle().raw(),
|
||||
Source::Scheme,
|
||||
event::EventFlags::READ,
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
libredox::call::setrens(0, 0).expect("rtl8168d: failed to enter null namespace");
|
||||
|
||||
scheme.tick().unwrap();
|
||||
|
||||
for event in event_queue.map(|e| e.expect("rtl8168d: failed to get next event")) {
|
||||
match event.user_data {
|
||||
Source::Irq => {
|
||||
let mut irq = [0; 8];
|
||||
irq_file.irq_handle().read(&mut irq).unwrap();
|
||||
//TODO: This may be causing spurious interrupts
|
||||
if unsafe { scheme.adapter_mut().irq() } {
|
||||
irq_file.irq_handle().write(&mut irq).unwrap();
|
||||
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
Source::Scheme => {
|
||||
scheme.tick().unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
unreachable!()
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
[package]
|
||||
name = "virtio-netd"
|
||||
description = "VirtIO network driver"
|
||||
version = "0.1.0"
|
||||
edition = "2021"
|
||||
|
||||
[dependencies]
|
||||
log.workspace = true
|
||||
static_assertions.workspace = true
|
||||
futures = { version = "0.3.28", features = ["executor"] }
|
||||
|
||||
virtio-core = { path = "../../virtio-core" }
|
||||
pcid = { path = "../../pcid" }
|
||||
common = { path = "../../common" }
|
||||
daemon = { path = "../../../daemon" }
|
||||
driver-network = { path = "../driver-network" }
|
||||
|
||||
redox_syscall.workspace = true
|
||||
libredox.workspace = true
|
||||
|
||||
[lints]
|
||||
workspace = true
|
||||
@@ -0,0 +1,6 @@
|
||||
[[drivers]]
|
||||
name = "virtio-net"
|
||||
class = 0x02
|
||||
vendor = 0x1AF4
|
||||
device = 0x1000
|
||||
command = ["virtio-netd"]
|
||||
@@ -0,0 +1,137 @@
|
||||
mod scheme;
|
||||
|
||||
use std::fs::File;
|
||||
use std::io::{Read, Write};
|
||||
use std::mem;
|
||||
|
||||
use driver_network::NetworkScheme;
|
||||
use pcid_interface::PciFunctionHandle;
|
||||
|
||||
use scheme::VirtioNet;
|
||||
|
||||
pub const VIRTIO_NET_F_MAC: u32 = 5;
|
||||
|
||||
#[derive(Debug)]
|
||||
#[repr(C)]
|
||||
pub struct VirtHeader {
|
||||
pub flags: u8,
|
||||
pub gso_type: u8,
|
||||
pub hdr_len: u16,
|
||||
pub gso_size: u16,
|
||||
pub csum_start: u16,
|
||||
pub csum_offset: u16,
|
||||
pub num_buffers: u16,
|
||||
}
|
||||
|
||||
static_assertions::const_assert_eq!(core::mem::size_of::<VirtHeader>(), 12);
|
||||
|
||||
const MAX_BUFFER_LEN: usize = 65535;
|
||||
fn main() {
|
||||
pcid_interface::pci_daemon(daemon_runner);
|
||||
}
|
||||
|
||||
fn daemon_runner(redox_daemon: daemon::Daemon, pcid_handle: PciFunctionHandle) -> ! {
|
||||
daemon(redox_daemon, pcid_handle).unwrap();
|
||||
unreachable!();
|
||||
}
|
||||
|
||||
fn daemon(
|
||||
daemon: daemon::Daemon,
|
||||
mut pcid_handle: PciFunctionHandle,
|
||||
) -> Result<(), Box<dyn std::error::Error>> {
|
||||
common::setup_logging(
|
||||
"net",
|
||||
"pci",
|
||||
"virtio-netd",
|
||||
common::output_level(),
|
||||
common::file_level(),
|
||||
);
|
||||
|
||||
// Double check that we have the right device.
|
||||
//
|
||||
// 0x1000 - virtio-net
|
||||
let pci_config = pcid_handle.config();
|
||||
|
||||
assert_eq!(pci_config.func.full_device_id.device_id, 0x1000);
|
||||
log::info!("virtio-net: initiating startup sequence :^)");
|
||||
|
||||
let device = virtio_core::probe_device(&mut pcid_handle)?;
|
||||
let device_space = device.device_space;
|
||||
|
||||
// Negotiate device features:
|
||||
let mac_address = if device.transport.check_device_feature(VIRTIO_NET_F_MAC) {
|
||||
let mac = unsafe {
|
||||
[
|
||||
core::ptr::read_volatile(device_space.add(0)),
|
||||
core::ptr::read_volatile(device_space.add(1)),
|
||||
core::ptr::read_volatile(device_space.add(2)),
|
||||
core::ptr::read_volatile(device_space.add(3)),
|
||||
core::ptr::read_volatile(device_space.add(4)),
|
||||
core::ptr::read_volatile(device_space.add(5)),
|
||||
]
|
||||
};
|
||||
|
||||
log::info!(
|
||||
"virtio-net: device MAC is {:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}:{:>02X}",
|
||||
mac[0],
|
||||
mac[1],
|
||||
mac[2],
|
||||
mac[3],
|
||||
mac[4],
|
||||
mac[5]
|
||||
);
|
||||
|
||||
device.transport.ack_driver_feature(VIRTIO_NET_F_MAC);
|
||||
mac
|
||||
} else {
|
||||
unimplemented!()
|
||||
};
|
||||
|
||||
device.transport.finalize_features();
|
||||
|
||||
// Allocate the recieve and transmit queues:
|
||||
//
|
||||
// > Empty buffers are placed in one virtqueue for receiving
|
||||
// > packets, and outgoing packets are enqueued into another
|
||||
// > for transmission in that order.
|
||||
//
|
||||
// TODO(andypython): Should we use the same IRQ vector for both?
|
||||
let rx_queue = device
|
||||
.transport
|
||||
.setup_queue(virtio_core::MSIX_PRIMARY_VECTOR, &device.irq_handle)?;
|
||||
|
||||
let tx_queue = device
|
||||
.transport
|
||||
.setup_queue(virtio_core::MSIX_PRIMARY_VECTOR, &device.irq_handle)?;
|
||||
|
||||
device.transport.run_device();
|
||||
|
||||
let mut name = pci_config.func.name();
|
||||
name.push_str("_virtio_net");
|
||||
|
||||
let device = VirtioNet::new(mac_address, rx_queue, tx_queue);
|
||||
let mut scheme = NetworkScheme::new(
|
||||
move || {
|
||||
//TODO: do device init in this function to prevent hangs
|
||||
device
|
||||
},
|
||||
daemon,
|
||||
format!("network.{name}"),
|
||||
);
|
||||
|
||||
let mut event_queue = File::open("/scheme/event")?;
|
||||
event_queue.write(&syscall::Event {
|
||||
id: scheme.event_handle().raw(),
|
||||
flags: syscall::EVENT_READ,
|
||||
data: 0,
|
||||
})?;
|
||||
|
||||
libredox::call::setrens(0, 0).expect("virtio-netd: failed to enter null namespace");
|
||||
|
||||
scheme.tick()?;
|
||||
|
||||
loop {
|
||||
event_queue.read(&mut [0; mem::size_of::<syscall::Event>()])?; // Wait for event
|
||||
scheme.tick()?;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
use std::sync::Arc;
|
||||
|
||||
use driver_network::NetworkAdapter;
|
||||
|
||||
use common::dma::Dma;
|
||||
|
||||
use virtio_core::spec::{Buffer, ChainBuilder, DescriptorFlags};
|
||||
use virtio_core::transport::Queue;
|
||||
|
||||
use crate::{VirtHeader, MAX_BUFFER_LEN};
|
||||
|
||||
pub struct VirtioNet<'a> {
|
||||
mac_address: [u8; 6],
|
||||
|
||||
/// Reciever Queue.
|
||||
rx: Arc<Queue<'a>>,
|
||||
rx_buffers: Vec<Dma<[u8]>>,
|
||||
|
||||
/// Transmiter Queue.
|
||||
tx: Arc<Queue<'a>>,
|
||||
|
||||
recv_head: u16,
|
||||
}
|
||||
|
||||
impl<'a> VirtioNet<'a> {
|
||||
pub fn new(mac_address: [u8; 6], rx: Arc<Queue<'a>>, tx: Arc<Queue<'a>>) -> Self {
|
||||
// Populate all of the `rx_queue` with buffers to maximize performence.
|
||||
let mut rx_buffers = vec![];
|
||||
for i in 0..(rx.descriptor_len() as usize) {
|
||||
rx_buffers.push(unsafe {
|
||||
Dma::<[u8]>::zeroed_slice(MAX_BUFFER_LEN)
|
||||
.unwrap()
|
||||
.assume_init()
|
||||
});
|
||||
|
||||
let chain = ChainBuilder::new()
|
||||
.chain(Buffer::new_unsized(&rx_buffers[i]).flags(DescriptorFlags::WRITE_ONLY))
|
||||
.build();
|
||||
|
||||
let _ = rx.send(chain);
|
||||
}
|
||||
|
||||
Self {
|
||||
mac_address,
|
||||
|
||||
rx,
|
||||
rx_buffers,
|
||||
tx,
|
||||
|
||||
recv_head: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Returns the number of bytes read. Returns `0` if the operation would block.
|
||||
fn try_recv(&mut self, target: &mut [u8]) -> usize {
|
||||
let header_size = core::mem::size_of::<VirtHeader>();
|
||||
|
||||
if self.recv_head == self.rx.used.head_index() {
|
||||
// The read would block.
|
||||
return 0;
|
||||
}
|
||||
|
||||
let idx = self.rx.used.head_index() as usize;
|
||||
let element = self.rx.used.get_element_at(idx - 1);
|
||||
|
||||
let descriptor_idx = element.table_index.get();
|
||||
let payload_size = element.written.get() as usize - header_size;
|
||||
|
||||
// XXX: The header and packet are added as one output descriptor to the transmit queue,
|
||||
// and the device is notified of the new entry (see 5.1.5 Device Initialization).
|
||||
let buffer = &self.rx_buffers[descriptor_idx as usize];
|
||||
// TODO: Check the header.
|
||||
let _header = unsafe { &*(buffer.as_ptr() as *const VirtHeader) };
|
||||
let packet = &buffer[header_size..(header_size + payload_size)];
|
||||
|
||||
// Copy the packet into the buffer.
|
||||
target[..payload_size].copy_from_slice(&packet);
|
||||
|
||||
self.recv_head = self.rx.used.head_index();
|
||||
payload_size
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a> NetworkAdapter for VirtioNet<'a> {
|
||||
fn mac_address(&mut self) -> [u8; 6] {
|
||||
self.mac_address
|
||||
}
|
||||
|
||||
fn available_for_read(&mut self) -> usize {
|
||||
(self.rx.used.head_index() - self.recv_head).into()
|
||||
}
|
||||
|
||||
fn read_packet(&mut self, buf: &mut [u8]) -> syscall::Result<Option<usize>> {
|
||||
let bytes = self.try_recv(buf);
|
||||
|
||||
if bytes != 0 {
|
||||
// We read some bytes.
|
||||
Ok(Some(bytes))
|
||||
} else {
|
||||
Ok(None)
|
||||
}
|
||||
}
|
||||
|
||||
fn write_packet(&mut self, buffer: &[u8]) -> syscall::Result<usize> {
|
||||
let header = unsafe { Dma::<VirtHeader>::zeroed()?.assume_init() };
|
||||
|
||||
let mut payload = unsafe { Dma::<[u8]>::zeroed_slice(buffer.len())?.assume_init() };
|
||||
payload.copy_from_slice(buffer);
|
||||
|
||||
let chain = ChainBuilder::new()
|
||||
.chain(Buffer::new(&header))
|
||||
.chain(Buffer::new_unsized(&payload))
|
||||
.build();
|
||||
|
||||
futures::executor::block_on(self.tx.send(chain));
|
||||
Ok(buffer.len())
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user