diff --git a/src/context/switch.rs b/src/context/switch.rs index 5e20faa11d..d45485848c 100644 --- a/src/context/switch.rs +++ b/src/context/switch.rs @@ -8,7 +8,7 @@ use crate::{ ArcContextLockWriteGuard, Context, ContextLock, }, cpu_set::LogicalCpuId, - cpu_stats, + cpu_stats::{self, CpuState}, percpu::PercpuBlock, sync::{ArcRwLockWriteGuard, CleanLockToken, L4}, }; @@ -236,7 +236,7 @@ pub fn switch(token: &mut CleanLockToken) -> SwitchResult { // Update per-cpu times let percpu_nanos = switch_time.saturating_sub(percpu.switch_internals.switch_time.get()) as u64; let percpu_ms = percpu_nanos / 1_000_000; - percpu.stats.add_time(percpu_ms); + let was_idle = percpu.stats.add_time(percpu_ms) == CpuState::Idle as u8; percpu.switch_internals.switch_time.set(switch_time); // Switch process states, TSS stack pointer, and store new context ID @@ -255,7 +255,9 @@ pub fn switch(token: &mut CleanLockToken) -> SwitchResult { next_context.cpu_id = Some(cpu_id); // Update times - prev_context.cpu_time += switch_time.saturating_sub(prev_context.switch_time); + if !was_idle { + prev_context.cpu_time += switch_time.saturating_sub(prev_context.switch_time); + } next_context.switch_time = switch_time; if next_context.userspace { percpu.stats.set_state(cpu_stats::CpuState::User); diff --git a/src/cpu_stats.rs b/src/cpu_stats.rs index 448e1a8faf..02e029df67 100644 --- a/src/cpu_stats.rs +++ b/src/cpu_stats.rs @@ -78,20 +78,22 @@ impl CpuStats { self.state.store(new_state as u8, Ordering::Relaxed); } - /// Increments time statistics of a CPU + /// Increments time statistics of a CPU, return the state is was accounting to. /// /// Which statistic is incremented depends on the [`State`] of the CPU. /// /// # Parameters /// * `nanos` - Number of nanoseconds to add. #[inline] - pub fn add_time(&self, nanos: u64) { - match self.state.load(Ordering::Relaxed) { + pub fn add_time(&self, nanos: u64) -> u8 { + let state = self.state.load(Ordering::Relaxed); + match state { val if val == CpuState::Idle as u8 => self.idle.fetch_add(nanos, Ordering::Relaxed), val if val == CpuState::User as u8 => self.user.fetch_add(nanos, Ordering::Relaxed), val if val == CpuState::Kernel as u8 => self.kernel.fetch_add(nanos, Ordering::Relaxed), _ => unreachable!("all possible values are covered"), }; + state } /// Add an IRQ event to both the global count and the CPU that handled it.