Ensure that MMIO memory is mapped without caching

This commit is contained in:
Jeremy Soller
2019-04-08 20:22:01 -06:00
parent e090281086
commit 7afaadabd9
11 changed files with 169 additions and 184 deletions
+3 -3
View File
@@ -6,7 +6,7 @@ use std::str;
use std::collections::BTreeMap;
use std::sync::atomic::{AtomicUsize, Ordering};
use syscall::PHYSMAP_WRITE;
use syscall::{PHYSMAP_NO_CACHE, PHYSMAP_WRITE};
use syscall::error::{Error, EACCES, EBADF, Result, EINVAL};
use syscall::flag::{SEEK_SET, SEEK_CUR, SEEK_END};
use syscall::io::{Mmio, Io};
@@ -159,7 +159,7 @@ impl IntelHDA {
};
let buff_desc_virt = unsafe {
syscall::physmap(buff_desc_phys, 0x1000, PHYSMAP_WRITE)
syscall::physmap(buff_desc_phys, 0x1000, PHYSMAP_WRITE | PHYSMAP_NO_CACHE)
.expect("ihdad: failed to map address for buffer descriptor list.")
};
@@ -172,7 +172,7 @@ impl IntelHDA {
.expect("Could not allocate physical memory for CORB and RIRB.")
};
let cmd_buff_virt = unsafe { syscall::physmap(cmd_buff_address, 0x1000, PHYSMAP_WRITE).expect("ihdad: failed to map address for CORB/RIRB buff") };
let cmd_buff_virt = unsafe { syscall::physmap(cmd_buff_address, 0x1000, PHYSMAP_WRITE | PHYSMAP_NO_CACHE).expect("ihdad: failed to map address for CORB/RIRB buff") };
print!("Virt: {:016X}, Phys: {:016X}\n", cmd_buff_virt, cmd_buff_address);
let mut module = IntelHDA {
+2 -2
View File
@@ -1,4 +1,4 @@
use syscall::PHYSMAP_WRITE;
use syscall::{PHYSMAP_WRITE, PHYSMAP_NO_CACHE};
use syscall::error::{Error, EIO, Result};
use syscall::io::{Mmio, Io};
use std::result;
@@ -301,7 +301,7 @@ impl StreamBuffer {
};
let addr = match unsafe {
syscall::physmap(phys, block_length * block_count, PHYSMAP_WRITE)
syscall::physmap(phys, block_length * block_count, PHYSMAP_WRITE | PHYSMAP_NO_CACHE)
} {
Ok(addr) => addr,
Err(err) => {