From dc33cba4c08b2035e33337bc60ff340ebcc838a2 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Tue, 11 Jun 2024 20:51:01 +0200
Subject: [PATCH 1/2] Fix typo

---
 virtio-core/src/spec/transport_pci.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/virtio-core/src/spec/transport_pci.rs b/virtio-core/src/spec/transport_pci.rs
index 7ef8efa8ef..c6cb4a8af4 100644
--- a/virtio-core/src/spec/transport_pci.rs
+++ b/virtio-core/src/spec/transport_pci.rs
@@ -33,7 +33,7 @@ pub struct PciCapability {
     pub cfg_type: CfgType,
     /// Where to find it.
     pub bar: u8,
-    /// Multiple capabilities of the same typel
+    /// Multiple capabilities of the same type.
     pub id: u8,
     /// Pad to a full dword.
     pub padding: [u8; 2],

From f6a709ee5aea5be311125cc85559dcf58afcf2a3 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Tue, 11 Jun 2024 20:50:48 +0200
Subject: [PATCH 2/2] pcid: Simplify PciFunc::read_range

This also avoids UB caused by creating a slice of uninitialized u8.
---
 Cargo.lock           |  1 -
 pcid/Cargo.toml      |  1 -
 pcid/src/pci/func.rs | 14 +++-----------
 3 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 9ce5ed9fb6..ad80b39ff7 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -922,7 +922,6 @@ dependencies = [
  "bincode",
  "bit_field",
  "bitflags 1.3.2",
- "byteorder",
  "common",
  "fdt 0.1.0",
  "libc",
diff --git a/pcid/Cargo.toml b/pcid/Cargo.toml
index 864e9a0598..6083222d46 100644
--- a/pcid/Cargo.toml
+++ b/pcid/Cargo.toml
@@ -15,7 +15,6 @@ path = "src/lib.rs"
 bincode = "1.2"
 bitflags = "1"
 bit_field = "0.10"
-byteorder = "1.2"
 fdt = { git = "https://gitlab.redox-os.org/rosehuds/fdt.git" }
 libc = "0.2"
 log = "0.4"
diff --git a/pcid/src/pci/func.rs b/pcid/src/pci/func.rs
index e94e40818d..7caec137a8 100644
--- a/pcid/src/pci/func.rs
+++ b/pcid/src/pci/func.rs
@@ -1,4 +1,3 @@
-use byteorder::{ByteOrder, LittleEndian};
 use pci_types::{ConfigRegionAccess, PciAddress};
 
 pub struct PciFunc<'pci> {
@@ -9,17 +8,10 @@ pub struct PciFunc<'pci> {
 impl<'pci> PciFunc<'pci> {
     pub unsafe fn read_range(&self, offset: u16, len: u16) -> Vec<u8> {
         assert!(len > 3 && len % 4 == 0, "invalid range length: {}", len);
-        let mut ret = Vec::with_capacity(len as usize);
-        let results = (offset..offset + len)
+        (offset..offset + len)
             .step_by(4)
-            .fold(Vec::new(), |mut acc, offset| {
-                let val = self.read_u32(offset);
-                acc.push(val);
-                acc
-            });
-        ret.set_len(len as usize);
-        LittleEndian::write_u32_into(&*results, &mut ret);
-        ret
+            .flat_map(|offset| self.read_u32(offset).to_le_bytes())
+            .collect::<Vec<u8>>()
     }
 
     pub unsafe fn read_u8(&self, offset: u16) -> u8 {