diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs index 05fe4fb468..9259770623 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs @@ -7,18 +7,23 @@ use super::dp_aux::DpAux; use super::info::IntelDeviceInfo; use crate::driver::Result; -// ── Display Stream Compression (DSC 1.2a) ──────────────────────────────── -// DSC reduces display link bandwidth by 2-3x using visually lossless -// compression. Required for 4K@60+ over DP 1.4 HBR3, 5K, 8K, and -// any DP 2.0 UHBR configuration. -// -// PPS (Picture Parameter Set): 128-byte configuration block containing -// slice dimensions, bits per component, and rate control parameters. -// Programmed into DSC_PPS registers per pipe before DSC enable. -// -// DSC_CTL (0x6B000): enable (bit 31), slice count (bits 11-8), -// bits per component (bits 5-4: 0=8, 1=10, 2=12) -// DPCD: DP_DSC_SUPPORT (0x060) sink capability, DP_DSC_ENABLE (0x06F) +const DSC_CTL_BASE: usize = 0x6B000; +const DSC_PPS_BASE: usize = 0x6B200; +const DSC_RC_RANGE_PARAM_BASE: usize = 0x6B400; +const DSC_TRANS_STRIDE: usize = 0x1000; +const DSC_PPS_SIZE: usize = 128; +const DSC_RC_RANGE_SIZE: usize = 128; + +const DSC_CTL_ENABLE: u32 = 1 << 31; +const DSC_CTL_SLICE_COUNT_SHIFT: u32 = 8; +const DSC_CTL_BPC_SHIFT: u32 = 4; +const DSC_CTL_BPC_8: u32 = 0; +const DSC_CTL_BPC_10: u32 = 1; +const DSC_CTL_BPC_12: u32 = 2; + +const DP_DSC_SUPPORT: u32 = 0x060; +const DP_DSC_ENABLE: u32 = 0x06F; +const DP_DSC_ENABLE_SINK: u8 = 1 << 0; pub struct DscState { mmio: Arc, diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs index 8100e0a5da..1b2c46f180 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs @@ -1,51 +1,77 @@ +pub mod alpm; +pub mod audio_eld; pub mod backlight; pub mod batch; +pub mod cdclk_tables; +pub mod color_lmem; +pub mod color_pipeline; pub mod context; pub mod cursor; +pub mod cx0_phy; pub mod ddi_buf_trans; pub mod display; pub mod display_cdclk; pub mod display_combo_phy; pub mod display_dmc; pub mod display_dpll; +pub mod display_irq; pub mod display_power; pub mod display_psr; pub mod display_transcoder; pub mod display_watermark; +pub mod dkl_phy; +pub mod dmc_power; +pub mod dp_audio; pub mod dp_aux; pub mod dp_link; pub mod dp_mst; pub mod drrs; pub mod dsb; +pub mod dp_fec; +pub mod dsc; +pub mod edp_pll; pub mod execlists; pub mod fbc; pub mod fence; pub mod gamma; pub mod gem; pub mod gmbus; +pub mod gpu_reset; pub mod gt; pub mod gtt; pub mod guc; +pub mod guc_submission; pub mod hangcheck; pub mod hdmi; +pub mod hdmi_frl; +pub mod hdmi_scrambler; pub mod hotplug; pub mod huc; pub mod info; pub mod lmem; +pub mod lspcon; +pub mod mg_pll; pub mod mocs; pub mod panel_pps; +pub mod panel_fitter; pub mod pch; pub mod plane_universal; pub mod psr2; +pub mod psr_full; pub mod regs; pub mod regs_gen4_7; pub mod regs_gen9; pub mod regs_gen12; pub mod regs_xe2; pub mod ring; +pub mod rps_rc6; +pub mod snps_phy; pub mod syncobj; +pub mod tc_port; pub mod vbt; +pub mod vrr; pub mod watermark; +pub mod workarounds; use std::collections::HashMap; use std::sync::atomic::{AtomicU64, Ordering}; @@ -1096,24 +1122,26 @@ impl GpuDriver for IntelDriver { } fn handle_irq(&self) -> Result> { - let irq_event = { - let mut irq_handle = self - .irq_handle - .lock() - .map_err(|_| DriverError::Initialization("Intel IRQ state poisoned".into()))?; - match irq_handle.as_mut() { - Some(handle) => handle - .try_wait() - .map_err(|e| DriverError::Io(format!("Intel IRQ poll failed: {e}")))?, - None => return Ok(None), - } + let mut irq_guard = self.irq_handle.lock() + .map_err(|_| DriverError::Initialization("Intel IRQ state poisoned".into()))?; + + let irq_event = match irq_guard.as_mut() { + Some(handle) => handle.try_wait() + .map_err(|e| DriverError::Io(format!("Intel IRQ poll failed: {e}")))?, + None => return Ok(None), }; if !irq_event { return Ok(None); } - self.process_irq() + let result = self.process_irq(); + + if let Some(handle) = irq_guard.as_mut() { + let _ = handle.eoi(); + } + + result } fn redox_private_cs_submit( diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/vrr.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/vrr.rs index 50d829b82e..814585c2db 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/vrr.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/vrr.rs @@ -6,15 +6,16 @@ use redox_driver_sys::memory::MmioRegion; use super::info::IntelDeviceInfo; use crate::driver::Result; -// ── Variable Refresh Rate / Adaptive Sync ──────────────────────────────── -// VRR allows the display refresh rate to vary dynamically to match -// GPU rendering rate, eliminating screen tearing without vsync latency. -// Compatible with VESA Adaptive-Sync, AMD FreeSync, and G-Sync Compatible. -// -// VRR_CTL: enable (bit 31), flip line (bits 12-0) -// The flip line specifies which scanline to flip the framebuffer at. -// VRR_MIN_FRAME_TIME / VRR_MAX_FRAME_TIME: vtotal range for refresh rate. -// VRR_STATUS: current VRR state per transcoder. +const VRR_CTL_BASE: usize = 0x60420; +const VRR_CTL_ENABLE: u32 = 1 << 31; +const VRR_CTL_FLIP_LINE_SHIFT: u32 = 0; +const VRR_CTL_FLIP_LINE_MASK: u32 = 0x1FFF; +const VRR_MAX_FRAME_TIME: u32 = 0x60424; +const VRR_MIN_FRAME_TIME: u32 = 0x60428; +const VRR_STATUS_BASE: usize = 0x60440; +const VRR_TRANS_STRIDE: usize = 0x1000; + +const VRR_DEFAULT_FLIP_LINE: u32 = 0x400; pub struct VrrState { mmio: Arc,