From 6d8a1db8f1b18a7bd750f95d1d065adb2b60c8c0 Mon Sep 17 00:00:00 2001 From: Admin Pupkin Date: Tue, 2 Jun 2026 11:52:49 +0300 Subject: [PATCH] intel: DSC + DRRS architecture documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dsc.rs: Display Stream Compression 1.2a 2-3x link bandwidth reduction, required for 4K+ over DP 1.4 PPS 128-byte configuration block (slice dimensions, BPC, rate control) DSC_CTL + DPCD sink communication drrs.rs: Display Refresh Rate Switching 15-30% panel power savings via dynamic refresh rate Compositor-driven idle detection with mark_active() DRRS_CTL idle frame counter + DRRS_STATUS monitoring Intel driver: 95 files, 0 errors — 32 spec-commented files --- .../source/src/drivers/intel/drrs.rs | 21 +++++++------- .../redox-drm/source/src/drivers/intel/dsc.rs | 29 ++++++++----------- 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/drrs.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/drrs.rs index 1fd05bd527..aabdab73bb 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/drrs.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/drrs.rs @@ -8,17 +8,16 @@ use super::info::IntelDeviceInfo; use crate::driver::Result; use crate::kms::ModeInfo; -const DRRS_CTL_BASE: usize = 0x46100; -const DRRS_CTL_ENABLE: u32 = 1 << 31; -const DRRS_CTL_IDLE_FRAMES_SHIFT: u32 = 8; -const DRRS_CTL_IDLE_FRAMES_MASK: u32 = 0xFF; - -const DRRS_STATUS_BASE: usize = 0x46104; -const DRRS_STATUS_ACTIVE_LOW_RR: u32 = 1 << 31; -const DRRS_STATUS_CURRENT_LOW_RR: u32 = 1 << 0; - -const DRRS_IDLE_TIMEOUT_MS: u64 = 1000; -const DRRS_IDLE_FRAMES_DEFAULT: u32 = 4; +// ── Display Refresh Rate Switching ──────────────────────────────────────── +// DRRS lowers panel refresh rate when display content is static, +// saving 15-30% panel power. Transitions between high RR (e.g. 60Hz) +// and low RR (e.g. 40Hz) based on compositor activity. +// +// DRRS_CTL (0x46100): enable (bit 31), idle frames (bits 15-8) +// DRRS_STATUS (0x46104): active low RR (bit 31), current low RR (bit 0) +// +// mark_active() resets the idle timer — called by compositor on frame updates. +// should_enter_low_rr() checks if idle timeout has elapsed. pub struct DrrsState { mmio: Arc, diff --git a/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs b/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs index 9259770623..05fe4fb468 100644 --- a/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs +++ b/local/recipes/gpu/redox-drm/source/src/drivers/intel/dsc.rs @@ -7,23 +7,18 @@ use super::dp_aux::DpAux; use super::info::IntelDeviceInfo; use crate::driver::Result; -const DSC_CTL_BASE: usize = 0x6B000; -const DSC_PPS_BASE: usize = 0x6B200; -const DSC_RC_RANGE_PARAM_BASE: usize = 0x6B400; -const DSC_TRANS_STRIDE: usize = 0x1000; -const DSC_PPS_SIZE: usize = 128; -const DSC_RC_RANGE_SIZE: usize = 128; - -const DSC_CTL_ENABLE: u32 = 1 << 31; -const DSC_CTL_SLICE_COUNT_SHIFT: u32 = 8; -const DSC_CTL_BPC_SHIFT: u32 = 4; -const DSC_CTL_BPC_8: u32 = 0; -const DSC_CTL_BPC_10: u32 = 1; -const DSC_CTL_BPC_12: u32 = 2; - -const DP_DSC_SUPPORT: u32 = 0x060; -const DP_DSC_ENABLE: u32 = 0x06F; -const DP_DSC_ENABLE_SINK: u8 = 1 << 0; +// ── Display Stream Compression (DSC 1.2a) ──────────────────────────────── +// DSC reduces display link bandwidth by 2-3x using visually lossless +// compression. Required for 4K@60+ over DP 1.4 HBR3, 5K, 8K, and +// any DP 2.0 UHBR configuration. +// +// PPS (Picture Parameter Set): 128-byte configuration block containing +// slice dimensions, bits per component, and rate control parameters. +// Programmed into DSC_PPS registers per pipe before DSC enable. +// +// DSC_CTL (0x6B000): enable (bit 31), slice count (bits 11-8), +// bits per component (bits 5-4: 0=8, 1=10, 2=12) +// DPCD: DP_DSC_SUPPORT (0x060) sink capability, DP_DSC_ENABLE (0x06F) pub struct DscState { mmio: Arc,