From 6bd4bb814fff1cd980263bbb3880351f1ea8cbfa Mon Sep 17 00:00:00 2001 From: 4lDO2 <4ldo2@protonmail.com> Date: Thu, 18 Jun 2020 19:17:20 +0000 Subject: [PATCH] Support xHCs that only support 32-bit physical addresses. --- Cargo.lock | 164 +++++++++++++++++----------------- nvmed/src/nvme/identify.rs | 6 +- nvmed/src/nvme/mod.rs | 4 +- xhcid/src/xhci/capability.rs | 6 ++ xhcid/src/xhci/context.rs | 19 ++-- xhcid/src/xhci/event.rs | 7 +- xhcid/src/xhci/irq_reactor.rs | 8 +- xhcid/src/xhci/mod.rs | 44 ++++++--- xhcid/src/xhci/ring.rs | 28 +++--- xhcid/src/xhci/scheme.rs | 12 +-- 10 files changed, 163 insertions(+), 135 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 6c72bc911e..e293e0c3cf 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -52,7 +52,7 @@ name = "atty" version = "0.2.14" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "hermit-abi 0.1.13 (registry+https://github.com/rust-lang/crates.io-index)", + "hermit-abi 0.1.14 (registry+https://github.com/rust-lang/crates.io-index)", "libc 0.2.71 (registry+https://github.com/rust-lang/crates.io-index)", "winapi 0.3.8 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -86,7 +86,7 @@ version = "1.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "byteorder 1.3.4 (registry+https://github.com/rust-lang/crates.io-index)", - "serde 1.0.110 (registry+https://github.com/rust-lang/crates.io-index)", + "serde 1.0.112 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -137,8 +137,8 @@ name = "chrono" version = "0.4.11" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ - "num-integer 0.1.42 (registry+https://github.com/rust-lang/crates.io-index)", - "num-traits 0.2.11 (registry+https://github.com/rust-lang/crates.io-index)", + "num-integer 0.1.43 (registry+https://github.com/rust-lang/crates.io-index)", + "num-traits 0.2.12 (registry+https://github.com/rust-lang/crates.io-index)", "time 0.1.43 (registry+https://github.com/rust-lang/crates.io-index)", ] @@ -274,9 +274,9 @@ version = "0.3.5" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "proc-macro-hack 0.5.16 (registry+https://github.com/rust-lang/crates.io-index)", - "proc-macro2 1.0.17 (registry+https://github.com/rust-lang/crates.io-index)", - "quote 1.0.6 (registry+https://github.com/rust-lang/crates.io-index)", - "syn 1.0.27 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro2 1.0.18 (registry+https://github.com/rust-lang/crates.io-index)", + "quote 1.0.7 (registry+https://github.com/rust-lang/crates.io-index)", + "syn 1.0.31 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] @@ -304,17 +304,17 @@ dependencies = [ "futures-sink 0.3.5 (registry+https://github.com/rust-lang/crates.io-index)", "futures-task 0.3.5 (registry+https://github.com/rust-lang/crates.io-index)", "memchr 2.3.3 (registry+https://github.com/rust-lang/crates.io-index)", - "pin-project 0.4.17 (registry+https://github.com/rust-lang/crates.io-index)", + "pin-project 0.4.22 (registry+https://github.com/rust-lang/crates.io-index)", "pin-utils 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)", "proc-macro-hack 0.5.16 (registry+https://github.com/rust-lang/crates.io-index)", - "proc-macro-nested 0.1.4 (registry+https://github.com/rust-lang/crates.io-index)", + "proc-macro-nested 0.1.6 (registry+https://github.com/rust-lang/crates.io-index)", "slab 0.4.2 (registry+https://github.com/rust-lang/crates.io-index)", ] [[package]] name = "gpt" version = "0.6.3" -source = "git+https://gitlab.redox-os.org/redox-os/gpt#de8270848edf07b68b7e0d73d6efcb15b2e1f090" +source = "git+https://gitlab.redox-os.org/redox-os/gpt#4d800981c5dfae60ae183dbddaa3e026f80a5e5c" dependencies = [ "bitflags 1.2.1 (registry+https://github.com/rust-lang/crates.io-index)", "crc 1.8.1 (registry+https://github.com/rust-lang/crates.io-index)", @@ -324,7 +324,7 @@ dependencies = [ [[package]] name = "hermit-abi" -version = "0.1.13" +version = "0.1.14" source = "registry+https://github.com/rust-lang/crates.io-index" dependencies = [ "libc 0.2.71 (registry+https://github.com/rust-lang/crates.io-index)", @@ -360,7 +360,7 @@ dependencies = [ [[package]] name = "itoa" -version = "0.4.5" +version = "0.4.6" source = "registry+https://github.com/rust-lang/crates.io-index" [[package]] @@ -476,7 +476,7 @@ dependencies = [ [[package]] name = "netutils" version = "0.1.0" -source = "git+https://gitlab.redox-os.org/redox-os/netutils.git?branch=redox-unix#6f81f874f2015d82e811102160808db581f585a5" +source = "git+https://gitlab.redox-os.org/redox-os/netutils.git?branch=redox-unix#a66c155fa4bb248151100c2ac861a913df7c75cd" dependencies = [ "arg_parser 0.1.0 (git+https://gitlab.redox-os.org/redox-os/arg-parser.git)", "extra 0.1.0 (git+https://gitlab.redox-os.org/redox-os/libextra.git)", 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that order. pub async fn identify_controller(&self) { // TODO: Use same buffer - let data: Dma = Dma::zeroed().unwrap(); + let data: Dma = unsafe { Dma::zeroed().unwrap().assume_init() }; // println!(" - Attempting to identify controller"); let comp = self @@ -175,7 +175,7 @@ impl Nvme { } pub async fn identify_namespace_list(&self, base: u32) -> Vec { // TODO: Use buffer - let data: Dma<[u32; 1024]> = Dma::zeroed().unwrap(); + let data: Dma<[u32; 1024]> = unsafe { Dma::zeroed().unwrap().assume_init() }; // println!(" - Attempting to retrieve namespace ID list"); let comp = self @@ -191,7 +191,7 @@ impl Nvme { } pub async fn identify_namespace(&self, nsid: u32) -> NvmeNamespace { //TODO: Use buffer - let data: Dma = Dma::zeroed().unwrap(); + let data: Dma = unsafe { Dma::zeroed().unwrap().assume_init() }; // println!(" - Attempting to identify namespace {}", nsid); let comp = self diff --git a/nvmed/src/nvme/mod.rs b/nvmed/src/nvme/mod.rs index f5af0f0c37..b80a633513 100644 --- a/nvmed/src/nvme/mod.rs +++ b/nvmed/src/nvme/mod.rs @@ -206,8 +206,8 @@ impl Nvme { // map the zero interrupt vector (which according to the spec shall always point to the // admin completion queue) to CQID 0 (admin completion queue) cqs_for_ivs: RwLock::new(std::iter::once((0, smallvec!(0))).collect()), - buffer: Mutex::new(Dma::zeroed()?), - buffer_prp: Mutex::new(Dma::zeroed()?), + buffer: Mutex::new(unsafe { Dma::zeroed()?.assume_init() }), + buffer_prp: Mutex::new(unsafe { Dma::zeroed()?.assume_init() }), interrupt_method: Mutex::new(interrupt_method), pcid_interface: Mutex::new(pcid_interface), reactor_sender, diff --git a/xhcid/src/xhci/capability.rs b/xhcid/src/xhci/capability.rs index 4ec7b10a15..5479be88fb 100644 --- a/xhcid/src/xhci/capability.rs +++ b/xhcid/src/xhci/capability.rs @@ -14,6 +14,8 @@ pub struct CapabilityRegs { pub hcc_params2: Mmio, } +pub const HCC_PARAMS1_AC64_BIT: u32 = 1 << HCC_PARAMS1_AC64_SHIFT; +pub const HCC_PARAMS1_AC64_SHIFT: u8 = 0; pub const HCC_PARAMS1_MAXPSASIZE_MASK: u32 = 0xF000; // 15:12 pub const HCC_PARAMS1_MAXPSASIZE_SHIFT: u8 = 12; pub const HCC_PARAMS1_XECP_MASK: u32 = 0xFFFF_0000; @@ -35,6 +37,10 @@ pub const HCS_PARAMS2_MAX_SCRATCHPAD_BUFS_HI_MASK: u32 = 0x03E0_0000; pub const HCS_PARAMS2_MAX_SCRATCHPAD_BUFS_HI_SHIFT: u8 = 21; impl CapabilityRegs { + pub fn ac64(&self) -> bool { + self.hcc_params1.readf(HCC_PARAMS1_AC64_BIT) + } + pub fn lec(&self) -> bool { self.hcc_params2.readf(HCC_PARAMS2_LEC_BIT) } diff --git a/xhcid/src/xhci/context.rs b/xhcid/src/xhci/context.rs index e971ad28a7..e6f56427e6 100644 --- a/xhcid/src/xhci/context.rs +++ b/xhcid/src/xhci/context.rs @@ -4,6 +4,7 @@ use log::debug; use syscall::error::Result; use syscall::io::{Dma, Io, Mmio}; +use super::Xhci; use super::ring::Ring; #[repr(packed)] @@ -80,13 +81,13 @@ pub struct DeviceContextList { } impl DeviceContextList { - pub fn new(max_slots: u8) -> Result { - let mut dcbaa = Dma::<[u64; 256]>::zeroed()?; + pub fn new(ac64: bool, max_slots: u8) -> Result { + let mut dcbaa = unsafe { Xhci::alloc_dma_zeroed_raw::<[u64; 256]>(ac64)? }; let mut contexts = vec![]; // Create device context buffers for each slot for i in 0..max_slots as usize { - let context: Dma = Dma::zeroed()?; + let context: Dma = unsafe { Xhci::alloc_dma_zeroed_raw(ac64) }?; dcbaa[i] = context.physical() as u64; contexts.push(context); } @@ -130,19 +131,19 @@ pub struct StreamContextArray { } impl StreamContextArray { - pub fn new(count: usize) -> Result { + pub fn new(ac64: bool, count: usize) -> Result { unsafe { Ok(Self { - contexts: Dma::zeroed_unsized(count)?, + contexts: Xhci::alloc_dma_zeroed_unsized_raw(ac64, count)?, rings: BTreeMap::new(), }) } } - pub fn add_ring(&mut self, stream_id: u16, link: bool) -> Result<()> { + pub fn add_ring(&mut self, ac64: bool, stream_id: u16, link: bool) -> Result<()> { // NOTE: stream_id 0 is reserved assert_ne!(stream_id, 0); - let ring = Ring::new(16, link)?; + let ring = Ring::new(ac64, 16, link)?; let pointer = ring.register(); let sct = StreamContextType::PrimaryRing; @@ -176,8 +177,8 @@ pub struct ScratchpadBufferArray { pub pages: Vec, } impl ScratchpadBufferArray { - pub fn new(page_size: usize, entries: u16) -> Result { - let mut entries = unsafe { Dma::zeroed_unsized(entries as usize)? }; + pub fn new(ac64: bool, page_size: usize, entries: u16) -> Result { + let mut entries = unsafe { Xhci::alloc_dma_zeroed_unsized_raw(ac64, entries as usize)? }; let pages = entries.iter_mut().map(|entry: &mut ScratchpadBufferEntry| -> Result { let pointer = unsafe { syscall::physalloc(page_size)? }; diff --git a/xhcid/src/xhci/event.rs b/xhcid/src/xhci/event.rs index b3e0af0e35..7ee17d6957 100644 --- a/xhcid/src/xhci/event.rs +++ b/xhcid/src/xhci/event.rs @@ -1,6 +1,7 @@ use syscall::error::Result; use syscall::io::{Dma, Io, Mmio}; +use super::Xhci; use super::ring::Ring; use super::trb::Trb; @@ -19,10 +20,10 @@ pub struct EventRing { } impl EventRing { - pub fn new() -> Result { + pub fn new(ac64: bool) -> Result { let mut ring = EventRing { - ste: unsafe { Dma::zeroed_unsized(1)? }, - ring: Ring::new(256, false)?, + ste: unsafe { Xhci::alloc_dma_zeroed_unsized_raw(ac64, 1)? }, + ring: Ring::new(ac64, 256, false)?, }; ring.ste[0].address.write(ring.ring.trbs.physical() as u64); diff --git a/xhcid/src/xhci/irq_reactor.rs b/xhcid/src/xhci/irq_reactor.rs index 2b80883c29..9989da87e5 100644 --- a/xhcid/src/xhci/irq_reactor.rs +++ b/xhcid/src/xhci/irq_reactor.rs @@ -218,7 +218,7 @@ impl IrqReactor { // Before waking, it's crucial that the command TRB that generated this event // is fetched before removing this event TRB from the queue. - let command_trb = match self.hci.cmd.lock().unwrap().phys_addr_to_entry_mut(phys_ptr) { + let command_trb = match self.hci.cmd.lock().unwrap().phys_addr_to_entry_mut(self.hci.cap.ac64(), phys_ptr) { Some(command_trb) => { let t = command_trb.clone(); command_trb.reserved(false); @@ -379,7 +379,7 @@ impl Future for EventTrbFuture { impl Xhci { pub fn get_transfer_trb(&self, paddr: u64, id: RingId) -> Option { - self.with_ring(id, |ring| ring.phys_addr_to_entry(paddr)).flatten() + self.with_ring(id, |ring| ring.phys_addr_to_entry(self.cap.ac64(), paddr)).flatten() } pub fn with_ring T>(&self, id: RingId, function: F) -> Option { use super::RingOrStreams; @@ -419,7 +419,7 @@ impl Xhci { is_isoch_or_vf, state_kind: StateKind::Transfer { ring_id, - phys_ptr: ring.trb_phys_ptr(trb), + phys_ptr: ring.trb_phys_ptr(self.cap.ac64(), trb), }, message: Arc::new(Mutex::new(None)), }, @@ -435,7 +435,7 @@ impl Xhci { // This is only possible for transfers if they are isochronous, or for Force Event TRBs (virtualization). is_isoch_or_vf: false, state_kind: StateKind::CommandCompletion { - phys_ptr: command_ring.trb_phys_ptr(trb), + phys_ptr: command_ring.trb_phys_ptr(self.cap.ac64(), trb), }, message: Arc::new(Mutex::new(None)), }, diff --git a/xhcid/src/xhci/mod.rs b/xhcid/src/xhci/mod.rs index d8f3348f71..3fc5d75a46 100644 --- a/xhcid/src/xhci/mod.rs +++ b/xhcid/src/xhci/mod.rs @@ -14,8 +14,8 @@ use crossbeam_channel::{Receiver, Sender}; use log::{debug, error, info, trace, warn}; use serde::Deserialize; use syscall::error::{Error, Result, EBADF, EBADMSG, ENOENT, EIO}; -use syscall::flag::O_RDONLY; -use syscall::io::{Dma, Io}; +use syscall::flag::{O_RDONLY, PhysallocFlags}; +use syscall::io::{Dma, Io, PhysBox}; use crate::usb; @@ -131,25 +131,25 @@ impl Xhci { } async fn fetch_dev_desc(&self, port: usize, slot: u8) -> Result { - let mut desc = Dma::::zeroed()?; + let mut desc = unsafe { self.alloc_dma_zeroed::()? }; self.get_desc_raw(port, slot, usb::DescriptorKind::Device, 0, &mut desc).await?; Ok(*desc) } async fn fetch_config_desc(&self, port: usize, slot: u8, config: u8) -> Result<(usb::ConfigDescriptor, [u8; 4087])> { - let mut desc = Dma::<(usb::ConfigDescriptor, [u8; 4087])>::zeroed()?; + let mut desc = unsafe { self.alloc_dma_zeroed::<(usb::ConfigDescriptor, [u8; 4087])>()? }; self.get_desc_raw(port, slot, usb::DescriptorKind::Configuration, config, &mut desc).await?; Ok(*desc) } async fn fetch_bos_desc(&self, port: usize, slot: u8) -> Result<(usb::BosDescriptor, [u8; 4087])> { - let mut desc = Dma::<(usb::BosDescriptor, [u8; 4087])>::zeroed()?; + let mut desc = unsafe { self.alloc_dma_zeroed::<(usb::BosDescriptor, [u8; 4087])>()? }; self.get_desc_raw(port, slot, usb::DescriptorKind::BinaryObjectStorage, 0, &mut desc).await?; Ok(*desc) } async fn fetch_string_desc(&self, port: usize, slot: u8, index: u8) -> Result { - let mut sdesc = Dma::<(u8, u8, [u16; 127])>::zeroed()?; + let mut sdesc = unsafe { self.alloc_dma_zeroed::<(u8, u8, [u16; 127])>()? }; self.get_desc_raw(port, slot, usb::DescriptorKind::String, index, &mut sdesc).await?; let len = sdesc.0 as usize; @@ -295,7 +295,7 @@ impl Xhci { // Create the command ring with 4096 / 16 (TRB size) entries, so that it uses all of the // DMA allocation (which is at least a 4k page). let entries_per_page = page_size / mem::size_of::(); - let cmd = Ring::new(entries_per_page, true)?; + let cmd = Ring::new(cap.ac64(), entries_per_page, true)?; let (irq_reactor_sender, irq_reactor_receiver) = crossbeam_channel::unbounded(); @@ -310,11 +310,11 @@ impl Xhci { dbs: Mutex::new(dbs), run: Mutex::new(run), - dev_ctx: DeviceContextList::new(max_slots)?, + dev_ctx: DeviceContextList::new(cap.ac64(), max_slots)?, scratchpad_buf_arr: None, // initialized in init() cmd: Mutex::new(cmd), - primary_event_ring: Mutex::new(EventRing::new()?), + primary_event_ring: Mutex::new(EventRing::new(cap.ac64())?), handles: CHashMap::new(), next_handle: AtomicUsize::new(0), port_states: CHashMap::new(), @@ -410,7 +410,7 @@ impl Xhci { if buf_count == 0 { return Ok(()); } - let scratchpad_buf_arr = ScratchpadBufferArray::new(self.page_size,buf_count)?; + let scratchpad_buf_arr = ScratchpadBufferArray::new(self.cap.ac64(), self.page_size,buf_count)?; self.dev_ctx.dcbaa[0] = scratchpad_buf_arr.register() as u64; debug!("Setting up {} scratchpads, at {:#0x}", buf_count, scratchpad_buf_arr.register()); self.scratchpad_buf_arr = Some(scratchpad_buf_arr); @@ -441,6 +441,26 @@ impl Xhci { pub fn slot_state(&self, slot: usize) -> u8 { self.dev_ctx.contexts[slot].slot.state() } + pub unsafe fn alloc_phys(ac64: bool, byte_count: usize) -> Result { + let flags = if ac64 { + PhysallocFlags::SPACE_64 + } else { + PhysallocFlags::SPACE_32 + }; + PhysBox::new_with_flags(byte_count, flags) + } + pub unsafe fn alloc_dma_zeroed_raw(ac64: bool) -> Result> { + Ok(Dma::from_physbox_zeroed(Self::alloc_phys(ac64, mem::size_of::())?)?.assume_init()) + } + pub unsafe fn alloc_dma_zeroed(&self) -> Result> { + Self::alloc_dma_zeroed_raw(self.cap.ac64()) + } + pub unsafe fn alloc_dma_zeroed_unsized_raw(ac64: bool, count: usize) -> Result> { + Ok(Dma::from_physbox_zeroed_unsized(Self::alloc_phys(ac64, mem::size_of::() * count)?, count)?.assume_init()) + } + pub unsafe fn alloc_dma_zeroed_unsized(&self, count: usize) -> Result> { + Self::alloc_dma_zeroed_unsized_raw(self.cap.ac64(), count) + } pub async fn probe(&self) -> Result<()> { info!("XHCI capabilities: {:?}", self.capabilities_iter().collect::>()); @@ -469,7 +489,7 @@ impl Xhci { info!("Enabled port {}, which the xHC mapped to {}", i, slot); - let mut input = Dma::::zeroed()?; + let mut input = unsafe { self.alloc_dma_zeroed::()? }; let mut ring = self.address_device(&mut input, i, slot_ty, slot, speed).await?; info!("Addressed device"); @@ -553,7 +573,7 @@ impl Xhci { slot: u8, speed: u8, ) -> Result { - let mut ring = Ring::new(16, true)?; + let mut ring = Ring::new(self.cap.ac64(), 16, true)?; { input_context.add_context.write(1 << 1 | 1); // Enable the slot (zeroth bit) and the control endpoint (first bit). diff --git a/xhcid/src/xhci/ring.rs b/xhcid/src/xhci/ring.rs index 67cafcf080..8326217858 100644 --- a/xhcid/src/xhci/ring.rs +++ b/xhcid/src/xhci/ring.rs @@ -3,6 +3,7 @@ use std::mem; use syscall::error::Result; use syscall::io::Dma; +use super::Xhci; use super::trb::Trb; pub struct Ring { @@ -13,10 +14,10 @@ pub struct Ring { } impl Ring { - pub fn new(length: usize, link: bool) -> Result { + pub fn new(ac64: bool, length: usize, link: bool) -> Result { Ok(Ring { - link: link, - trbs: unsafe { Dma::zeroed_unsized(length)? }, + link, + trbs: unsafe { Xhci::alloc_dma_zeroed_unsized_raw(ac64, length)? }, i: 0, cycle: link, }) @@ -64,9 +65,8 @@ impl Ring { /// /// # Panics /// Panics if paddr is not a multiple of 16 bytes, i.e. the size of a TRB. - // TODO: Use usize instead of u64. - pub fn phys_addr_to_index(&self, paddr: u64) -> Option { - let base = self.trbs.physical(); + pub fn phys_addr_to_index(&self, ac64: bool, paddr: u64) -> Option { + let base = self.trbs.physical() & if ac64 { 0xFFFF_FFFF_FFFF_FFFF } else { 0xFFFF_FFFF }; let offset = paddr.checked_sub(base as u64)? as usize; assert_eq!(offset % mem::size_of::(), 0, "unaligned TRB physical address"); @@ -79,15 +79,15 @@ impl Ring { Some(index) } - pub fn phys_addr_to_entry_ref(&self, paddr: u64) -> Option<&Trb> { - Some(&self.trbs[self.phys_addr_to_index(paddr)?]) + pub fn phys_addr_to_entry_ref(&self, ac64: bool, paddr: u64) -> Option<&Trb> { + Some(&self.trbs[self.phys_addr_to_index(ac64, paddr)?]) } - pub fn phys_addr_to_entry_mut(&mut self, paddr: u64) -> Option<&mut Trb> { - let index = self.phys_addr_to_index(paddr)?; + pub fn phys_addr_to_entry_mut(&mut self, ac64: bool, paddr: u64) -> Option<&mut Trb> { + let index = self.phys_addr_to_index(ac64, paddr)?; Some(&mut self.trbs[index]) } - pub fn phys_addr_to_entry(&self, paddr: u64) -> Option { - Some(self.trbs[self.phys_addr_to_index(paddr)?].clone()) + pub fn phys_addr_to_entry(&self, ac64: bool, paddr: u64) -> Option { + Some(self.trbs[self.phys_addr_to_index(ac64, paddr)?].clone()) } pub(crate) fn start_virt_addr(&self) -> *const Trb { self.trbs.as_ptr() @@ -95,7 +95,7 @@ impl Ring { pub(crate) fn end_virt_addr(&self) -> *const Trb { unsafe { self.start_virt_addr().offset(self.trbs.len() as isize) } } - pub fn trb_phys_ptr(&self, trb: &Trb) -> u64 { + pub fn trb_phys_ptr(&self, ac64: bool, trb: &Trb) -> u64 { let trb_virt_pointer = trb as *const Trb; let trbs_base_virt_pointer = self.trbs.as_ptr(); @@ -104,7 +104,7 @@ impl Ring { } let trb_offset_from_base = trb_virt_pointer as u64 - trbs_base_virt_pointer as u64; - let trbs_base_phys_ptr = self.trbs.physical() as u64; + let trbs_base_phys_ptr = (self.trbs.physical() as u64) & if ac64 { 0xFFFF_FFFF_FFFF_FFFF } else { 0xFFFF_FFFF }; let trb_phys_ptr = trbs_base_phys_ptr + trb_offset_from_base; trb_phys_ptr } diff --git a/xhcid/src/xhci/scheme.rs b/xhcid/src/xhci/scheme.rs index 039da4431f..8370414a85 100644 --- a/xhcid/src/xhci/scheme.rs +++ b/xhcid/src/xhci/scheme.rs @@ -694,10 +694,10 @@ impl Xhci { assert_ne!(ep_ty, 0); // 0 means invalid. let ring_ptr = if usb_log_max_streams.is_some() { - let mut array = StreamContextArray::new(1 << (primary_streams + 1))?; + let mut array = StreamContextArray::new(self.cap.ac64(), 1 << (primary_streams + 1))?; // TODO: Use as many stream rings as needed. - array.add_ring(1, true)?; + array.add_ring(self.cap.ac64(), 1, true)?; let array_ptr = array.register(); assert_eq!( @@ -715,7 +715,7 @@ impl Xhci { array_ptr } else { - let ring = Ring::new(16, true)?; + let ring = Ring::new(self.cap.ac64(), 16, true)?; let ring_ptr = ring.register(); assert_eq!( @@ -796,7 +796,7 @@ impl Xhci { if buf.is_empty() { return Err(Error::new(EINVAL)); } - let dma_buffer = unsafe { Dma::<[u8]>::zeroed_unsized(buf.len())? }; + let dma_buffer = unsafe { self.alloc_dma_zeroed_unsized(buf.len())? }; let (completion_code, bytes_transferred, dma_buffer) = self.transfer( port_num, @@ -812,7 +812,7 @@ impl Xhci { if sbuf.is_empty() { return Err(Error::new(EINVAL)); } - let mut dma_buffer = unsafe { Dma::<[u8]>::zeroed_unsized(sbuf.len()) }?; + let mut dma_buffer = unsafe { self.alloc_dma_zeroed_unsized(sbuf.len()) }?; dma_buffer.copy_from_slice(sbuf); trace!("TRANSFER_WRITE port {} ep {}, buffer at {:p}, size {}, dma buffer {:?}", port_num, endp_idx + 1, sbuf.as_ptr(), sbuf.len(), DmaSliceDbg(&dma_buffer)); @@ -1163,7 +1163,7 @@ impl Xhci { // TODO: Reuse buffers, or something. // TODO: Validate the size. // TODO: Sizes above 65536, *perhaps*. - let data_buffer = unsafe { Dma::<[u8]>::zeroed_unsized(req.length as usize)? }; + let data_buffer = unsafe { self.alloc_dma_zeroed_unsized(req.length as usize)? }; assert_eq!(data_buffer.len(), req.length as usize); Ok(match transfer_kind {