diff --git a/xhcid/src/xhci/mod.rs b/xhcid/src/xhci/mod.rs index cc02df6172..3ceec1e196 100644 --- a/xhcid/src/xhci/mod.rs +++ b/xhcid/src/xhci/mod.rs @@ -1188,7 +1188,15 @@ impl Xhci { .map(|subclass| subclass == ifdesc.sub_class) .unwrap_or(true) }) { - info!("Loading subdriver \"{}\"", driver.name); + info!( + "Loading subdriver \"{}\" for port {} iface {} proto {} class {}.{}", + driver.name, + port, + ifdesc.number, + ifdesc.protocol, + ifdesc.class, + ifdesc.sub_class + ); let (command, args) = driver.command.split_first().ok_or(Error::new(EBADMSG))?; let command = if command.starts_with('/') { @@ -1217,8 +1225,8 @@ impl Xhci { }); } else { warn!( - "No driver for USB class {}.{}", - ifdesc.class, ifdesc.sub_class + "No driver for port {} iface {} proto {} class {}.{}", + port, ifdesc.number, ifdesc.protocol, ifdesc.class, ifdesc.sub_class ); } } diff --git a/xhcid/src/xhci/scheme.rs b/xhcid/src/xhci/scheme.rs index c475bb2b18..4120365096 100644 --- a/xhcid/src/xhci/scheme.rs +++ b/xhcid/src/xhci/scheme.rs @@ -578,7 +578,7 @@ impl Xhci { pub async fn execute_command(&self, f: F) -> (Trb, Trb) { //TODO: find out why this bit is set earlier! if self.interrupt_is_pending(0) { - warn!("The EHB bit is already set!"); + debug!("The EHB bit is already set!"); //self.force_clear_interrupt(0); } @@ -586,7 +586,7 @@ impl Xhci { let mut command_ring = self.cmd.lock().unwrap(); let (cmd_index, cycle) = (command_ring.next_index(), command_ring.cycle); - info!("Sending command with cycle bit {}", cycle as u8); + debug!("Sending command with cycle bit {}", cycle as u8); { let command_trb = &mut command_ring.trbs[cmd_index];