Red Bear OS — microkernel OS in Rust, based on Redox
Derivative of Redox OS (https://www.redox-os.org) adding: - AMD GPU driver (amdgpu) via LinuxKPI compat layer - ext4 filesystem support (ext4d scheme daemon) - ACPI fixes for AMD bare metal (x2APIC, DMAR, IVRS, MCFG) - Custom branding (hostname, os-release, boot identity) Build system is full upstream Redox with RBOS overlay in local/. Patches for kernel, base, and relibc are symlinked from local/patches/ and protected from make clean/distclean. Custom recipes live in local/recipes/ with symlinks into the recipes/ search path. Build: make all CONFIG_NAME=redbear-full Sync: ./local/scripts/sync-upstream.sh
This commit is contained in:
@@ -0,0 +1,427 @@
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#include "redox_glue.h"
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/* Global state */
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static struct drm_device g_drm_dev;
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static struct device g_device;
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static struct pci_dev *g_pci_dev;
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static void __iomem *g_mmio_base;
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static size_t g_mmio_size;
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static u64 g_fb_phys;
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static size_t g_fb_size;
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static int g_asic_family = -1;
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/* ASIC family definitions based on device IDs */
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#define ASIC_FAMILY_NAVI10 0x7310
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#define ASIC_FAMILY_NAVI14 0x7340
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#define ASIC_FAMILY_NAVI21 0x73A0
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#define ASIC_FAMILY_NAVI22 0x73C0
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#define ASIC_FAMILY_NAVI23 0x73E0
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#define ASIC_FAMILY_NAVI24 0x7420
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#define ASIC_FAMILY_NAVI31 0x7440
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#define ASIC_FAMILY_NAVI32 0x7480
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#define ASIC_FAMILY_NAVI33 0x74A0
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#define AMDGPU_DC_HPD_STATUS_REG 0x4A00
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#define AMDGPU_DC_MAX_CONNECTORS 4
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#define AMDGPU_DC_BYTES_PER_PIXEL 4U
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#define AMDGPU_DC_PIXEL_FORMAT_ARGB8888 3U
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#define AMDGPU_DC_OTG_CONTROL 0x00
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#define AMDGPU_DC_OTG_VIEWPORT_SIZE 0x10
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#define AMDGPU_DC_OTG_VSYNC_ADJUST 0x14
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#define AMDGPU_DC_OTG_H_TOTAL 0x18
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#define AMDGPU_DC_OTG_V_TOTAL 0x1C
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#define AMDGPU_DC_OTG_VSTARTUP 0x20
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#define AMDGPU_DC_HUBP_PRIMARY_ADDR_LOW 0x00
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#define AMDGPU_DC_HUBP_PRIMARY_ADDR_HIGH 0x04
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#define AMDGPU_DC_HUBP_SURFACE_PITCH 0x08
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#define AMDGPU_DC_HUBP_SURFACE_CONFIG 0x0C
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#define AMDGPU_DC_HUBP_VIEWPORT_START 0x10
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#define AMDGPU_DC_HUBP_VIEWPORT_SIZE 0x14
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#define AMDGPU_DC_HUBP_FLIP_CONTROL 0x18
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#define AMDGPU_DC_HUBP_FLIP_ADDR_LOW 0x1C
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#define AMDGPU_DC_HUBP_FLIP_ADDR_HIGH 0x20
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struct connector_info_ffi {
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int id;
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int connector_type;
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int connector_type_id;
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int connection;
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int mm_width;
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int mm_height;
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int encoder_id;
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};
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struct amdgpu_redox_connector_desc {
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int id;
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u32 hpd_mask;
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int connector_type;
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int connector_type_id;
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int encoder_id;
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int mm_width;
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int mm_height;
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};
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static const struct amdgpu_redox_connector_desc g_connector_descs[AMDGPU_DC_MAX_CONNECTORS] = {
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{ .id = 1, .hpd_mask = 0x01, .connector_type = 10, .connector_type_id = 1, .encoder_id = 1, .mm_width = 600, .mm_height = 340 },
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{ .id = 2, .hpd_mask = 0x02, .connector_type = 10, .connector_type_id = 2, .encoder_id = 2, .mm_width = 600, .mm_height = 340 },
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{ .id = 3, .hpd_mask = 0x04, .connector_type = 11, .connector_type_id = 3, .encoder_id = 3, .mm_width = 600, .mm_height = 340 },
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{ .id = 4, .hpd_mask = 0x08, .connector_type = 11, .connector_type_id = 4, .encoder_id = 4, .mm_width = 600, .mm_height = 340 },
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};
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static inline void __iomem *amdgpu_dc_reg_ptr(u32 base, u32 offset)
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{
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return (u8 __iomem *)g_mmio_base + base + offset;
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}
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static int amdgpu_dc_validate_mmio_access(u32 base, u32 offset)
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{
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u64 end = (u64)base + (u64)offset + sizeof(u32);
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if (!g_mmio_base) {
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return -ENODEV;
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}
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if (end > g_mmio_size) {
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pr_err("amdgpu_redox: MMIO access %#x+%#x outside aperture %zu\n",
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base, offset, g_mmio_size);
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return -EINVAL;
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}
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return 0;
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}
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static inline void amdgpu_dc_write_reg(u32 base, u32 offset, u32 value)
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{
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if (amdgpu_dc_validate_mmio_access(base, offset) != 0) {
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return;
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}
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writel(value, amdgpu_dc_reg_ptr(base, offset));
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}
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static inline u32 amdgpu_dc_read_reg(u32 base, u32 offset)
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{
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if (amdgpu_dc_validate_mmio_access(base, offset) != 0) {
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return 0;
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}
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return readl(amdgpu_dc_reg_ptr(base, offset));
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}
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static inline u32 amdgpu_dc_hpd_status(void)
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{
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if (amdgpu_dc_validate_mmio_access(0, AMDGPU_DC_HPD_STATUS_REG) != 0) {
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return 0;
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}
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return readl((u8 __iomem *)g_mmio_base + AMDGPU_DC_HPD_STATUS_REG);
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}
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/* Initialize AMD Display Core */
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int amdgpu_dc_init(void *mmio_base, size_t mmio_size)
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{
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int ret = 0;
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u32 gpu_id = 0;
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const char *firmware_name = NULL;
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printk("amdgpu_redox: initializing AMD Display Core\n");
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if (!mmio_base || mmio_size < sizeof(u32)) {
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pr_err("amdgpu_redox: invalid MMIO for DC init\n");
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return -EINVAL;
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}
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gpu_id = readl(mmio_base);
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printk("amdgpu_redox: GPU ID = %#010x\n", gpu_id);
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switch (gpu_id) {
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case ASIC_FAMILY_NAVI10:
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g_asic_family = ASIC_FAMILY_NAVI10;
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firmware_name = "dmcub_dcn20.bin";
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break;
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case ASIC_FAMILY_NAVI14:
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g_asic_family = ASIC_FAMILY_NAVI14;
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firmware_name = "dmcub_dcn20.bin";
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break;
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case ASIC_FAMILY_NAVI21:
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g_asic_family = ASIC_FAMILY_NAVI21;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI22:
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g_asic_family = ASIC_FAMILY_NAVI22;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI23:
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g_asic_family = ASIC_FAMILY_NAVI23;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI24:
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g_asic_family = ASIC_FAMILY_NAVI24;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI31:
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g_asic_family = ASIC_FAMILY_NAVI31;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI32:
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g_asic_family = ASIC_FAMILY_NAVI32;
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firmware_name = "dmcub_dcn31.bin";
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break;
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case ASIC_FAMILY_NAVI33:
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g_asic_family = ASIC_FAMILY_NAVI33;
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firmware_name = "dmcub_dcn31.bin";
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break;
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default:
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pr_warn("amdgpu_redox: unknown ASIC %#010x, using DCN31 firmware\n", gpu_id);
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g_asic_family = gpu_id;
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firmware_name = "dmcub_dcn31.bin";
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break;
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}
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printk("amdgpu_redox: ASIC family identified, loading firmware: %s\n", firmware_name);
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{
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const struct firmware *fw = NULL;
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int fw_ret = request_firmware(&fw, firmware_name, NULL);
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if (fw_ret != 0 || !fw) {
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pr_warn("amdgpu_redox: firmware %s not available (err=%d), continuing without\n",
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firmware_name, fw_ret);
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} else {
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printk("amdgpu_redox: firmware %s loaded (%zu bytes)\n", firmware_name, fw->size);
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release_firmware(fw);
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}
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}
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return ret;
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}
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/* Initialize AMD GPU hardware for display */
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int amdgpu_redox_init(void *mmio_base, size_t mmio_size, uint64_t fb_phys, size_t fb_size)
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{
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int ret;
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printk("amdgpu_redox: initializing AMD GPU display\n");
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printk("amdgpu_redox: MMIO base=%p size=%zu\n", mmio_base, mmio_size);
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printk("amdgpu_redox: FB phys=%#llx size=%zu\n", (unsigned long long)fb_phys, fb_size);
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if (!mmio_base || mmio_size == 0) {
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pr_err("amdgpu_redox: invalid MMIO mapping provided by redox-drm\n");
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return -EINVAL;
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}
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memset(&g_drm_dev, 0, sizeof(g_drm_dev));
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memset(&g_device, 0, sizeof(g_device));
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g_mmio_base = mmio_base;
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g_mmio_size = mmio_size;
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g_fb_phys = fb_phys;
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g_fb_size = fb_size;
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g_pci_dev = redox_pci_find_amd_gpu();
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if (!g_pci_dev) {
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pr_err("amdgpu_redox: no AMD PCI device available from integration layer\n");
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return -ENODEV;
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}
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g_pci_dev->mmio_base = g_mmio_base;
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g_pci_dev->resource_start[0] = (phys_addr_t)(uintptr_t)g_mmio_base;
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g_pci_dev->resource_len[0] = g_mmio_size;
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g_device.pci_dev = g_pci_dev;
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g_drm_dev.dev = &g_device;
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ret = amdgpu_dc_init(mmio_base, mmio_size);
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if (ret != 0) {
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pr_err("amdgpu_redox: failed to initialize DC\n");
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return ret;
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}
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return 0;
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}
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/* Cleanup */
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void amdgpu_redox_cleanup(void)
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{
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printk("amdgpu_redox: cleanup\n");
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if (g_pci_dev) {
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redox_pci_dev_put(g_pci_dev);
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g_pci_dev = NULL;
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}
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g_mmio_base = NULL;
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g_mmio_size = 0;
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g_fb_phys = 0;
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g_fb_size = 0;
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memset(&g_drm_dev, 0, sizeof(g_drm_dev));
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memset(&g_device, 0, sizeof(g_device));
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}
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/* Get connector info — called by redox-drm */
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int amdgpu_dc_detect_connectors(void)
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{
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int num_connectors = 0;
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if (!g_mmio_base) {
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pr_err("amdgpu_redox: detect_connectors called before init\n");
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return -ENODEV;
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}
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#ifdef __redox__
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u32 hpd_status = amdgpu_dc_hpd_status();
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int i;
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for (i = 0; i < AMDGPU_DC_MAX_CONNECTORS; ++i) {
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if (hpd_status & g_connector_descs[i].hpd_mask) {
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num_connectors++;
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}
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}
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printk("amdgpu_redox: detected %d connector(s)\n", num_connectors);
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#else
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printk("amdgpu_redox: running on Linux, using AMD DC detection\n");
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#endif
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return num_connectors;
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}
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/* Get connector info by index */
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int amdgpu_dc_get_connector_info(int idx, void *info)
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{
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struct connector_info_ffi *ffi_info = (struct connector_info_ffi *)info;
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if (!g_mmio_base) {
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pr_err("amdgpu_redox: get_connector_info called before init\n");
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return -ENODEV;
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}
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if (idx < 0 || !ffi_info) {
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return -EINVAL;
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}
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#ifdef __redox__
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{
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u32 hpd_status = amdgpu_dc_hpd_status();
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int active_index = 0;
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int i;
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for (i = 0; i < AMDGPU_DC_MAX_CONNECTORS; ++i) {
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const struct amdgpu_redox_connector_desc *desc = &g_connector_descs[i];
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if (!(hpd_status & desc->hpd_mask)) {
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continue;
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}
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if (active_index == idx) {
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ffi_info->id = desc->id;
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ffi_info->connector_type = desc->connector_type;
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ffi_info->connector_type_id = desc->connector_type_id;
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ffi_info->connection = 1;
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ffi_info->mm_width = desc->mm_width;
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ffi_info->mm_height = desc->mm_height;
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ffi_info->encoder_id = desc->encoder_id;
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return 0;
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}
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active_index++;
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}
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}
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#endif
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return -ENOENT;
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}
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/* Set CRTC mode — called by redox-drm for modesetting */
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int amdgpu_dc_set_crtc(int crtc_id, uint64_t fb_addr, uint32_t width, uint32_t height)
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{
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printk("amdgpu_redox: set_crtc(%d, fb=%#llx, %ux%u)\n",
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crtc_id,
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(unsigned long long)fb_addr,
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width,
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height);
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if (!g_mmio_base) {
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pr_err("amdgpu_redox: set_crtc called before amdgpu_redox_init\n");
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return -ENODEV;
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}
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#ifdef __redox__
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const u32 bytes_per_pixel = AMDGPU_DC_BYTES_PER_PIXEL;
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u32 pitch;
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u32 viewport_size;
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const u32 h_total = width + 160U;
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const u32 v_total = height + 45U;
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const u32 v_sync_start = height + 3U;
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const u32 v_sync_end = v_sync_start + 5U;
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const u32 v_sync_adjust = (v_sync_start & 0xFFFFU) | (v_sync_end << 16);
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const u32 vstartup = v_sync_start > 1U ? (v_sync_start - 1U) : 0U;
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u64 required_bytes;
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if (crtc_id < 0 || crtc_id > 3) {
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pr_err("amdgpu_redox: invalid crtc_id %d\n", crtc_id);
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return -EINVAL;
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}
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if (width == 0 || height == 0 || width > 0xFFFFU || height > 0xFFFFU) {
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pr_err("amdgpu_redox: invalid mode %ux%u\n", width, height);
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return -EINVAL;
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}
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if (width > (UINT32_MAX / bytes_per_pixel)) {
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pr_err("amdgpu_redox: pitch overflow for width %u\n", width);
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return -EINVAL;
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}
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pitch = width * bytes_per_pixel;
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viewport_size = (width & 0xFFFFU) | (height << 16);
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required_bytes = (u64)pitch * (u64)height;
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/* The Rust-side allocates scanout buffers via GTT VA space (0..256MiB).
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* The display controller programs these GPU-virtual addresses directly;
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* the GTT hardware translates them to physical backing pages at runtime.
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* Validate only that the address + size fits in a u64 and that the
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* programmed registers can hold the values. */
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if (required_bytes == 0) {
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pr_err("amdgpu_redox: zero-sized framebuffer for crtc %d\n", crtc_id);
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return -EINVAL;
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}
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u32 otg_base = 0x4800 + (crtc_id * 0x800);
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u32 hubp_base = 0x5800 + (crtc_id * 0x400);
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u32 otg_control;
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if (amdgpu_dc_validate_mmio_access(otg_base, AMDGPU_DC_OTG_VSTARTUP) != 0 ||
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amdgpu_dc_validate_mmio_access(hubp_base, AMDGPU_DC_HUBP_FLIP_ADDR_HIGH) != 0) {
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return -EINVAL;
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}
|
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otg_control = amdgpu_dc_read_reg(otg_base, AMDGPU_DC_OTG_CONTROL);
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otg_control &= ~0x01U;
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amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_CONTROL, otg_control);
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mb();
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_PRIMARY_ADDR_LOW, (u32)(fb_addr & 0xFFFFFFFFULL));
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_PRIMARY_ADDR_HIGH, (u32)((fb_addr >> 32) & 0xFFFFFFFFULL));
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_SURFACE_PITCH, pitch);
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_SURFACE_CONFIG, AMDGPU_DC_PIXEL_FORMAT_ARGB8888);
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_VIEWPORT_START, 0);
|
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_VIEWPORT_SIZE, viewport_size);
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_FLIP_ADDR_LOW, (u32)(fb_addr & 0xFFFFFFFFULL));
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amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_FLIP_ADDR_HIGH, (u32)((fb_addr >> 32) & 0xFFFFFFFFULL));
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||||
amdgpu_dc_write_reg(hubp_base, AMDGPU_DC_HUBP_FLIP_CONTROL, 0);
|
||||
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_VIEWPORT_SIZE, viewport_size);
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_VSYNC_ADJUST, v_sync_adjust);
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_H_TOTAL, h_total);
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_V_TOTAL, v_total);
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_VSTARTUP, vstartup);
|
||||
mb();
|
||||
|
||||
otg_control |= 0x01;
|
||||
amdgpu_dc_write_reg(otg_base, AMDGPU_DC_OTG_CONTROL, otg_control);
|
||||
|
||||
printk("amdgpu_redox: CRTC %d enabled at %ux%u, fb=%#llx\n",
|
||||
crtc_id, width, height, (unsigned long long)fb_addr);
|
||||
#else
|
||||
printk("amdgpu_redox: running on Linux, using AMD DC modesetting\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user