pcid: Use pci_types for parsing capabilties
This commit is contained in:
bjorn3
+119
-97
@@ -5,10 +5,10 @@ use std::sync::Arc;
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use std::thread;
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use log::{error, info};
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use pci_types::capability::{MultipleMessageSupport, PciCapability};
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use pci_types::{ConfigRegionAccess, PciAddress};
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use crate::driver_interface;
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use crate::pci::cap::Capability as PciCapability;
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use crate::State;
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pub struct DriverHandler {
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@@ -97,7 +97,6 @@ impl DriverHandler {
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request: driver_interface::PcidClientRequest,
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args: &driver_interface::SubdriverArguments,
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) -> driver_interface::PcidClientResponse {
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use crate::pci::cap::{MsiCapability, MsixCapability};
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use driver_interface::*;
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match request {
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@@ -105,7 +104,9 @@ impl DriverHandler {
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self.capabilities
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.iter()
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.filter_map(|capability| match capability {
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PciCapability::Vendor(capability) => Some(capability.clone()),
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PciCapability::Vendor(addr) => unsafe {
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Some(VendorSpecificCapability::parse(*addr, &self.state.pcie))
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},
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_ => None,
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})
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.collect::<Vec<_>>(),
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@@ -121,85 +122,87 @@ impl DriverHandler {
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})
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.collect(),
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),
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PcidClientRequest::EnableFeature(feature) => match feature {
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PciFeature::Msi => {
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if let Some(msix_capability) = self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msix_mut())
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{
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// If MSI-X is supported disable it before enabling MSI as they can't be
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// active at the same time.
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unsafe {
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msix_capability.set_msix_enabled(false);
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msix_capability.write_a(self.addr, &self.state.pcie);
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PcidClientRequest::EnableFeature(feature) => {
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match feature {
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PciFeature::Msi => {
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if let Some(msix_capability) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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// If MSI-X is supported disable it before enabling MSI as they can't be
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// active at the same time.
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msix_capability.set_enabled(false, &self.state.pcie);
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}
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}
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let capability: &mut MsiCapability = match self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msi_mut())
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{
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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unsafe {
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capability.set_enabled(true);
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capability.write_message_control(self.addr, &self.state.pcie);
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let capability = match self.capabilities.iter_mut().find_map(|capability| {
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match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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}
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}) {
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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capability.set_enabled(true, &self.state.pcie);
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PcidClientResponse::FeatureEnabled(feature)
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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PciFeature::MsiX => {
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if let Some(msi_capability) = self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msi_mut())
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{
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// If MSI is supported disable it before enabling MSI-X as they can't be
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// active at the same time.
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unsafe {
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msi_capability.set_enabled(false);
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msi_capability.write_message_control(self.addr, &self.state.pcie);
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PciFeature::MsiX => {
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if let Some(msi_capability) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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// If MSI is supported disable it before enabling MSI-X as they can't be
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// active at the same time.
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msi_capability.set_enabled(false, &self.state.pcie);
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}
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}
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let capability: &mut MsixCapability = match self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msix_mut())
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{
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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unsafe {
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capability.set_msix_enabled(true);
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capability.write_a(self.addr, &self.state.pcie);
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let capability = match self.capabilities.iter_mut().find_map(|capability| {
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match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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}
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}) {
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Some(capability) => capability,
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None => {
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return PcidClientResponse::Error(
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PcidServerResponseError::NonexistentFeature(feature),
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)
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}
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};
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capability.set_enabled(true, &self.state.pcie);
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PcidClientResponse::FeatureEnabled(feature)
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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},
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}
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PcidClientRequest::FeatureInfo(feature) => PcidClientResponse::FeatureInfo(
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feature,
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match feature {
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PciFeature::Msi => {
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if let Some(info) = self
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.capabilities
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.iter()
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.find_map(|capability| capability.as_msi())
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if let Some(info) =
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self.capabilities
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.iter()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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PciFeatureInfo::Msi(msi::MsiInfo {
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log2_multiple_message_capable: info.multi_message_capable(),
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is_64bit: info.has_64_bit_addr(),
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has_per_vector_masking: info.is_pvt_capable(),
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log2_multiple_message_capable: info.multiple_message_capable()
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as u8,
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is_64bit: info.is_64bit(),
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has_per_vector_masking: info.has_per_vector_masking(),
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})
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} else {
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return PcidClientResponse::Error(
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@@ -208,16 +211,19 @@ impl DriverHandler {
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}
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}
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PciFeature::MsiX => {
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if let Some(info) = self
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.capabilities
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.iter()
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.find_map(|capability| capability.as_msix())
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if let Some(info) =
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self.capabilities
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.iter()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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PciFeatureInfo::MsiX(msi::MsixInfo {
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table_bar: info.table_bir(),
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table_bar: info.table_bar(),
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table_offset: info.table_offset(),
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table_size: info.table_size(),
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pba_bar: info.pba_bir(),
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pba_bar: info.pba_bar(),
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pba_offset: info.pba_offset(),
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})
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} else {
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@@ -230,18 +236,36 @@ impl DriverHandler {
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),
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PcidClientRequest::SetFeatureInfo(info_to_set) => match info_to_set {
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SetFeatureInfo::Msi(info_to_set) => {
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if let Some(info) = self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msi_mut())
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if let Some(info) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::Msi(cap) => Some(cap),
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_ => None,
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})
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{
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if let Some(mme) = info_to_set.multi_message_enable {
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if info.multi_message_capable() < mme || mme > 0b101 {
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if (info.multiple_message_capable() as u8) < mme {
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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info.set_multi_message_enable(mme);
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info.set_multiple_message_enable(
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match mme {
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0 => MultipleMessageSupport::Int1,
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1 => MultipleMessageSupport::Int2,
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2 => MultipleMessageSupport::Int4,
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3 => MultipleMessageSupport::Int8,
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4 => MultipleMessageSupport::Int16,
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5 => MultipleMessageSupport::Int32,
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_ => {
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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)
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}
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},
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&self.state.pcie,
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);
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}
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if let Some(message_addr_and_data) = info_to_set.message_address_and_data {
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let message_addr = message_addr_and_data.addr;
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@@ -250,27 +274,25 @@ impl DriverHandler {
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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info.set_message_address(message_addr as u32);
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info.set_message_upper_address((message_addr >> 32) as u32);
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if message_addr_and_data.data & ((1 << info.multi_message_enable()) - 1)
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if message_addr_and_data.data
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& ((1 << info.multiple_message_enable(&self.state.pcie) as u8) - 1)
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!= 0
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{
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return PcidClientResponse::Error(
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PcidServerResponseError::InvalidBitPattern,
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);
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}
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info.set_message_data(
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info.set_message_info(
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message_addr,
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message_addr_and_data
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.data
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.try_into()
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.expect("pcid: MSI message data too big"),
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&self.state.pcie,
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);
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}
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if let Some(mask_bits) = info_to_set.mask_bits {
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info.set_mask_bits(mask_bits);
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}
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unsafe {
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info.write_all(self.addr, &self.state.pcie);
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info.set_message_mask(mask_bits, &self.state.pcie);
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::Msi)
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} else {
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@@ -280,16 +302,16 @@ impl DriverHandler {
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}
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}
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SetFeatureInfo::MsiX { function_mask } => {
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if let Some(info) = self
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.capabilities
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.iter_mut()
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.find_map(|capability| capability.as_msix_mut())
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if let Some(info) =
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self.capabilities
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.iter_mut()
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.find_map(|capability| match capability {
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PciCapability::MsiX(cap) => Some(cap),
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_ => None,
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})
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{
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if let Some(mask) = function_mask {
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info.set_function_mask(mask);
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unsafe {
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info.write_a(self.addr, &self.state.pcie);
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}
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info.set_function_mask(mask, &self.state.pcie);
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::MsiX)
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} else {
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