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mesa-clc: vendor as full-fork recipe (path=source, patches baked)

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vasilito
2026-08-01 04:44:05 +03:00
parent f8e4789a2b
commit 406ee9fbeb
12522 changed files with 6035591 additions and 3 deletions
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local/recipes/dev/mesa-clc/source/include/drm-uapi/README
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This directory contains a copy of the installed kernel headers
required by several drivers to communicate with the kernel.
Whenever one of those driver needs new definitions for new kernel
APIs, these files should be updated.
These files in upstream Mesa should only be updated once the changes
have landed in the drm-next branch of the drm repository.
The drm repository is currently located at:
* https://gitlab.freedesktop.org/drm/kernel
* git url: https://gitlab.freedesktop.org/drm/kernel.git
Tagged Linux kernel releases can also be used.
When using the drm repository, it is recommended that the headers are
generated using a *merge commit* in the drm-next branch. After
checking out the commit in the drm (or tagged Linux release) tree, the
drm-uapi files can be generated by running this from the drm tree:
$ make headers_install INSTALL_HDR_PATH=/path/to/install
This will generate files under /path/to/install/include/drm which can
be copied into the Mesa include/drm-uapi directory. It is not required
to copy/update all kernel header files.
The commit message for the Mesa drm-uapi update should include the
full commit version of the drm kernel tree. An easy way to generate
this is with the following command in the drm tree:
$ git log -1 --pretty=short --no-decorate
Which would produce output similar to this to include in the Mesa
commit:
commit a78313bb206e0c456a989f380c4cbd8af8af7c76
Merge: 365aa9f57399 79655e867ad6
Author: Dave Airlie <airlied@redhat.com>
Merge tag 'drm-intel-gt-next-2024-06-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
local/recipes/dev/mesa-clc/source/include/drm-uapi/amdgpu_drm.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/asahi_drm.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/d3dkmthk.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/dma-buf.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Framework for buffer objects that can be shared across devices/subsystems.
*
* Copyright(C) 2015 Intel Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _DMA_BUF_UAPI_H_
#define _DMA_BUF_UAPI_H_
#if defined(__linux__) || defined(__managarm__)
#include <linux/types.h>
#else /* One of the BSDs */
#include <stdint.h>
#include <sys/types.h>
typedef int8_t __s8;
typedef uint8_t __u8;
typedef int16_t __s16;
typedef uint16_t __u16;
typedef int32_t __s32;
typedef uint32_t __u32;
typedef int64_t __s64;
typedef uint64_t __u64;
#endif
/**
* struct dma_buf_sync - Synchronize with CPU access.
*
* When a DMA buffer is accessed from the CPU via mmap, it is not always
* possible to guarantee coherency between the CPU-visible map and underlying
* memory. To manage coherency, DMA_BUF_IOCTL_SYNC must be used to bracket
* any CPU access to give the kernel the chance to shuffle memory around if
* needed.
*
* Prior to accessing the map, the client must call DMA_BUF_IOCTL_SYNC
* with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
* access is complete, the client should call DMA_BUF_IOCTL_SYNC with
* DMA_BUF_SYNC_END and the same read/write flags.
*
* The synchronization provided via DMA_BUF_IOCTL_SYNC only provides cache
* coherency. It does not prevent other processes or devices from
* accessing the memory at the same time. If synchronization with a GPU or
* other device driver is required, it is the client's responsibility to
* wait for buffer to be ready for reading or writing before calling this
* ioctl with DMA_BUF_SYNC_START. Likewise, the client must ensure that
* follow-up work is not submitted to GPU or other device driver until
* after this ioctl has been called with DMA_BUF_SYNC_END?
*
* If the driver or API with which the client is interacting uses implicit
* synchronization, waiting for prior work to complete can be done via
* poll() on the DMA buffer file descriptor. If the driver or API requires
* explicit synchronization, the client may have to wait on a sync_file or
* other synchronization primitive outside the scope of the DMA buffer API.
*/
struct dma_buf_sync {
/**
* @flags: Set of access flags
*
* DMA_BUF_SYNC_START:
* Indicates the start of a map access session.
*
* DMA_BUF_SYNC_END:
* Indicates the end of a map access session.
*
* DMA_BUF_SYNC_READ:
* Indicates that the mapped DMA buffer will be read by the
* client via the CPU map.
*
* DMA_BUF_SYNC_WRITE:
* Indicates that the mapped DMA buffer will be written by the
* client via the CPU map.
*
* DMA_BUF_SYNC_RW:
* An alias for DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE.
*/
__u64 flags;
};
#define DMA_BUF_SYNC_READ (1 << 0)
#define DMA_BUF_SYNC_WRITE (2 << 0)
#define DMA_BUF_SYNC_RW (DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE)
#define DMA_BUF_SYNC_START (0 << 2)
#define DMA_BUF_SYNC_END (1 << 2)
#define DMA_BUF_SYNC_VALID_FLAGS_MASK \
(DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END)
#define DMA_BUF_NAME_LEN 32
/**
* struct dma_buf_export_sync_file - Get a sync_file from a dma-buf
*
* Userspace can perform a DMA_BUF_IOCTL_EXPORT_SYNC_FILE to retrieve the
* current set of fences on a dma-buf file descriptor as a sync_file. CPU
* waits via poll() or other driver-specific mechanisms typically wait on
* whatever fences are on the dma-buf at the time the wait begins. This
* is similar except that it takes a snapshot of the current fences on the
* dma-buf for waiting later instead of waiting immediately. This is
* useful for modern graphics APIs such as Vulkan which assume an explicit
* synchronization model but still need to inter-operate with dma-buf.
*
* The intended usage pattern is the following:
*
* 1. Export a sync_file with flags corresponding to the expected GPU usage
* via DMA_BUF_IOCTL_EXPORT_SYNC_FILE.
*
* 2. Submit rendering work which uses the dma-buf. The work should wait on
* the exported sync file before rendering and produce another sync_file
* when complete.
*
* 3. Import the rendering-complete sync_file into the dma-buf with flags
* corresponding to the GPU usage via DMA_BUF_IOCTL_IMPORT_SYNC_FILE.
*
* Unlike doing implicit synchronization via a GPU kernel driver's exec ioctl,
* the above is not a single atomic operation. If userspace wants to ensure
* ordering via these fences, it is the respnosibility of userspace to use
* locks or other mechanisms to ensure that no other context adds fences or
* submits work between steps 1 and 3 above.
*/
struct dma_buf_export_sync_file {
/**
* @flags: Read/write flags
*
* Must be DMA_BUF_SYNC_READ, DMA_BUF_SYNC_WRITE, or both.
*
* If DMA_BUF_SYNC_READ is set and DMA_BUF_SYNC_WRITE is not set,
* the returned sync file waits on any writers of the dma-buf to
* complete. Waiting on the returned sync file is equivalent to
* poll() with POLLIN.
*
* If DMA_BUF_SYNC_WRITE is set, the returned sync file waits on
* any users of the dma-buf (read or write) to complete. Waiting
* on the returned sync file is equivalent to poll() with POLLOUT.
* If both DMA_BUF_SYNC_WRITE and DMA_BUF_SYNC_READ are set, this
* is equivalent to just DMA_BUF_SYNC_WRITE.
*/
__u32 flags;
/** @fd: Returned sync file descriptor */
__s32 fd;
};
/**
* struct dma_buf_import_sync_file - Insert a sync_file into a dma-buf
*
* Userspace can perform a DMA_BUF_IOCTL_IMPORT_SYNC_FILE to insert a
* sync_file into a dma-buf for the purposes of implicit synchronization
* with other dma-buf consumers. This allows clients using explicitly
* synchronized APIs such as Vulkan to inter-op with dma-buf consumers
* which expect implicit synchronization such as OpenGL or most media
* drivers/video.
*/
struct dma_buf_import_sync_file {
/**
* @flags: Read/write flags
*
* Must be DMA_BUF_SYNC_READ, DMA_BUF_SYNC_WRITE, or both.
*
* If DMA_BUF_SYNC_READ is set and DMA_BUF_SYNC_WRITE is not set,
* this inserts the sync_file as a read-only fence. Any subsequent
* implicitly synchronized writes to this dma-buf will wait on this
* fence but reads will not.
*
* If DMA_BUF_SYNC_WRITE is set, this inserts the sync_file as a
* write fence. All subsequent implicitly synchronized access to
* this dma-buf will wait on this fence.
*/
__u32 flags;
/** @fd: Sync file descriptor */
__s32 fd;
};
#define DMA_BUF_BASE 'b'
#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync)
/* 32/64bitness of this uapi was botched in android, there's no difference
* between them in actual uapi, they're just different numbers.
*/
#define DMA_BUF_SET_NAME _IOW(DMA_BUF_BASE, 1, const char *)
#define DMA_BUF_SET_NAME_A _IOW(DMA_BUF_BASE, 1, __u32)
#define DMA_BUF_SET_NAME_B _IOW(DMA_BUF_BASE, 1, __u64)
#define DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct dma_buf_export_sync_file)
#define DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct dma_buf_import_sync_file)
#endif
local/recipes/dev/mesa-clc/source/include/drm-uapi/drm.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/drm_fourcc.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/drm_mode.h
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local/recipes/dev/mesa-clc/source/include/drm-uapi/ethosu_accel.h
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/* SPDX-License-Identifier: MIT */
/* Copyright (C) 2025 Arm, Ltd. */
#ifndef _ETHOSU_DRM_H_
#define _ETHOSU_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* DOC: IOCTL IDs
*
* enum drm_ethosu_ioctl_id - IOCTL IDs
*
* Place new ioctls at the end, don't re-order, don't replace or remove entries.
*
* These IDs are not meant to be used directly. Use the DRM_IOCTL_ETHOSU_xxx
* definitions instead.
*/
enum drm_ethosu_ioctl_id {
/** @DRM_ETHOSU_DEV_QUERY: Query device information. */
DRM_ETHOSU_DEV_QUERY = 0,
/** @DRM_ETHOSU_BO_CREATE: Create a buffer object. */
DRM_ETHOSU_BO_CREATE,
/** @DRM_ETHOSU_BO_WAIT: Wait on a buffer object's fence. */
DRM_ETHOSU_BO_WAIT,
/**
* @DRM_ETHOSU_BO_MMAP_OFFSET: Get the file offset to pass to
* mmap to map a GEM object.
*/
DRM_ETHOSU_BO_MMAP_OFFSET,
/**
* @DRM_ETHOSU_CMDSTREAM_BO_CREATE: Create a command stream buffer
* object.
*/
DRM_ETHOSU_CMDSTREAM_BO_CREATE,
/** @DRM_ETHOSU_SUBMIT: Submit a job and BOs to run. */
DRM_ETHOSU_SUBMIT,
};
/**
* DOC: IOCTL arguments
*/
/**
* enum drm_ethosu_dev_query_type - Query type
*
* Place new types at the end, don't re-order, don't remove or replace.
*/
enum drm_ethosu_dev_query_type {
/** @DRM_ETHOSU_DEV_QUERY_NPU_INFO: Query NPU information. */
DRM_ETHOSU_DEV_QUERY_NPU_INFO = 0,
};
/**
* struct drm_ethosu_gpu_info - NPU information
*
* Structure grouping all queryable information relating to the NPU.
*/
struct drm_ethosu_npu_info {
/** @id : NPU ID. */
__u32 id;
#define DRM_ETHOSU_ARCH_MAJOR(x) ((x) >> 28)
#define DRM_ETHOSU_ARCH_MINOR(x) (((x) >> 20) & 0xff)
#define DRM_ETHOSU_ARCH_PATCH(x) (((x) >> 16) & 0xf)
#define DRM_ETHOSU_PRODUCT_MAJOR(x) (((x) >> 12) & 0xf)
#define DRM_ETHOSU_VERSION_MAJOR(x) (((x) >> 8) & 0xf)
#define DRM_ETHOSU_VERSION_MINOR(x) (((x) >> 4) & 0xff)
#define DRM_ETHOSU_VERSION_STATUS(x) ((x) & 0xf)
/** @gpu_rev: GPU revision. */
__u32 config;
__u32 sram_size;
};
/**
* struct drm_ethosu_dev_query - Arguments passed to DRM_ETHOSU_IOCTL_DEV_QUERY
*/
struct drm_ethosu_dev_query {
/** @type: the query type (see drm_ethosu_dev_query_type). */
__u32 type;
/**
* @size: size of the type being queried.
*
* If pointer is NULL, size is updated by the driver to provide the
* output structure size. If pointer is not NULL, the driver will
* only copy min(size, actual_structure_size) bytes to the pointer,
* and update the size accordingly. This allows us to extend query
* types without breaking userspace.
*/
__u32 size;
/**
* @pointer: user pointer to a query type struct.
*
* Pointer can be NULL, in which case, nothing is copied, but the
* actual structure size is returned. If not NULL, it must point to
* a location that's large enough to hold size bytes.
*/
__u64 pointer;
};
/**
* enum drm_ethosu_bo_flags - Buffer object flags, passed at creation time.
*/
enum drm_ethosu_bo_flags {
/**
* @DRM_ETHOSU_BO_NO_MMAP: The buffer object will never be CPU-mapped
* in userspace.
*/
DRM_ETHOSU_BO_NO_MMAP = (1 << 0),
};
/**
* struct drm_ethosu_bo_create - Arguments passed to DRM_IOCTL_ETHOSU_BO_CREATE.
*/
struct drm_ethosu_bo_create {
/**
* @size: Requested size for the object
*
* The (page-aligned) allocated size for the object will be returned.
*/
__u64 size;
/**
* @flags: Flags. Must be a combination of drm_ethosu_bo_flags flags.
*/
__u32 flags;
/**
* @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
__u32 handle;
};
/**
* struct drm_ethosu_bo_mmap_offset - Arguments passed to DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET.
*/
struct drm_ethosu_bo_mmap_offset {
/** @handle: Handle of the object we want an mmap offset for. */
__u32 handle;
/** @pad: MBZ. */
__u32 pad;
/** @offset: The fake offset to use for subsequent mmap calls. */
__u64 offset;
};
/**
* struct drm_ethosu_wait_bo - ioctl argument for waiting for
* completion of the last DRM_ETHOSU_SUBMIT on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_ethosu_bo_wait {
__u32 handle;
__u32 pad;
__s64 timeout_ns; /* absolute */
};
struct drm_ethosu_cmdstream_bo_create {
/* Size of the data argument. */
__u32 size;
/* Flags, currently must be 0. */
__u32 flags;
/* Pointer to the data. */
__u64 data;
/** Returned GEM handle for the BO. */
__u32 handle;
/* Pad, must be 0. */
__u32 pad;
};
/**
* struct drm_ethosu_job - A job to be run on the NPU
*
* The kernel will schedule the execution of this job taking into account its
* dependencies with other jobs. All tasks in the same job will be executed
* sequentially on the same core, to benefit from memory residency in SRAM.
*/
struct drm_ethosu_job {
/** Input: BO handle for cmdstream. */
__u32 cmd_bo;
/** Input: Amount of SRAM to use. */
__u32 sram_size;
#define ETHOSU_MAX_REGIONS 8
/** Input: Array of BO handles for each region. */
__u32 region_bo_handles[ETHOSU_MAX_REGIONS];
};
/**
* struct drm_ethosu_submit - ioctl argument for submitting commands to the NPU.
*
* The kernel will schedule the execution of these jobs in dependency order.
*/
struct drm_ethosu_submit {
/** Input: Pointer to an array of struct drm_ethosu_job. */
__u64 jobs;
/** Input: Number of jobs passed in. */
__u32 job_count;
/** Reserved, must be zero. */
__u32 pad;
};
/**
* DRM_IOCTL_ETHOSU() - Build a ethosu IOCTL number
* @__access: Access type. Must be R, W or RW.
* @__id: One of the DRM_ETHOSU_xxx id.
* @__type: Suffix of the type being passed to the IOCTL.
*
* Don't use this macro directly, use the DRM_IOCTL_ETHOSU_xxx
* values instead.
*
* Return: An IOCTL number to be passed to ioctl() from userspace.
*/
#define DRM_IOCTL_ETHOSU(__access, __id, __type) \
DRM_IO ## __access(DRM_COMMAND_BASE + DRM_ETHOSU_ ## __id, \
struct drm_ethosu_ ## __type)
enum {
DRM_IOCTL_ETHOSU_DEV_QUERY =
DRM_IOCTL_ETHOSU(WR, DEV_QUERY, dev_query),
DRM_IOCTL_ETHOSU_BO_CREATE =
DRM_IOCTL_ETHOSU(WR, BO_CREATE, bo_create),
DRM_IOCTL_ETHOSU_BO_WAIT =
DRM_IOCTL_ETHOSU(WR, BO_WAIT, bo_wait),
DRM_IOCTL_ETHOSU_BO_MMAP_OFFSET =
DRM_IOCTL_ETHOSU(WR, BO_MMAP_OFFSET, bo_mmap_offset),
DRM_IOCTL_ETHOSU_CMDSTREAM_BO_CREATE =
DRM_IOCTL_ETHOSU(WR, CMDSTREAM_BO_CREATE, cmdstream_bo_create),
DRM_IOCTL_ETHOSU_SUBMIT =
DRM_IOCTL_ETHOSU(WR, SUBMIT, submit),
};
#if defined(__cplusplus)
}
#endif
#endif /* _ETHOSU_DRM_H_ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/etnaviv_drm.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2015 Etnaviv Project
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ETNAVIV_DRM_H__
#define __ETNAVIV_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints:
* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
* user/kernel compatibility
* 2) Keep fields aligned to their size
* 3) Because of how drm_ioctl() works, we can add new fields at
* the end of an ioctl if some care is taken: drm_ioctl() will
* zero out the new fields at the tail of the ioctl, so a zero
* value should have a backwards compatible meaning. And for
* output params, userspace won't see the newly added output
* fields.. so that has to be somehow ok.
*/
/* timeouts are specified in clock-monotonic absolute times (to simplify
* restarting interrupted ioctls). The following struct is logically the
* same as 'struct timespec' but 32/64b ABI safe.
*/
struct drm_etnaviv_timespec {
__s64 tv_sec; /* seconds */
__s64 tv_nsec; /* nanoseconds */
};
#define ETNAVIV_PARAM_GPU_MODEL 0x01
#define ETNAVIV_PARAM_GPU_REVISION 0x02
#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
#define ETNA_MAX_PIPES 4
struct drm_etnaviv_param {
__u32 pipe; /* in */
__u32 param; /* in, ETNAVIV_PARAM_x */
__u64 value; /* out (get_param) or in (set_param) */
};
/*
* GEM buffers:
*/
#define ETNA_BO_CACHE_MASK 0x000f0000
/* cache modes */
#define ETNA_BO_CACHED 0x00010000
#define ETNA_BO_WC 0x00020000
#define ETNA_BO_UNCACHED 0x00040000
/* map flags */
#define ETNA_BO_FORCE_MMU 0x00100000
struct drm_etnaviv_gem_new {
__u64 size; /* in */
__u32 flags; /* in, mask of ETNA_BO_x */
__u32 handle; /* out */
};
struct drm_etnaviv_gem_info {
__u32 handle; /* in */
__u32 pad;
__u64 offset; /* out, offset to pass to mmap() */
};
#define ETNA_PREP_READ 0x01
#define ETNA_PREP_WRITE 0x02
#define ETNA_PREP_NOSYNC 0x04
struct drm_etnaviv_gem_cpu_prep {
__u32 handle; /* in */
__u32 op; /* in, mask of ETNA_PREP_x */
struct drm_etnaviv_timespec timeout; /* in */
};
struct drm_etnaviv_gem_cpu_fini {
__u32 handle; /* in */
__u32 flags; /* in, placeholder for now, no defined values */
};
/*
* Cmdstream Submission:
*/
/* The value written into the cmdstream is logically:
* relocbuf->gpuaddr + reloc_offset
*
* NOTE that reloc's must be sorted by order of increasing submit_offset,
* otherwise EINVAL.
*/
struct drm_etnaviv_gem_submit_reloc {
__u32 submit_offset; /* in, offset from submit_bo */
__u32 reloc_idx; /* in, index of reloc_bo buffer */
__u64 reloc_offset; /* in, offset from start of reloc_bo */
__u32 flags; /* in, placeholder for now, no defined values */
};
/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
* cmdstream buffer(s) themselves or reloc entries) has one (and only
* one) entry in the submit->bos[] table.
*
* As a optimization, the current buffer (gpu virtual address) can be
* passed back through the 'presumed' field. If on a subsequent reloc,
* userspace passes back a 'presumed' address that is still valid,
* then patching the cmdstream for this entry is skipped. This can
* avoid kernel needing to map/access the cmdstream bo in the common
* case.
* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
* field is interpreted as the fixed location to map the bo into the gpu
* virtual address space. If the kernel is unable to map the buffer at
* this location the submit will fail. This means userspace is responsible
* for the whole gpu virtual address management.
*/
#define ETNA_SUBMIT_BO_READ 0x0001
#define ETNA_SUBMIT_BO_WRITE 0x0002
struct drm_etnaviv_gem_submit_bo {
__u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */
__u32 handle; /* in, GEM handle */
__u64 presumed; /* in/out, presumed buffer address */
};
/* performance monitor request (pmr) */
#define ETNA_PM_PROCESS_PRE 0x0001
#define ETNA_PM_PROCESS_POST 0x0002
struct drm_etnaviv_gem_submit_pmr {
__u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */
__u8 domain; /* in, pm domain */
__u8 pad;
__u16 signal; /* in, pm signal */
__u32 sequence; /* in, sequence number */
__u32 read_offset; /* in, offset from read_bo */
__u32 read_idx; /* in, index of read_bo buffer */
};
/* Each cmdstream submit consists of a table of buffers involved, and
* one or more cmdstream buffers. This allows for conditional execution
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
*/
#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
#define ETNA_SUBMIT_SOFTPIN 0x0008
#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
ETNA_SUBMIT_FENCE_FD_IN | \
ETNA_SUBMIT_FENCE_FD_OUT| \
ETNA_SUBMIT_SOFTPIN)
#define ETNA_PIPE_3D 0x00
#define ETNA_PIPE_2D 0x01
#define ETNA_PIPE_VG 0x02
struct drm_etnaviv_gem_submit {
__u32 fence; /* out */
__u32 pipe; /* in */
__u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */
__u32 nr_bos; /* in, number of submit_bo's */
__u32 nr_relocs; /* in, number of submit_reloc's */
__u32 stream_size; /* in, cmdstream size */
__u64 bos; /* in, ptr to array of submit_bo's */
__u64 relocs; /* in, ptr to array of submit_reloc's */
__u64 stream; /* in, ptr to cmdstream */
__u32 flags; /* in, mask of ETNA_SUBMIT_x */
__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
__u64 pmrs; /* in, ptr to array of submit_pmr's */
__u32 nr_pmrs; /* in, number of submit_pmr's */
__u32 pad;
};
/* The normal way to synchronize with the GPU is just to CPU_PREP on
* a buffer if you need to access it from the CPU (other cmdstream
* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
* handle the required synchronization under the hood). This ioctl
* mainly just exists as a way to implement the gallium pipe_fence
* APIs without requiring a dummy bo to synchronize on.
*/
#define ETNA_WAIT_NONBLOCK 0x01
struct drm_etnaviv_wait_fence {
__u32 pipe; /* in */
__u32 fence; /* in */
__u32 flags; /* in, mask of ETNA_WAIT_x */
__u32 pad;
struct drm_etnaviv_timespec timeout; /* in */
};
#define ETNA_USERPTR_READ 0x01
#define ETNA_USERPTR_WRITE 0x02
struct drm_etnaviv_gem_userptr {
__u64 user_ptr; /* in, page aligned user pointer */
__u64 user_size; /* in, page aligned user size */
__u32 flags; /* in, flags */
__u32 handle; /* out, non-zero handle */
};
struct drm_etnaviv_gem_wait {
__u32 pipe; /* in */
__u32 handle; /* in, bo to be waited for */
__u32 flags; /* in, mask of ETNA_WAIT_x */
__u32 pad;
struct drm_etnaviv_timespec timeout; /* in */
};
/*
* Performance Monitor (PM):
*/
struct drm_etnaviv_pm_domain {
__u32 pipe; /* in */
__u8 iter; /* in/out, select pm domain at index iter */
__u8 id; /* out, id of domain */
__u16 nr_signals; /* out, how many signals does this domain provide */
char name[64]; /* out, name of domain */
};
struct drm_etnaviv_pm_signal {
__u32 pipe; /* in */
__u8 domain; /* in, pm domain index */
__u8 pad;
__u16 iter; /* in/out, select pm source at index iter */
__u16 id; /* out, id of signal */
char name[64]; /* out, name of domain */
};
#define DRM_ETNAVIV_GET_PARAM 0x00
/* placeholder:
#define DRM_ETNAVIV_SET_PARAM 0x01
*/
#define DRM_ETNAVIV_GEM_NEW 0x02
#define DRM_ETNAVIV_GEM_INFO 0x03
#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
#define DRM_ETNAVIV_GEM_SUBMIT 0x06
#define DRM_ETNAVIV_WAIT_FENCE 0x07
#define DRM_ETNAVIV_GEM_USERPTR 0x08
#define DRM_ETNAVIV_GEM_WAIT 0x09
#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
#if defined(__cplusplus)
}
#endif
#endif /* __ETNAVIV_DRM_H__ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/gpu_scheduler.h
+44
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _DRM_GPU_SCHEDULER_H_
#define _DRM_GPU_SCHEDULER_H_
/* Only leaving the important enum definition to avoid pull in several Linux
* specific headers
*/
/* These are often used as an (initial) index
* to an array, and as such should start at 0.
*/
enum drm_sched_priority {
DRM_SCHED_PRIORITY_MIN,
DRM_SCHED_PRIORITY_NORMAL,
DRM_SCHED_PRIORITY_HIGH,
DRM_SCHED_PRIORITY_KERNEL,
DRM_SCHED_PRIORITY_COUNT,
DRM_SCHED_PRIORITY_UNSET = -2
};
#endif
local/recipes/dev/mesa-clc/source/include/drm-uapi/i915_drm.h
+3916
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local/recipes/dev/mesa-clc/source/include/drm-uapi/lima_drm.h
+176
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@@ -0,0 +1,176 @@
/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
#ifndef __LIMA_DRM_H__
#define __LIMA_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
enum drm_lima_param_gpu_id {
DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
DRM_LIMA_PARAM_GPU_ID_MALI400,
DRM_LIMA_PARAM_GPU_ID_MALI450,
};
enum drm_lima_param {
DRM_LIMA_PARAM_GPU_ID,
DRM_LIMA_PARAM_NUM_PP,
DRM_LIMA_PARAM_GP_VERSION,
DRM_LIMA_PARAM_PP_VERSION,
};
/**
* get various information of the GPU
*/
struct drm_lima_get_param {
__u32 param; /* in, value in enum drm_lima_param */
__u32 pad; /* pad, must be zero */
__u64 value; /* out, parameter value */
};
/*
* heap buffer dynamically increase backup memory size when GP task fail
* due to lack of heap memory. size field of heap buffer is an up bound of
* the backup memory which can be set to a fairly large value.
*/
#define LIMA_BO_FLAG_HEAP (1 << 0)
/**
* create a buffer for used by GPU
*/
struct drm_lima_gem_create {
__u32 size; /* in, buffer size */
__u32 flags; /* in, buffer flags */
__u32 handle; /* out, GEM buffer handle */
__u32 pad; /* pad, must be zero */
};
/**
* get information of a buffer
*/
struct drm_lima_gem_info {
__u32 handle; /* in, GEM buffer handle */
__u32 va; /* out, virtual address mapped into GPU MMU */
__u64 offset; /* out, used to mmap this buffer to CPU */
};
#define LIMA_SUBMIT_BO_READ 0x01
#define LIMA_SUBMIT_BO_WRITE 0x02
/* buffer information used by one task */
struct drm_lima_gem_submit_bo {
__u32 handle; /* in, GEM buffer handle */
__u32 flags; /* in, buffer read/write by GPU */
};
#define LIMA_GP_FRAME_REG_NUM 6
/* frame used to setup GP for each task */
struct drm_lima_gp_frame {
__u32 frame[LIMA_GP_FRAME_REG_NUM];
};
#define LIMA_PP_FRAME_REG_NUM 23
#define LIMA_PP_WB_REG_NUM 12
/* frame used to setup mali400 GPU PP for each task */
struct drm_lima_m400_pp_frame {
__u32 frame[LIMA_PP_FRAME_REG_NUM];
__u32 num_pp;
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
__u32 plbu_array_address[4];
__u32 fragment_stack_address[4];
};
/* frame used to setup mali450 GPU PP for each task */
struct drm_lima_m450_pp_frame {
__u32 frame[LIMA_PP_FRAME_REG_NUM];
__u32 num_pp;
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
__u32 use_dlbu;
__u32 _pad;
union {
__u32 plbu_array_address[8];
__u32 dlbu_regs[4];
};
__u32 fragment_stack_address[8];
};
#define LIMA_PIPE_GP 0x00
#define LIMA_PIPE_PP 0x01
#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
/**
* submit a task to GPU
*
* User can always merge multi sync_file and drm_syncobj
* into one drm_syncobj as in_sync[0], but we reserve
* in_sync[1] for another task's out_sync to avoid the
* export/import/merge pass when explicit sync.
*/
struct drm_lima_gem_submit {
__u32 ctx; /* in, context handle task is submitted to */
__u32 pipe; /* in, which pipe to use, GP/PP */
__u32 nr_bos; /* in, array length of bos field */
__u32 frame_size; /* in, size of frame field */
__u64 bos; /* in, array of drm_lima_gem_submit_bo */
__u64 frame; /* in, GP/PP frame */
__u32 flags; /* in, submit flags */
__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
};
#define LIMA_GEM_WAIT_READ 0x01
#define LIMA_GEM_WAIT_WRITE 0x02
/**
* wait pending GPU task finish of a buffer
*/
struct drm_lima_gem_wait {
__u32 handle; /* in, GEM buffer handle */
__u32 op; /* in, CPU want to read/write this buffer */
__s64 timeout_ns; /* in, wait timeout in absulute time */
};
/**
* create a context
*/
struct drm_lima_ctx_create {
__u32 id; /* out, context handle */
__u32 _pad; /* pad, must be zero */
};
/**
* free a context
*/
struct drm_lima_ctx_free {
__u32 id; /* in, context handle */
__u32 _pad; /* pad, must be zero */
};
#define DRM_LIMA_GET_PARAM 0x00
#define DRM_LIMA_GEM_CREATE 0x01
#define DRM_LIMA_GEM_INFO 0x02
#define DRM_LIMA_GEM_SUBMIT 0x03
#define DRM_LIMA_GEM_WAIT 0x04
#define DRM_LIMA_CTX_CREATE 0x05
#define DRM_LIMA_CTX_FREE 0x06
#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
#if defined(__cplusplus)
}
#endif
#endif /* __LIMA_DRM_H__ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/msm_drm.h
+528
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/*
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints:
* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
* user/kernel compatibility
* 2) Keep fields aligned to their size
* 3) Because of how drm_ioctl() works, we can add new fields at
* the end of an ioctl if some care is taken: drm_ioctl() will
* zero out the new fields at the tail of the ioctl, so a zero
* value should have a backwards compatible meaning. And for
* output params, userspace won't see the newly added output
* fields.. so that has to be somehow ok.
*/
#define MSM_PIPE_NONE 0x00
#define MSM_PIPE_2D0 0x01
#define MSM_PIPE_2D1 0x02
#define MSM_PIPE_3D0 0x10
/* The pipe-id just uses the lower bits, so can be OR'd with flags in
* the upper 16 bits (which could be extended further, if needed, maybe
* we extend/overload the pipe-id some day to deal with multiple rings,
* but even then I don't think we need the full lower 16 bits).
*/
#define MSM_PIPE_ID_MASK 0xffff
#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
/* timeouts are specified in clock-monotonic absolute times (to simplify
* restarting interrupted ioctls). The following struct is logically the
* same as 'struct timespec' but 32/64b ABI safe.
*/
struct drm_msm_timespec {
__s64 tv_sec; /* seconds */
__s64 tv_nsec; /* nanoseconds */
};
/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
* "RW" indicates a param that can be both read (GET_PARAM) and written
* (SET_PARAM)
*/
#define MSM_PARAM_GPU_ID 0x01 /* RO */
#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
#define MSM_PARAM_CHIP_ID 0x03 /* RO */
#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
#define MSM_PARAM_FAULTS 0x09 /* RO */
#define MSM_PARAM_SUSPENDS 0x0a /* RO */
#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
#define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
#define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */
#define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
#define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */
#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
#define MSM_PARAM_RAYTRACING 0x11 /* RO */
#define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */
#define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */
#define MSM_PARAM_UCHE_TRAP_BASE 0x14 /* RO */
/* PRR (Partially Resident Region) is required for sparse residency: */
#define MSM_PARAM_HAS_PRR 0x15 /* RO */
/* MSM_PARAM_EN_VM_BIND is set to 1 to enable VM_BIND ops.
*
* With VM_BIND enabled, userspace is required to allocate iova and use the
* VM_BIND ops for map/unmap ioctls. MSM_INFO_SET_IOVA and MSM_INFO_GET_IOVA
* will be rejected. (The latter does not have a sensible meaning when a BO
* can have multiple and/or partial mappings.)
*
* With VM_BIND enabled, userspace does not include a submit_bo table in the
* SUBMIT ioctl (this will be rejected), the resident set is determined by
* the the VM_BIND ops.
*
* Enabling VM_BIND will fail on devices which do not have per-process pgtables.
* And it is not allowed to disable VM_BIND once it has been enabled.
*
* Enabling VM_BIND should be done (attempted) prior to allocating any BOs or
* submitqueues of type MSM_SUBMITQUEUE_VM_BIND.
*
* Relatedly, when VM_BIND mode is enabled, the kernel will not try to recover
* from GPU faults or failed async VM_BIND ops, in particular because it is
* difficult to communicate to userspace which op failed so that userspace
* could rewind and try again. When the VM is marked unusable, the SUBMIT
* ioctl will throw -EPIPE.
*/
#define MSM_PARAM_EN_VM_BIND 0x16 /* WO, once */
/* For backwards compat. The original support for preemption was based on
* a single ring per priority level so # of priority levels equals the #
* of rings. With drm/scheduler providing additional levels of priority,
* the number of priorities is greater than the # of rings. The param is
* renamed to better reflect this.
*/
#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
struct drm_msm_param {
__u32 pipe; /* in, MSM_PIPE_x */
__u32 param; /* in, MSM_PARAM_x */
__u64 value; /* out (get_param) or in (set_param) */
__u32 len; /* zero for non-pointer params */
__u32 pad; /* must be zero */
};
/*
* GEM buffers:
*/
#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
#define MSM_BO_GPU_READONLY 0x00000002
/* Private buffers do not need to be explicitly listed in the SUBMIT
* ioctl, unless referenced by a drm_msm_gem_submit_cmd. Private
* buffers may NOT be imported/exported or used for scanout (or any
* other situation where buffers can be indefinitely pinned, but
* cases other than scanout are all kernel owned BOs which are not
* visible to userspace).
*
* In exchange for those constraints, all private BOs associated with
* a single context (drm_file) share a single dma_resv, and if there
* has been no eviction since the last submit, there are no per-BO
* bookeeping to do, significantly cutting the SUBMIT overhead.
*/
#define MSM_BO_NO_SHARE 0x00000004
#define MSM_BO_CACHE_MASK 0x000f0000
/* cache modes */
#define MSM_BO_CACHED 0x00010000
#define MSM_BO_WC 0x00020000
#define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
#define MSM_BO_CACHED_COHERENT 0x080000
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
MSM_BO_GPU_READONLY | \
MSM_BO_NO_SHARE | \
MSM_BO_CACHE_MASK)
struct drm_msm_gem_new {
__u64 size; /* in */
__u32 flags; /* in, mask of MSM_BO_x */
__u32 handle; /* out */
};
/* Get or set GEM buffer info. The requested value can be passed
* directly in 'value', or for data larger than 64b 'value' is a
* pointer to userspace buffer, with 'len' specifying the number of
* bytes copied into that buffer. For info returned by pointer,
* calling the GEM_INFO ioctl with null 'value' will return the
* required buffer size in 'len'
*/
#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
#define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */
#define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */
struct drm_msm_gem_info {
__u32 handle; /* in */
__u32 info; /* in - one of MSM_INFO_* */
__u64 value; /* in or out */
__u32 len; /* in or out */
__u32 pad;
};
#define MSM_PREP_READ 0x01
#define MSM_PREP_WRITE 0x02
#define MSM_PREP_NOSYNC 0x04
#define MSM_PREP_BOOST 0x08
#define MSM_PREP_FLAGS (MSM_PREP_READ | \
MSM_PREP_WRITE | \
MSM_PREP_NOSYNC | \
MSM_PREP_BOOST | \
0)
struct drm_msm_gem_cpu_prep {
__u32 handle; /* in */
__u32 op; /* in, mask of MSM_PREP_x */
struct drm_msm_timespec timeout; /* in */
};
struct drm_msm_gem_cpu_fini {
__u32 handle; /* in */
};
/*
* Cmdstream Submission:
*/
#define MSM_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
#define MSM_SYNCOBJ_FLAGS ( \
MSM_SYNCOBJ_RESET | \
0)
struct drm_msm_syncobj {
__u32 handle; /* in, syncobj handle. */
__u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
__u64 point; /* in, timepoint for timeline syncobjs. */
};
/* The value written into the cmdstream is logically:
*
* ((relocbuf->gpuaddr + reloc_offset) << shift) | or
*
* When we have GPU's w/ >32bit ptrs, it should be possible to deal
* with this by emit'ing two reloc entries with appropriate shift
* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
*
* NOTE that reloc's must be sorted by order of increasing submit_offset,
* otherwise EINVAL.
*/
struct drm_msm_gem_submit_reloc {
__u32 submit_offset; /* in, offset from submit_bo */
#ifdef __cplusplus
__u32 _or; /* in, value OR'd with result */
#else
__u32 or; /* in, value OR'd with result */
#endif
__s32 shift; /* in, amount of left shift (can be negative) */
__u32 reloc_idx; /* in, index of reloc_bo buffer */
__u64 reloc_offset; /* in, offset from start of reloc_bo */
};
/* submit-types:
* BUF - this cmd buffer is executed normally.
* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
* processed normally, but the kernel does not setup an IB to
* this buffer in the first-level ringbuffer
* CTX_RESTORE_BUF - only executed if there has been a GPU context
* switch since the last SUBMIT ioctl
*/
#define MSM_SUBMIT_CMD_BUF 0x0001
#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
struct drm_msm_gem_submit_cmd {
__u32 type; /* in, one of MSM_SUBMIT_CMD_x */
__u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
__u32 submit_offset; /* in, offset into submit_bo */
__u32 size; /* in, cmdstream size */
__u32 pad;
__u32 nr_relocs; /* in, number of submit_reloc's */
union {
__u64 relocs; /* in, ptr to array of submit_reloc's */
__u64 iova; /* cmdstream address (for VM_BIND contexts) */
};
};
/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
* cmdstream buffer(s) themselves or reloc entries) has one (and only
* one) entry in the submit->bos[] table.
*
* As a optimization, the current buffer (gpu virtual address) can be
* passed back through the 'presumed' field. If on a subsequent reloc,
* userspace passes back a 'presumed' address that is still valid,
* then patching the cmdstream for this entry is skipped. This can
* avoid kernel needing to map/access the cmdstream bo in the common
* case.
*/
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE 0x0002
#define MSM_SUBMIT_BO_DUMP 0x0004
#define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
MSM_SUBMIT_BO_WRITE | \
MSM_SUBMIT_BO_DUMP | \
MSM_SUBMIT_BO_NO_IMPLICIT)
struct drm_msm_gem_submit_bo {
__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
__u32 handle; /* in, GEM handle */
__u64 presumed; /* in/out, presumed buffer address */
};
/* Valid submit ioctl flags: */
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
#define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
#define MSM_SUBMIT_FLAGS ( \
MSM_SUBMIT_NO_IMPLICIT | \
MSM_SUBMIT_FENCE_FD_IN | \
MSM_SUBMIT_FENCE_FD_OUT | \
MSM_SUBMIT_SUDO | \
MSM_SUBMIT_SYNCOBJ_IN | \
MSM_SUBMIT_SYNCOBJ_OUT | \
MSM_SUBMIT_FENCE_SN_IN | \
0)
/* Each cmdstream submit consists of a table of buffers involved, and
* one or more cmdstream buffers. This allows for conditional execution
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
*/
struct drm_msm_gem_submit {
__u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
__u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
__u32 nr_bos; /* in, number of submit_bo's */
__u32 nr_cmds; /* in, number of submit_cmd's */
__u64 bos; /* in, ptr to array of submit_bo's */
__u64 cmds; /* in, ptr to array of submit_cmd's */
__s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
__u32 queueid; /* in, submitqueue id */
__u64 in_syncobjs; /* in, ptr to array of drm_msm_syncobj */
__u64 out_syncobjs; /* in, ptr to array of drm_msm_syncobj */
__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
__u32 syncobj_stride; /* in, stride of syncobj arrays. */
__u32 pad; /*in, reserved for future use, always 0. */
};
#define MSM_VM_BIND_OP_UNMAP 0
#define MSM_VM_BIND_OP_MAP 1
#define MSM_VM_BIND_OP_MAP_NULL 2
#define MSM_VM_BIND_OP_DUMP 1
#define MSM_VM_BIND_OP_FLAGS ( \
MSM_VM_BIND_OP_DUMP | \
0)
/**
* struct drm_msm_vm_bind_op - bind/unbind op to run
*/
struct drm_msm_vm_bind_op {
/** @op: one of MSM_VM_BIND_OP_x */
__u32 op;
/** @handle: GEM object handle, MBZ for UNMAP or MAP_NULL */
__u32 handle;
/** @obj_offset: Offset into GEM object, MBZ for UNMAP or MAP_NULL */
__u64 obj_offset;
/** @iova: Address to operate on */
__u64 iova;
/** @range: Number of bites to to map/unmap */
__u64 range;
/** @flags: Bitmask of MSM_VM_BIND_OP_FLAG_x */
__u32 flags;
/** @pad: MBZ */
__u32 pad;
};
#define MSM_VM_BIND_FENCE_FD_IN 0x00000001
#define MSM_VM_BIND_FENCE_FD_OUT 0x00000002
#define MSM_VM_BIND_FLAGS ( \
MSM_VM_BIND_FENCE_FD_IN | \
MSM_VM_BIND_FENCE_FD_OUT | \
0)
/**
* struct drm_msm_vm_bind - Input of &DRM_IOCTL_MSM_VM_BIND
*/
struct drm_msm_vm_bind {
/** @flags: in, bitmask of MSM_VM_BIND_x */
__u32 flags;
/** @nr_ops: the number of bind ops in this ioctl */
__u32 nr_ops;
/** @fence_fd: in/out fence fd (see MSM_VM_BIND_FENCE_FD_IN/OUT) */
__s32 fence_fd;
/** @queue_id: in, submitqueue id */
__u32 queue_id;
/** @in_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
__u64 in_syncobjs;
/** @out_syncobjs: in, ptr to array of drm_msm_gem_syncobj */
__u64 out_syncobjs;
/** @nr_in_syncobjs: in, number of entries in in_syncobj */
__u32 nr_in_syncobjs;
/** @nr_out_syncobjs: in, number of entries in out_syncobj */
__u32 nr_out_syncobjs;
/** @syncobj_stride: in, stride of syncobj arrays */
__u32 syncobj_stride;
/** @op_stride: sizeof each struct drm_msm_vm_bind_op in @ops */
__u32 op_stride;
union {
/** @op: used if num_ops == 1 */
struct drm_msm_vm_bind_op op;
/** @ops: userptr to array of drm_msm_vm_bind_op if num_ops > 1 */
__u64 ops;
};
};
#define MSM_WAIT_FENCE_BOOST 0x00000001
#define MSM_WAIT_FENCE_FLAGS ( \
MSM_WAIT_FENCE_BOOST | \
0)
/* The normal way to synchronize with the GPU is just to CPU_PREP on
* a buffer if you need to access it from the CPU (other cmdstream
* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
* handle the required synchronization under the hood). This ioctl
* mainly just exists as a way to implement the gallium pipe_fence
* APIs without requiring a dummy bo to synchronize on.
*/
struct drm_msm_wait_fence {
__u32 fence; /* in */
__u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */
struct drm_msm_timespec timeout; /* in */
__u32 queueid; /* in, submitqueue id */
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
#define __MSM_MADV_PURGED 2 /* internal state */
struct drm_msm_gem_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, MSM_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
/*
* Draw queues allow the user to set specific submission parameter. Command
* submissions specify a specific submitqueue to use. ID 0 is reserved for
* backwards compatibility as a "default" submitqueue.
*
* Because VM_BIND async updates happen on the CPU, they must run on a
* virtual queue created with the flag MSM_SUBMITQUEUE_VM_BIND. If we had
* a way to do pgtable updates on the GPU, we could drop this restriction.
*/
#define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001
#define MSM_SUBMITQUEUE_VM_BIND 0x00000002 /* virtual queue for VM_BIND ops */
#define MSM_SUBMITQUEUE_FLAGS ( \
MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
MSM_SUBMITQUEUE_VM_BIND | \
0)
/*
* The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
* a lower numeric value is higher priority.
*/
struct drm_msm_submitqueue {
__u32 flags; /* in, MSM_SUBMITQUEUE_x */
__u32 prio; /* in, Priority level */
__u32 id; /* out, identifier */
};
#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
struct drm_msm_submitqueue_query {
__u64 data;
__u32 id;
__u32 param;
__u32 len;
__u32 pad;
};
#define DRM_MSM_GET_PARAM 0x00
#define DRM_MSM_SET_PARAM 0x01
#define DRM_MSM_GEM_NEW 0x02
#define DRM_MSM_GEM_INFO 0x03
#define DRM_MSM_GEM_CPU_PREP 0x04
#define DRM_MSM_GEM_CPU_FINI 0x05
#define DRM_MSM_GEM_SUBMIT 0x06
#define DRM_MSM_WAIT_FENCE 0x07
#define DRM_MSM_GEM_MADVISE 0x08
/* placeholder:
#define DRM_MSM_GEM_SVM_NEW 0x09
*/
#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
#define DRM_MSM_VM_BIND 0x0D
#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
#define DRM_IOCTL_MSM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind)
#if defined(__cplusplus)
}
#endif
#endif /* __MSM_DRM_H__ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/nouveau_drm.h
+586
View File
@@ -0,0 +1,586 @@
/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__
#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define NOUVEAU_GETPARAM_PCI_VENDOR 3
#define NOUVEAU_GETPARAM_PCI_DEVICE 4
#define NOUVEAU_GETPARAM_BUS_TYPE 5
#define NOUVEAU_GETPARAM_FB_SIZE 8
#define NOUVEAU_GETPARAM_AGP_SIZE 9
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
/*
* NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
*
* Query the maximum amount of IBs that can be pushed through a single
* &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
* ioctl().
*/
#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
/*
* NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size
*
* Query the VRAM BAR size.
*/
#define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
/*
* NOUVEAU_GETPARAM_VRAM_USED
*
* Get remaining VRAM size.
*/
#define NOUVEAU_GETPARAM_VRAM_USED 19
/*
* NOUVEAU_GETPARAM_HAS_VMA_TILEMODE
*
* Query whether tile mode and PTE kind are accepted with VM allocs or not.
*/
#define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
struct drm_nouveau_getparam {
__u64 param;
__u64 value;
};
/*
* Those are used to support selecting the main engine used on Kepler.
* This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle
*/
#define NOUVEAU_FIFO_ENGINE_GR 0x01
#define NOUVEAU_FIFO_ENGINE_VP 0x02
#define NOUVEAU_FIFO_ENGINE_PPP 0x04
#define NOUVEAU_FIFO_ENGINE_BSP 0x08
#define NOUVEAU_FIFO_ENGINE_CE 0x30
struct drm_nouveau_channel_alloc {
__u32 fb_ctxdma_handle;
__u32 tt_ctxdma_handle;
__s32 channel;
__u32 pushbuf_domains;
/* Notifier memory */
__u32 notifier_handle;
/* DRM-enforced subchannel assignments */
struct {
__u32 handle;
__u32 grclass;
} subchan[8];
__u32 nr_subchan;
};
struct drm_nouveau_channel_free {
__s32 channel;
};
struct drm_nouveau_notifierobj_alloc {
__u32 channel;
__u32 handle;
__u32 size;
__u32 offset;
};
struct drm_nouveau_gpuobj_free {
__s32 channel;
__u32 handle;
};
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
/* The BO will never be shared via import or export. */
#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
#define NOUVEAU_GEM_TILE_16BPP 0x00000001
#define NOUVEAU_GEM_TILE_32BPP 0x00000002
#define NOUVEAU_GEM_TILE_ZETA 0x00000004
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
struct drm_nouveau_gem_info {
__u32 handle;
__u32 domain;
__u64 size;
__u64 offset;
__u64 map_handle;
__u32 tile_mode;
__u32 tile_flags;
};
struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info;
__u32 channel_hint;
__u32 align;
};
#define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed {
__u32 valid;
__u32 domain;
__u64 offset;
};
struct drm_nouveau_gem_pushbuf_bo {
__u64 user_priv;
__u32 handle;
__u32 read_domains;
__u32 write_domains;
__u32 valid_domains;
struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
};
#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
#define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc {
__u32 reloc_bo_index;
__u32 reloc_bo_offset;
__u32 bo_index;
__u32 flags;
__u32 data;
__u32 vor;
__u32 tor;
};
#define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push {
__u32 bo_index;
__u32 pad;
__u64 offset;
__u64 length;
#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
};
struct drm_nouveau_gem_pushbuf {
__u32 channel;
__u32 nr_buffers;
__u64 buffers;
__u32 nr_relocs;
__u32 nr_push;
__u64 relocs;
__u64 push;
__u32 suffix0;
__u32 suffix1;
#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
__u64 vram_available;
__u64 gart_available;
};
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep {
__u32 handle;
__u32 flags;
};
struct drm_nouveau_gem_cpu_fini {
__u32 handle;
};
/**
* struct drm_nouveau_sync - sync object
*
* This structure serves as synchronization mechanism for (potentially)
* asynchronous operations such as EXEC or VM_BIND.
*/
struct drm_nouveau_sync {
/**
* @flags: the flags for a sync object
*
* The first 8 bits are used to determine the type of the sync object.
*/
__u32 flags;
#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
/**
* @handle: the handle of the sync object
*/
__u32 handle;
/**
* @timeline_value:
*
* The timeline point of the sync object in case the syncobj is of
* type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
*/
__u64 timeline_value;
};
/**
* struct drm_nouveau_vm_init - GPU VA space init structure
*
* Used to initialize the GPU's VA space for a user client, telling the kernel
* which portion of the VA space is managed by the UMD and kernel respectively.
*
* For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
* channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
* with -ENOSYS.
*/
struct drm_nouveau_vm_init {
/**
* @kernel_managed_addr: start address of the kernel managed VA space
* region
*/
__u64 kernel_managed_addr;
/**
* @kernel_managed_size: size of the kernel managed VA space region in
* bytes
*/
__u64 kernel_managed_size;
};
/**
* struct drm_nouveau_vm_bind_op - VM_BIND operation
*
* This structure represents a single VM_BIND operation. UMDs should pass
* an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
*/
struct drm_nouveau_vm_bind_op {
/**
* @op: the operation type
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA
* space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be
* passed to instruct the kernel to create sparse mappings for the
* given range.
*
* %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the
* GPU's VA space. If the region the mapping is located in is a
* sparse region, new sparse mappings are created where the unmapped
* (memory backed) mapping was mapped previously. To remove a sparse
* region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
*/
__u32 op;
#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
/**
* @flags: the flags for a &drm_nouveau_vm_bind_op
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA
* space region should be sparse.
*/
__u32 flags;
#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
/**
* @handle: the handle of the DRM GEM object to map
*/
__u32 handle;
/**
* @pad: 32 bit padding, should be 0
*/
__u32 pad;
/**
* @addr:
*
* the address the VA space region or (memory backed) mapping should be mapped to
*/
__u64 addr;
/**
* @bo_offset: the offset within the BO backing the mapping
*/
__u64 bo_offset;
/**
* @range: the size of the requested mapping in bytes
*/
__u64 range;
};
/**
* struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
*/
struct drm_nouveau_vm_bind {
/**
* @op_count: the number of &drm_nouveau_vm_bind_op
*/
__u32 op_count;
/**
* @flags: the flags for a &drm_nouveau_vm_bind ioctl
*
* Supported values:
*
* %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND
* operation should be executed asynchronously by the kernel.
*
* If this flag is not supplied the kernel executes the associated
* operations synchronously and doesn't accept any &drm_nouveau_sync
* objects.
*/
__u32 flags;
#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
/**
* @wait_count: the number of wait &drm_nouveau_syncs
*/
__u32 wait_count;
/**
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
*/
__u32 sig_count;
/**
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
*/
__u64 wait_ptr;
/**
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
*/
__u64 sig_ptr;
/**
* @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
*/
__u64 op_ptr;
};
/**
* struct drm_nouveau_exec_push - EXEC push operation
*
* This structure represents a single EXEC push operation. UMDs should pass an
* array of this structure via struct drm_nouveau_exec's &push_ptr field.
*/
struct drm_nouveau_exec_push {
/**
* @va: the virtual address of the push buffer mapping
*/
__u64 va;
/**
* @va_len: the length of the push buffer mapping
*/
__u32 va_len;
/**
* @flags: the flags for this push buffer mapping
*/
__u32 flags;
#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
};
/**
* struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
*/
struct drm_nouveau_exec {
/**
* @channel: the channel to execute the push buffer in
*/
__u32 channel;
/**
* @push_count: the number of &drm_nouveau_exec_push ops
*/
__u32 push_count;
/**
* @wait_count: the number of wait &drm_nouveau_syncs
*/
__u32 wait_count;
/**
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
*/
__u32 sig_count;
/**
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
*/
__u64 wait_ptr;
/**
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
*/
__u64 sig_ptr;
/**
* @push_ptr: pointer to &drm_nouveau_exec_push ops
*/
__u64 push_ptr;
};
struct drm_nouveau_get_zcull_info {
/**
* @width_align_pixels: required alignment for region widths, in pixels
* (typically #TPC's * 16).
*/
__u32 width_align_pixels;
/**
* @height_align_pixels: required alignment for region heights, in
* pixels (typically 32).
*/
__u32 height_align_pixels;
/**
* @pixel_squares_by_aliquots: the pixel area covered by an aliquot
* (typically #Zcull_banks * 16 * 16).
*/
__u32 pixel_squares_by_aliquots;
/**
* @aliquot_total: the total aliquot pool available in hardware
*/
__u32 aliquot_total;
/**
* @zcull_region_byte_multiplier: the size of an aliquot in bytes, which
* is used for save/restore operations on a region
*/
__u32 zcull_region_byte_multiplier;
/**
* @zcull_region_header_size: the region header size in bytes, which is
* used for save/restore operations on a region
*/
__u32 zcull_region_header_size;
/**
* @zcull_subregion_header_size: the subregion header size in bytes,
* which is used for save/restore operations on a region
*/
__u32 zcull_subregion_header_size;
/**
* @subregion_count: the total number of subregions the hardware
* supports
*/
__u32 subregion_count;
/**
* @subregion_width_align_pixels: required alignment for subregion
* widths, in pixels (typically #TPC's * 16).
*/
__u32 subregion_width_align_pixels;
/**
* @subregion_height_align_pixels: required alignment for subregion
* heights, in pixels
*/
__u32 subregion_height_align_pixels;
/**
* @ctxsw_size: the size, in bytes, of a zcull context switching region.
* Will be zero if the kernel does not support zcull context switching.
*/
__u32 ctxsw_size;
/**
* @ctxsw_align: the alignment, in bytes, of a zcull context switching
* region
*/
__u32 ctxsw_align;
};
#define DRM_NOUVEAU_GETPARAM 0x00
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
#define DRM_NOUVEAU_NVIF 0x07
#define DRM_NOUVEAU_SVM_INIT 0x08
#define DRM_NOUVEAU_SVM_BIND 0x09
#define DRM_NOUVEAU_VM_INIT 0x10
#define DRM_NOUVEAU_VM_BIND 0x11
#define DRM_NOUVEAU_EXEC 0x12
#define DRM_NOUVEAU_GET_ZCULL_INFO 0x13
#define DRM_NOUVEAU_GEM_NEW 0x40
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_INFO 0x44
struct drm_nouveau_svm_init {
__u64 unmanaged_addr;
__u64 unmanaged_size;
};
struct drm_nouveau_svm_bind {
__u64 header;
__u64 va_start;
__u64 va_end;
__u64 npages;
__u64 stride;
__u64 result;
__u64 reserved0;
__u64 reserved1;
};
#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
#define NOUVEAU_SVM_BIND_TARGET_BITS 32
#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
/*
* Below is use to validate ioctl argument, userspace can also use it to make
* sure that no bit are set beyond known fields for a given kernel version.
*/
#define NOUVEAU_SVM_BIND_VALID_BITS 48
#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
/*
* NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
* result: number of page successfuly migrate to the target memory.
*/
#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
/*
* NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
*/
#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
#define DRM_IOCTL_NOUVEAU_GET_ZCULL_INFO DRM_IOR (DRM_COMMAND_BASE + DRM_NOUVEAU_GET_ZCULL_INFO, struct drm_nouveau_get_zcull_info)
#if defined(__cplusplus)
}
#endif
#endif /* __NOUVEAU_DRM_H__ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/panfrost_drm.h
+476
View File
@@ -0,0 +1,476 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2014-2018 Broadcom
* Copyright © 2019 Collabora ltd.
*/
#ifndef _PANFROST_DRM_H_
#define _PANFROST_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_PANFROST_SUBMIT 0x00
#define DRM_PANFROST_WAIT_BO 0x01
#define DRM_PANFROST_CREATE_BO 0x02
#define DRM_PANFROST_MMAP_BO 0x03
#define DRM_PANFROST_GET_PARAM 0x04
#define DRM_PANFROST_GET_BO_OFFSET 0x05
#define DRM_PANFROST_PERFCNT_ENABLE 0x06
#define DRM_PANFROST_PERFCNT_DUMP 0x07
#define DRM_PANFROST_MADVISE 0x08
#define DRM_PANFROST_SET_LABEL_BO 0x09
#define DRM_PANFROST_JM_CTX_CREATE 0x0a
#define DRM_PANFROST_JM_CTX_DESTROY 0x0b
#define DRM_PANFROST_SYNC_BO 0x0c
#define DRM_PANFROST_QUERY_BO_INFO 0x0d
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo)
#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo)
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise)
#define DRM_IOCTL_PANFROST_SET_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo)
#define DRM_IOCTL_PANFROST_JM_CTX_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_CREATE, struct drm_panfrost_jm_ctx_create)
#define DRM_IOCTL_PANFROST_JM_CTX_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_JM_CTX_DESTROY, struct drm_panfrost_jm_ctx_destroy)
#define DRM_IOCTL_PANFROST_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SYNC_BO, struct drm_panfrost_sync_bo)
#define DRM_IOCTL_PANFROST_QUERY_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_QUERY_BO_INFO, struct drm_panfrost_query_bo_info)
/*
* Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module
* param is set to true.
* All these ioctl(s) are subject to deprecation, so please don't rely on
* them for anything but debugging purpose.
*/
#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable)
#define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump)
#define PANFROST_JD_REQ_FS (1 << 0)
#define PANFROST_JD_REQ_CYCLE_COUNT (1 << 1)
/**
* struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute a render command list.
*/
struct drm_panfrost_submit {
/**
* @jc: Address to GPU mapping of job descriptor
*/
__u64 jc;
/**
* @in_syncs: An optional array of sync objects to wait on
* before starting this job.
*/
__u64 in_syncs;
/**
* @in_sync_count: Number of sync objects to wait on before
* starting this job.
*/
__u32 in_sync_count;
/**
* @out_sync: An optional sync object to place the completion fence in.
*/
__u32 out_sync;
/**
* @bo_handles: Pointer to a u32 array of the BOs that are
* referenced by the job.
*/
__u64 bo_handles;
/**
* @bo_handle_count: Number of BO handles passed in (size is
* that times 4).
*/
__u32 bo_handle_count;
/**
* @requirements: A combination of PANFROST_JD_REQ_*
*/
__u32 requirements;
/**
* @jm_ctx_handle: JM context handle. Zero if you want to use the
* default context.
*/
__u32 jm_ctx_handle;
/**
* @pad: Padding field. Must be zero.
*/
__u32 pad;
};
/**
* struct drm_panfrost_wait_bo - ioctl argument for waiting for
* completion of the last DRM_PANFROST_SUBMIT on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_panfrost_wait_bo {
/**
* @handle: Handle for the object to wait for.
*/
__u32 handle;
/**
* @pad: Padding, must be zero-filled.
*/
__u32 pad;
/**
* @timeout_ns: absolute number of nanoseconds to wait.
*/
__s64 timeout_ns;
};
/* Valid flags to pass to drm_panfrost_create_bo.
* PANFROST_BO_WB_MMAP can't be set if PANFROST_BO_HEAP is.
*/
#define PANFROST_BO_NOEXEC 1
#define PANFROST_BO_HEAP 2
#define PANFROST_BO_WB_MMAP 4
/**
* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
*
* The flags argument is a bit mask of PANFROST_BO_* flags.
*/
struct drm_panfrost_create_bo {
/**
* @size: size of shmem/BO area to create (bytes)
*/
__u32 size;
/**
* @flags: see PANFROST_BO_* flags
*/
__u32 flags;
/**
* @handle: Returned GEM handle for the BO.
*/
__u32 handle;
/**
* @pad: Padding, must be zero-filled.
*/
__u32 pad;
/**
* @offset: Returned offset for the BO in the GPU address space.
* This offset is private to the DRM fd and is valid for the
* lifetime of the GEM handle.
*
* This offset value will always be nonzero, since various HW
* units treat 0 specially.
*/
__u64 offset;
};
/**
* struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_panfrost_mmap_bo {
/**
* @handle: Handle for the object being mapped.
*/
__u32 handle;
/**
* @flags: currently not used (should be zero)
*/
__u32 flags;
/**
* @offset: offset into the drm node to use for subsequent mmap call.
*/
__u64 offset;
};
enum drm_panfrost_param {
DRM_PANFROST_PARAM_GPU_PROD_ID,
DRM_PANFROST_PARAM_GPU_REVISION,
DRM_PANFROST_PARAM_SHADER_PRESENT,
DRM_PANFROST_PARAM_TILER_PRESENT,
DRM_PANFROST_PARAM_L2_PRESENT,
DRM_PANFROST_PARAM_STACK_PRESENT,
DRM_PANFROST_PARAM_AS_PRESENT,
DRM_PANFROST_PARAM_JS_PRESENT,
DRM_PANFROST_PARAM_L2_FEATURES,
DRM_PANFROST_PARAM_CORE_FEATURES,
DRM_PANFROST_PARAM_TILER_FEATURES,
DRM_PANFROST_PARAM_MEM_FEATURES,
DRM_PANFROST_PARAM_MMU_FEATURES,
DRM_PANFROST_PARAM_THREAD_FEATURES,
DRM_PANFROST_PARAM_MAX_THREADS,
DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ,
DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ,
DRM_PANFROST_PARAM_COHERENCY_FEATURES,
DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
DRM_PANFROST_PARAM_TEXTURE_FEATURES1,
DRM_PANFROST_PARAM_TEXTURE_FEATURES2,
DRM_PANFROST_PARAM_TEXTURE_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES0,
DRM_PANFROST_PARAM_JS_FEATURES1,
DRM_PANFROST_PARAM_JS_FEATURES2,
DRM_PANFROST_PARAM_JS_FEATURES3,
DRM_PANFROST_PARAM_JS_FEATURES4,
DRM_PANFROST_PARAM_JS_FEATURES5,
DRM_PANFROST_PARAM_JS_FEATURES6,
DRM_PANFROST_PARAM_JS_FEATURES7,
DRM_PANFROST_PARAM_JS_FEATURES8,
DRM_PANFROST_PARAM_JS_FEATURES9,
DRM_PANFROST_PARAM_JS_FEATURES10,
DRM_PANFROST_PARAM_JS_FEATURES11,
DRM_PANFROST_PARAM_JS_FEATURES12,
DRM_PANFROST_PARAM_JS_FEATURES13,
DRM_PANFROST_PARAM_JS_FEATURES14,
DRM_PANFROST_PARAM_JS_FEATURES15,
DRM_PANFROST_PARAM_NR_CORE_GROUPS,
DRM_PANFROST_PARAM_THREAD_TLS_ALLOC,
DRM_PANFROST_PARAM_AFBC_FEATURES,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
DRM_PANFROST_PARAM_SELECTED_COHERENCY,
};
enum drm_panfrost_gpu_coherency {
DRM_PANFROST_GPU_COHERENCY_ACE_LITE = 0,
DRM_PANFROST_GPU_COHERENCY_ACE = 1,
DRM_PANFROST_GPU_COHERENCY_NONE = 31,
};
struct drm_panfrost_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
/*
* Returns the offset for the BO in the GPU address space for this DRM fd.
* This is the same value returned by drm_panfrost_create_bo, if that was called
* from this DRM fd.
*/
struct drm_panfrost_get_bo_offset {
__u32 handle;
__u32 pad;
__u64 offset;
};
struct drm_panfrost_perfcnt_enable {
__u32 enable;
/*
* On bifrost we have 2 sets of counters, this parameter defines the
* one to track.
*/
__u32 counterset;
};
struct drm_panfrost_perfcnt_dump {
__u64 buf_ptr;
};
/* madvise provides a way to tell the kernel in case a buffers contents
* can be discarded under memory pressure, which is useful for userspace
* bo cache where we want to optimistically hold on to buffer allocate
* and potential mmap, but allow the pages to be discarded under memory
* pressure.
*
* Typical usage would involve madvise(DONTNEED) when buffer enters BO
* cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
* In the WILLNEED case, 'retained' indicates to userspace whether the
* backing pages still exist.
*/
#define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
#define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */
struct drm_panfrost_madvise {
__u32 handle; /* in, GEM handle */
__u32 madv; /* in, PANFROST_MADV_x */
__u32 retained; /* out, whether backing store still exists */
};
/**
* struct drm_panfrost_set_label_bo - ioctl argument for labelling Panfrost BOs.
*/
struct drm_panfrost_set_label_bo {
/**
* @handle: Handle of the buffer object to label.
*/
__u32 handle;
/**
* @pad: Must be zero.
*/
__u32 pad;
/**
* @label: User pointer to a NUL-terminated string
*
* Length cannot be greater than 4096.
* NULL is permitted and means clear the label.
*/
__u64 label;
};
/* Valid flags to pass to drm_panfrost_bo_sync_op */
#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH 0
#define PANFROST_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE 1
/**
* struct drm_panthor_bo_flush_map_op - BO map sync op
*/
struct drm_panfrost_bo_sync_op {
/** @handle: Handle of the buffer object to sync. */
__u32 handle;
/** @type: Type of sync operation. */
__u32 type;
/**
* @offset: Offset into the BO at which the sync range starts.
*
* This will be rounded down to the nearest cache line as needed.
*/
__u32 offset;
/**
* @size: Size of the range to sync
*
* @size + @offset will be rounded up to the nearest cache line as
* needed.
*/
__u32 size;
};
/**
* struct drm_panfrost_sync_bo - ioctl argument for syncing BO maps
*/
struct drm_panfrost_sync_bo {
/** Array of struct drm_panfrost_bo_sync_op */
__u64 ops;
/** Number of BO sync ops */
__u32 op_count;
__u32 pad;
};
/** BO comes from a different subsystem. */
#define DRM_PANFROST_BO_IS_IMPORTED (1 << 0)
struct drm_panfrost_query_bo_info {
/** Handle of the object being queried. */
__u32 handle;
/** Extra flags that are not coming from the BO_CREATE ioctl(). */
__u32 extra_flags;
/** Flags passed at creation time. */
__u32 create_flags;
/** Will be zero on return. */
__u32 pad;
};
/* Definitions for coredump decoding in user space */
#define PANFROSTDUMP_MAJOR 1
#define PANFROSTDUMP_MINOR 0
#define PANFROSTDUMP_MAGIC 0x464E4150 /* PANF */
#define PANFROSTDUMP_BUF_REG 0
#define PANFROSTDUMP_BUF_BOMAP (PANFROSTDUMP_BUF_REG + 1)
#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1)
#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1)
/*
* This structure is the native endianness of the dumping machine, tools can
* detect the endianness by looking at the value in 'magic'.
*/
struct panfrost_dump_object_header {
__u32 magic;
__u32 type;
__u32 file_size;
__u32 file_offset;
union {
struct {
__u64 jc;
__u32 gpu_id;
__u32 major;
__u32 minor;
__u64 nbos;
} reghdr;
struct {
__u32 valid;
__u64 iova;
__u32 data[2];
} bomap;
/*
* Force same size in case we want to expand the header
* with new fields and also keep it 512-byte aligned
*/
__u32 sizer[496];
};
};
/* Registers object, an array of these */
struct panfrost_dump_registers {
__u32 reg;
__u32 value;
};
enum drm_panfrost_jm_ctx_priority {
/**
* @PANFROST_JM_CTX_PRIORITY_LOW: Low priority context.
*/
PANFROST_JM_CTX_PRIORITY_LOW = 0,
/**
* @PANFROST_JM_CTX_PRIORITY_MEDIUM: Medium priority context.
*/
PANFROST_JM_CTX_PRIORITY_MEDIUM,
/**
* @PANFROST_JM_CTX_PRIORITY_HIGH: High priority context.
*
* Requires CAP_SYS_NICE or DRM_MASTER.
*/
PANFROST_JM_CTX_PRIORITY_HIGH,
};
struct drm_panfrost_jm_ctx_create {
/**
* @handle: Handle of the created JM context
*/
__u32 handle;
/**
* @priority: Context priority (see enum drm_panfrost_jm_ctx_priority).
*/
__u32 priority;
};
struct drm_panfrost_jm_ctx_destroy {
/**
* @handle: Handle of the JM context to destroy.
*
* Must be a valid context handle returned by DRM_IOCTL_PANTHOR_JM_CTX_CREATE.
*/
__u32 handle;
/**
* @pad: Padding field, must be zero.
*/
__u32 pad;
};
#if defined(__cplusplus)
}
#endif
#endif /* _PANFROST_DRM_H_ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/panthor_drm.h
+1246
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local/recipes/dev/mesa-clc/source/include/drm-uapi/pvr_drm.h
+1295
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local/recipes/dev/mesa-clc/source/include/drm-uapi/radeon_drm.h
+1079
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local/recipes/dev/mesa-clc/source/include/drm-uapi/rknpu_ioctl.h
+314
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@@ -0,0 +1,314 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author: Felix Zeng <felix.zeng@rock-chips.com>
*/
#ifndef __LINUX_RKNPU_IOCTL_H
#define __LINUX_RKNPU_IOCTL_H
#include <linux/ioctl.h>
#include <linux/types.h>
#if !defined(__KERNEL__)
#define __user
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#define RKNPU_OFFSET_VERSION 0x0
#define RKNPU_OFFSET_PC_OP_EN 0x8
#define RKNPU_OFFSET_PC_DATA_ADDR 0x10
#define RKNPU_OFFSET_PC_DATA_AMOUNT 0x14
#define RKNPU_OFFSET_PC_TASK_CONTROL 0x30
#define RKNPU_OFFSET_PC_DMA_BASE_ADDR 0x34
#define RKNPU_OFFSET_PC_TASK_STATUS 0x3c
#define RKNPU_OFFSET_INT_MASK 0x20
#define RKNPU_OFFSET_INT_CLEAR 0x24
#define RKNPU_OFFSET_INT_STATUS 0x28
#define RKNPU_OFFSET_INT_RAW_STATUS 0x2c
#define RKNPU_OFFSET_CLR_ALL_RW_AMOUNT 0x8010
#define RKNPU_OFFSET_DT_WR_AMOUNT 0x8034
#define RKNPU_OFFSET_DT_RD_AMOUNT 0x8038
#define RKNPU_OFFSET_WT_RD_AMOUNT 0x803c
#define RKNPU_OFFSET_ENABLE_MASK 0xf008
#define RKNPU_INT_CLEAR 0x1ffff
#define RKNPU_PC_DATA_EXTRA_AMOUNT 4
#define RKNPU_STR_HELPER(x) #x
#define RKNPU_GET_DRV_VERSION_STRING(MAJOR, MINOR, PATCHLEVEL) \
RKNPU_STR_HELPER(MAJOR) \
"." RKNPU_STR_HELPER(MINOR) "." RKNPU_STR_HELPER(PATCHLEVEL)
#define RKNPU_GET_DRV_VERSION_CODE(MAJOR, MINOR, PATCHLEVEL) \
(MAJOR * 10000 + MINOR * 100 + PATCHLEVEL)
#define RKNPU_GET_DRV_VERSION_MAJOR(CODE) (CODE / 10000)
#define RKNPU_GET_DRV_VERSION_MINOR(CODE) ((CODE % 10000) / 100)
#define RKNPU_GET_DRV_VERSION_PATCHLEVEL(CODE) (CODE % 100)
/* memory type definitions. */
enum e_rknpu_mem_type {
/* physically continuous memory and used as default. */
RKNPU_MEM_CONTIGUOUS = 0 << 0,
/* physically non-continuous memory. */
RKNPU_MEM_NON_CONTIGUOUS = 1 << 0,
/* non-cacheable mapping and used as default. */
RKNPU_MEM_NON_CACHEABLE = 0 << 1,
/* cacheable mapping. */
RKNPU_MEM_CACHEABLE = 1 << 1,
/* write-combine mapping. */
RKNPU_MEM_WRITE_COMBINE = 1 << 2,
/* dma attr kernel mapping */
RKNPU_MEM_KERNEL_MAPPING = 1 << 3,
/* iommu mapping */
RKNPU_MEM_IOMMU = 1 << 4,
/* zero mapping */
RKNPU_MEM_ZEROING = 1 << 5,
/* allocate secure buffer */
RKNPU_MEM_SECURE = 1 << 6,
/* allocate from non-dma32 zone */
RKNPU_MEM_NON_DMA32 = 1 << 7,
RKNPU_MEM_MASK = RKNPU_MEM_NON_CONTIGUOUS | RKNPU_MEM_CACHEABLE |
RKNPU_MEM_WRITE_COMBINE | RKNPU_MEM_KERNEL_MAPPING |
RKNPU_MEM_IOMMU | RKNPU_MEM_ZEROING |
RKNPU_MEM_SECURE | RKNPU_MEM_NON_DMA32
};
/* sync mode definitions. */
enum e_rknpu_mem_sync_mode {
RKNPU_MEM_SYNC_TO_DEVICE = 1 << 0,
RKNPU_MEM_SYNC_FROM_DEVICE = 1 << 1,
RKNPU_MEM_SYNC_MASK =
RKNPU_MEM_SYNC_TO_DEVICE | RKNPU_MEM_SYNC_FROM_DEVICE
};
/* job mode definitions. */
enum e_rknpu_job_mode {
RKNPU_JOB_SLAVE = 0 << 0,
RKNPU_JOB_PC = 1 << 0,
RKNPU_JOB_BLOCK = 0 << 1,
RKNPU_JOB_NONBLOCK = 1 << 1,
RKNPU_JOB_PINGPONG = 1 << 2,
RKNPU_JOB_FENCE_IN = 1 << 3,
RKNPU_JOB_FENCE_OUT = 1 << 4,
RKNPU_JOB_MASK = RKNPU_JOB_PC | RKNPU_JOB_NONBLOCK |
RKNPU_JOB_PINGPONG | RKNPU_JOB_FENCE_IN |
RKNPU_JOB_FENCE_OUT
};
/* action definitions */
enum e_rknpu_action {
RKNPU_GET_HW_VERSION = 0,
RKNPU_GET_DRV_VERSION = 1,
RKNPU_GET_FREQ = 2,
RKNPU_SET_FREQ = 3,
RKNPU_GET_VOLT = 4,
RKNPU_SET_VOLT = 5,
RKNPU_ACT_RESET = 6,
RKNPU_GET_BW_PRIORITY = 7,
RKNPU_SET_BW_PRIORITY = 8,
RKNPU_GET_BW_EXPECT = 9,
RKNPU_SET_BW_EXPECT = 10,
RKNPU_GET_BW_TW = 11,
RKNPU_SET_BW_TW = 12,
RKNPU_ACT_CLR_TOTAL_RW_AMOUNT = 13,
RKNPU_GET_DT_WR_AMOUNT = 14,
RKNPU_GET_DT_RD_AMOUNT = 15,
RKNPU_GET_WT_RD_AMOUNT = 16,
RKNPU_GET_TOTAL_RW_AMOUNT = 17,
RKNPU_GET_IOMMU_EN = 18,
RKNPU_SET_PROC_NICE = 19,
RKNPU_POWER_ON = 20,
RKNPU_POWER_OFF = 21,
};
/**
* User-desired buffer creation information structure.
*
* @handle: The handle of the created GEM object.
* @flags: user request for setting memory type or cache attributes.
* @size: user-desired memory allocation size.
* - this size value would be page-aligned internally.
* @obj_addr: address of RKNPU memory object.
* @dma_addr: dma address that access by rknpu.
*/
struct rknpu_mem_create {
__u32 handle;
__u32 flags;
__u64 size;
__u64 obj_addr;
__u64 dma_addr;
};
/**
* A structure for getting a fake-offset that can be used with mmap.
*
* @handle: handle of gem object.
* @reserved: just padding to be 64-bit aligned.
* @offset: a fake-offset of gem object.
*/
struct rknpu_mem_map {
__u32 handle;
__u32 reserved;
__u64 offset;
};
/**
* For destroying DMA buffer
*
* @handle: handle of the buffer.
* @reserved: reserved for padding.
* @obj_addr: rknpu_mem_object addr.
*/
struct rknpu_mem_destroy {
__u32 handle;
__u32 reserved;
__u64 obj_addr;
};
/**
* For synchronizing DMA buffer
*
* @flags: user request for setting memory type or cache attributes.
* @reserved: reserved for padding.
* @obj_addr: address of RKNPU memory object.
* @offset: offset in bytes from start address of buffer.
* @size: size of memory region.
*
*/
struct rknpu_mem_sync {
__u32 flags;
__u32 reserved;
__u64 obj_addr;
__u64 offset;
__u64 size;
};
/**
* struct rknpu_task structure for task information
*
* @flags: flags for task
* @op_idx: operator index
* @enable_mask: enable mask
* @int_mask: interrupt mask
* @int_clear: interrupt clear
* @int_status: interrupt status
* @regcfg_amount: register config number
* @regcfg_offset: offset for register config
* @regcmd_addr: address for register command
*
*/
struct rknpu_task {
__u32 flags;
__u32 op_idx;
__u32 enable_mask;
__u32 int_mask;
__u32 int_clear;
__u32 int_status;
__u32 regcfg_amount;
__u32 regcfg_offset;
__u64 regcmd_addr;
} __packed;
/**
* struct rknpu_subcore_task structure for subcore task index
*
* @task_start: task start index
* @task_number: task number
*
*/
struct rknpu_subcore_task {
__u32 task_start;
__u32 task_number;
};
/**
* struct rknpu_submit structure for job submit
*
* @flags: flags for job submit
* @timeout: submit timeout
* @task_start: task start index
* @task_number: task number
* @task_counter: task counter
* @priority: submit priority
* @task_obj_addr: address of task object
* @regcfg_obj_addr: address of register config object
* @task_base_addr: task base address
* @user_data: (optional) user data
* @core_mask: core mask of rknpu
* @fence_fd: dma fence fd
* @subcore_task: subcore task
*
*/
struct rknpu_submit {
__u32 flags;
__u32 timeout;
__u32 task_start;
__u32 task_number;
__u32 task_counter;
__s32 priority;
__u64 task_obj_addr;
__u64 regcfg_obj_addr;
__u64 task_base_addr;
__u64 user_data;
__u32 core_mask;
__s32 fence_fd;
struct rknpu_subcore_task subcore_task[5];
};
/**
* struct rknpu_task structure for action (GET, SET or ACT)
*
* @flags: flags for action
* @value: GET or SET value
*
*/
struct rknpu_action {
__u32 flags;
__u32 value;
};
#define RKNPU_ACTION 0x00
#define RKNPU_SUBMIT 0x01
#define RKNPU_MEM_CREATE 0x02
#define RKNPU_MEM_MAP 0x03
#define RKNPU_MEM_DESTROY 0x04
#define RKNPU_MEM_SYNC 0x05
#define RKNPU_IOC_MAGIC 'r'
#define RKNPU_IOW(nr, type) _IOW(RKNPU_IOC_MAGIC, nr, type)
#define RKNPU_IOR(nr, type) _IOR(RKNPU_IOC_MAGIC, nr, type)
#define RKNPU_IOWR(nr, type) _IOWR(RKNPU_IOC_MAGIC, nr, type)
#include <drm.h>
#define DRM_IOCTL_RKNPU_ACTION \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_ACTION, struct rknpu_action)
#define DRM_IOCTL_RKNPU_SUBMIT \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_SUBMIT, struct rknpu_submit)
#define DRM_IOCTL_RKNPU_MEM_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_CREATE, struct rknpu_mem_create)
#define DRM_IOCTL_RKNPU_MEM_MAP \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_MAP, struct rknpu_mem_map)
#define DRM_IOCTL_RKNPU_MEM_DESTROY \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_DESTROY, struct rknpu_mem_destroy)
#define DRM_IOCTL_RKNPU_MEM_SYNC \
DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_SYNC, struct rknpu_mem_sync)
#define IOCTL_RKNPU_ACTION RKNPU_IOWR(RKNPU_ACTION, struct rknpu_action)
#define IOCTL_RKNPU_SUBMIT RKNPU_IOWR(RKNPU_SUBMIT, struct rknpu_submit)
#define IOCTL_RKNPU_MEM_CREATE \
RKNPU_IOWR(RKNPU_MEM_CREATE, struct rknpu_mem_create)
#define IOCTL_RKNPU_MEM_MAP RKNPU_IOWR(RKNPU_MEM_MAP, struct rknpu_mem_map)
#define IOCTL_RKNPU_MEM_DESTROY \
RKNPU_IOWR(RKNPU_MEM_DESTROY, struct rknpu_mem_destroy)
#define IOCTL_RKNPU_MEM_SYNC RKNPU_IOWR(RKNPU_MEM_SYNC, struct rknpu_mem_sync)
#endif
local/recipes/dev/mesa-clc/source/include/drm-uapi/rocket_accel.h
+142
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@@ -0,0 +1,142 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2024 Tomeu Vizoso
*/
#ifndef __DRM_UAPI_ROCKET_ACCEL_H__
#define __DRM_UAPI_ROCKET_ACCEL_H__
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_ROCKET_CREATE_BO 0x00
#define DRM_ROCKET_SUBMIT 0x01
#define DRM_ROCKET_PREP_BO 0x02
#define DRM_ROCKET_FINI_BO 0x03
#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
#define DRM_IOCTL_ROCKET_PREP_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_PREP_BO, struct drm_rocket_prep_bo)
#define DRM_IOCTL_ROCKET_FINI_BO DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_FINI_BO, struct drm_rocket_fini_bo)
/**
* struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
*
*/
struct drm_rocket_create_bo {
/** Input: Size of the requested BO. */
__u32 size;
/** Output: GEM handle for the BO. */
__u32 handle;
/**
* Output: DMA address for the BO in the NPU address space. This address
* is private to the DRM fd and is valid for the lifetime of the GEM
* handle.
*/
__u64 dma_address;
/** Output: Offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
/**
* struct drm_rocket_prep_bo - ioctl argument for starting CPU ownership of the BO.
*
* Takes care of waiting for any NPU jobs that might still use the NPU and performs cache
* synchronization.
*/
struct drm_rocket_prep_bo {
/** Input: GEM handle of the buffer object. */
__u32 handle;
/** Reserved, must be zero. */
__u32 reserved;
/** Input: Amount of time to wait for NPU jobs. */
__s64 timeout_ns;
};
/**
* struct drm_rocket_fini_bo - ioctl argument for finishing CPU ownership of the BO.
*
* Synchronize caches for NPU access.
*/
struct drm_rocket_fini_bo {
/** Input: GEM handle of the buffer object. */
__u32 handle;
/** Reserved, must be zero. */
__u32 reserved;
};
/**
* struct drm_rocket_task - A task to be run on the NPU
*
* A task is the smallest unit of work that can be run on the NPU.
*/
struct drm_rocket_task {
/** Input: DMA address to NPU mapping of register command buffer */
__u32 regcmd;
/** Input: Number of commands in the register command buffer */
__u32 regcmd_count;
};
/**
* struct drm_rocket_job - A job to be run on the NPU
*
* The kernel will schedule the execution of this job taking into account its
* dependencies with other jobs. All tasks in the same job will be executed
* sequentially on the same core, to benefit from memory residency in SRAM.
*/
struct drm_rocket_job {
/** Input: Pointer to an array of struct drm_rocket_task. */
__u64 tasks;
/** Input: Pointer to a u32 array of the BOs that are read by the job. */
__u64 in_bo_handles;
/** Input: Pointer to a u32 array of the BOs that are written to by the job. */
__u64 out_bo_handles;
/** Input: Number of tasks passed in. */
__u32 task_count;
/** Input: Size in bytes of the structs in the @tasks field. */
__u32 task_struct_size;
/** Input: Number of input BO handles passed in (size is that times 4). */
__u32 in_bo_handle_count;
/** Input: Number of output BO handles passed in (size is that times 4). */
__u32 out_bo_handle_count;
};
/**
* struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
*
* The kernel will schedule the execution of these jobs in dependency order.
*/
struct drm_rocket_submit {
/** Input: Pointer to an array of struct drm_rocket_job. */
__u64 jobs;
/** Input: Number of jobs passed in. */
__u32 job_count;
/** Input: Size in bytes of the structs in the @jobs field. */
__u32 job_struct_size;
/** Reserved, must be zero. */
__u64 reserved;
};
#if defined(__cplusplus)
}
#endif
#endif /* __DRM_UAPI_ROCKET_ACCEL_H__ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/sync_file.h
+111
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@@ -0,0 +1,111 @@
/*
* SPDX-License-Identifier: GPL-1.0-or-later WITH Linux-syscall-note
* Copyright 2012 Google, Inc.
*/
#ifndef _UAPI_LINUX_SYNC_H
#define _UAPI_LINUX_SYNC_H
#if defined(__linux__)
#include <linux/ioctl.h>
#include <linux/types.h>
#else /* One of the BSDs */
#include <stdint.h>
#include <sys/types.h>
#include <sys/ioccom.h>
typedef int8_t __s8;
typedef uint8_t __u8;
typedef int16_t __s16;
typedef uint16_t __u16;
typedef int32_t __s32;
typedef uint32_t __u32;
typedef int64_t __s64;
typedef uint64_t __u64;
#endif
/**
* struct sync_merge_data - data passed to merge ioctl
* @name: name of new fence
* @fd2: file descriptor of second fence
* @fence: returns the fd of the new fence to userspace
* @flags: merge_data flags
* @pad: padding for 64-bit alignment, should always be zero
*/
struct sync_merge_data {
char name[32];
__s32 fd2;
__s32 fence;
__u32 flags;
__u32 pad;
};
/**
* struct sync_fence_info - detailed fence information
* @obj_name: name of parent sync_timeline
* @driver_name: name of driver implementing the parent
* @status: status of the fence 0:active 1:signaled <0:error
* @flags: fence_info flags
* @timestamp_ns: timestamp of status change in nanoseconds
*/
struct sync_fence_info {
char obj_name[32];
char driver_name[32];
__s32 status;
__u32 flags;
__u64 timestamp_ns;
};
/**
* struct sync_file_info - data returned from fence info ioctl
* @name: name of fence
* @status: status of fence. 1: signaled 0:active <0:error
* @flags: sync_file_info flags
* @num_fences number of fences in the sync_file
* @pad: padding for 64-bit alignment, should always be zero
* @sync_fence_info: pointer to array of structs sync_fence_info with all
* fences in the sync_file
*/
struct sync_file_info {
char name[32];
__s32 status;
__u32 flags;
__u32 num_fences;
__u32 pad;
__u64 sync_fence_info;
};
#define SYNC_IOC_MAGIC '>'
/**
* Opcodes 0, 1 and 2 were burned during a API change to avoid users of the
* old API to get weird errors when trying to handling sync_files. The API
* change happened during the de-stage of the Sync Framework when there was
* no upstream users available.
*/
/**
* DOC: SYNC_IOC_MERGE - merge two fences
*
* Takes a struct sync_merge_data. Creates a new fence containing copies of
* the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the
* new fence's fd in sync_merge_data.fence
*/
#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data)
/**
* DOC: SYNC_IOC_FILE_INFO - get detailed information on a sync_file
*
* Takes a struct sync_file_info. If num_fences is 0, the field is updated
* with the actual number of fences. If num_fences is > 0, the system will
* use the pointer provided on sync_fence_info to return up to num_fences of
* struct sync_fence_info, with detailed fence information.
*/
#define SYNC_IOC_FILE_INFO _IOWR(SYNC_IOC_MAGIC, 4, struct sync_file_info)
#endif /* _UAPI_LINUX_SYNC_H */
local/recipes/dev/mesa-clc/source/include/drm-uapi/tegra_drm.h
+1060
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local/recipes/dev/mesa-clc/source/include/drm-uapi/v3d_drm.h
+793
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@@ -0,0 +1,793 @@
/*
* Copyright © 2014-2018 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _V3D_DRM_H_
#define _V3D_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_V3D_SUBMIT_CL 0x00
#define DRM_V3D_WAIT_BO 0x01
#define DRM_V3D_CREATE_BO 0x02
#define DRM_V3D_MMAP_BO 0x03
#define DRM_V3D_GET_PARAM 0x04
#define DRM_V3D_GET_BO_OFFSET 0x05
#define DRM_V3D_SUBMIT_TFU 0x06
#define DRM_V3D_SUBMIT_CSD 0x07
#define DRM_V3D_PERFMON_CREATE 0x08
#define DRM_V3D_PERFMON_DESTROY 0x09
#define DRM_V3D_PERFMON_GET_VALUES 0x0a
#define DRM_V3D_SUBMIT_CPU 0x0b
#define DRM_V3D_PERFMON_GET_COUNTER 0x0c
#define DRM_V3D_PERFMON_SET_GLOBAL 0x0d
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
struct drm_v3d_perfmon_create)
#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
struct drm_v3d_perfmon_destroy)
#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
struct drm_v3d_perfmon_get_values)
#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)
#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \
struct drm_v3d_perfmon_get_counter)
#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \
struct drm_v3d_perfmon_set_global)
#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
#define DRM_V3D_SUBMIT_EXTENSION 0x02
/* struct drm_v3d_extension - ioctl extensions
*
* Linked-list of generic extensions where the id identify which struct is
* pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
* the extension type.
*/
struct drm_v3d_extension {
__u64 next;
__u32 id;
#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
#define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02
#define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03
#define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04
#define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05
#define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06
#define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07
__u32 flags; /* mbz */
};
/* struct drm_v3d_sem - wait/signal semaphore
*
* If binary semaphore, it only takes syncobj handle and ignores flags and
* point fields. Point is defined for timeline syncobj feature.
*/
struct drm_v3d_sem {
__u32 handle; /* syncobj */
/* rsv below, for future uses */
__u32 flags;
__u64 point; /* for timeline sem support */
__u64 mbz[2]; /* must be zero, rsv */
};
/* Enum for each of the V3D queues. */
enum v3d_queue {
V3D_BIN,
V3D_RENDER,
V3D_TFU,
V3D_CSD,
V3D_CACHE_CLEAN,
V3D_CPU,
};
/**
* struct drm_v3d_multi_sync - ioctl extension to add support multiples
* syncobjs for commands submission.
*
* When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
* this extension to define wait and signal dependencies, instead of single
* in/out sync entries on submitting commands. The field flags is used to
* determine the stage to set wait dependencies.
*/
struct drm_v3d_multi_sync {
struct drm_v3d_extension base;
/* Array of wait and signal semaphores */
__u64 in_syncs;
__u64 out_syncs;
/* Number of entries */
__u32 in_sync_count;
__u32 out_sync_count;
/* set the stage (v3d_queue) to sync */
__u32 wait_stage;
__u32 pad; /* mbz */
};
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
*
* This asks the kernel to have the GPU execute an optional binner
* command list, and a render command list.
*
* The L1T, slice, L2C, L2T, and GCA caches will be flushed before
* each CL executes. The VCD cache should be flushed (if necessary)
* by the submitted CLs. The TLB writes are guaranteed to have been
* flushed by the time the render done IRQ happens, which is the
* trigger for out_sync. Any dirtying of cachelines by the job (only
* possible using TMU writes) must be flushed by the caller using the
* DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
*/
struct drm_v3d_submit_cl {
/* Pointer to the binner command list.
*
* This is the first set of commands executed, which runs the
* coordinate shader to determine where primitives land on the screen,
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*
* This BCL will block on any previous BCL submitted on the
* same FD, but not on any RCL or BCLs submitted by other
* clients -- that is left up to the submitter to control
* using in_sync_bcl if necessary.
*/
__u32 bcl_start;
/** End address of the BCL (first byte after the BCL) */
__u32 bcl_end;
/* Offset of the render command list.
*
* This is the second set of commands executed, which will either
* execute the tiles that have been set up by the BCL, or a fixed set
* of tiles (in the case of RCL-only blits).
*
* This RCL will block on this submit's BCL, and any previous
* RCL submitted on the same FD, but not on any RCL or BCLs
* submitted by other clients -- that is left up to the
* submitter to control using in_sync_rcl if necessary.
*/
__u32 rcl_start;
/** End address of the RCL (first byte after the RCL) */
__u32 rcl_end;
/** An optional sync object to wait on before starting the BCL. */
__u32 in_sync_bcl;
/** An optional sync object to wait on before starting the RCL. */
__u32 in_sync_rcl;
/** An optional sync object to place the completion fence in. */
__u32 out_sync;
/* Offset of the tile alloc memory
*
* This is optional on V3D 3.3 (where the CL can set the value) but
* required on V3D 4.1.
*/
__u32 qma;
/** Size of the tile alloc memory. */
__u32 qms;
/** Offset of the tile state data array. */
__u32 qts;
/* Pointer to a u32 array of the BOs that are referenced by the job.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* DRM_V3D_SUBMIT_* properties */
__u32 flags;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmon_id;
__u32 pad;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
};
/**
* struct drm_v3d_wait_bo - ioctl argument for waiting for
* completion of the last DRM_V3D_SUBMIT_CL on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_v3d_wait_bo {
__u32 handle;
__u32 pad;
__u64 timeout_ns;
};
/**
* struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_v3d_create_bo {
__u32 size;
__u32 flags;
/** Returned GEM handle for the BO. */
__u32 handle;
/**
* Returned offset for the BO in the V3D address space. This offset
* is private to the DRM fd and is valid for the lifetime of the GEM
* handle.
*
* This offset value will always be nonzero, since various HW
* units treat 0 specially.
*/
__u32 offset;
};
/**
* struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_v3d_mmap_bo {
/** Handle for the object being mapped. */
__u32 handle;
__u32 flags;
/** offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
enum drm_v3d_param {
DRM_V3D_PARAM_V3D_UIFCFG,
DRM_V3D_PARAM_V3D_HUB_IDENT1,
DRM_V3D_PARAM_V3D_HUB_IDENT2,
DRM_V3D_PARAM_V3D_HUB_IDENT3,
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
DRM_V3D_PARAM_SUPPORTS_TFU,
DRM_V3D_PARAM_SUPPORTS_CSD,
DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
DRM_V3D_PARAM_SUPPORTS_PERFMON,
DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,
DRM_V3D_PARAM_MAX_PERF_COUNTERS,
DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES,
DRM_V3D_PARAM_GLOBAL_RESET_COUNTER,
DRM_V3D_PARAM_CONTEXT_RESET_COUNTER,
};
struct drm_v3d_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
/**
* Returns the offset for the BO in the V3D address space for this DRM fd.
* This is the same value returned by drm_v3d_create_bo, if that was called
* from this DRM fd.
*/
struct drm_v3d_get_bo_offset {
__u32 handle;
__u32 offset;
};
struct drm_v3d_submit_tfu {
__u32 icfg;
__u32 iia;
__u32 iis;
__u32 ica;
__u32 iua;
__u32 ioa;
__u32 ios;
__u32 coef[4];
/* First handle is the output BO, following are other inputs.
* 0 for unused.
*/
__u32 bo_handles[4];
/* sync object to block on before running the TFU job. Each TFU
* job will execute in the order submitted to its FD. Synchronization
* against rendering jobs requires using sync objects.
*/
__u32 in_sync;
/* Sync object to signal when the TFU job is done. */
__u32 out_sync;
__u32 flags;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
struct {
__u32 ioc;
__u32 pad;
} v71;
};
/* Submits a compute shader for dispatch. This job will block on any
* previous compute shaders submitted on this fd, and any other
* synchronization must be performed with in_sync/out_sync.
*/
struct drm_v3d_submit_csd {
__u32 cfg[7];
__u32 coef[4];
/* Pointer to a u32 array of the BOs that are referenced by the job.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* sync object to block on before running the CSD job. Each
* CSD job will execute in the order submitted to its FD.
* Synchronization against rendering/TFU jobs or CSD from
* other fds requires using sync objects.
*/
__u32 in_sync;
/* Sync object to signal when the CSD job is done. */
__u32 out_sync;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmon_id;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
__u32 flags;
__u32 pad;
};
/**
* struct drm_v3d_indirect_csd - ioctl extension for the CPU job to create an
* indirect CSD
*
* When an extension of DRM_V3D_EXT_ID_CPU_INDIRECT_CSD id is defined, it
* points to this extension to define a indirect CSD submission. It creates a
* CPU job linked to a CSD job. The CPU job waits for the indirect CSD
* dependencies and, once they are signaled, it updates the CSD job config
* before allowing the CSD job execution.
*/
struct drm_v3d_indirect_csd {
struct drm_v3d_extension base;
/* Indirect CSD */
struct drm_v3d_submit_csd submit;
/* Handle of the indirect BO, that should be also attached to the
* indirect CSD.
*/
__u32 indirect;
/* Offset within the BO where the workgroup counts are stored */
__u32 offset;
/* Workgroups size */
__u32 wg_size;
/* Indices of the uniforms with the workgroup dispatch counts
* in the uniform stream. If the uniform rewrite is not needed,
* the offset must be 0xffffffff.
*/
__u32 wg_uniform_offsets[3];
};
/**
* struct drm_v3d_timestamp_query - ioctl extension for the CPU job to calculate
* a timestamp query
*
* When an extension DRM_V3D_EXT_ID_TIMESTAMP_QUERY is defined, it points to
* this extension to define a timestamp query submission. This CPU job will
* calculate the timestamp query and update the query value within the
* timestamp BO. Moreover, it will signal the timestamp syncobj to indicate
* query availability.
*/
struct drm_v3d_timestamp_query {
struct drm_v3d_extension base;
/* Array of queries' offsets within the timestamp BO for their value */
__u64 offsets;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
/* Number of queries */
__u32 count;
/* mbz */
__u32 pad;
};
/**
* struct drm_v3d_reset_timestamp_query - ioctl extension for the CPU job to
* reset timestamp queries
*
* When an extension DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY is defined, it
* points to this extension to define a reset timestamp submission. This CPU
* job will reset the timestamp queries based on value offset of the first
* query. Moreover, it will reset the timestamp syncobj to reset query
* availability.
*/
struct drm_v3d_reset_timestamp_query {
struct drm_v3d_extension base;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
/* Offset of the first query within the timestamp BO for its value */
__u32 offset;
/* Number of queries */
__u32 count;
};
/**
* struct drm_v3d_copy_timestamp_query - ioctl extension for the CPU job to copy
* query results to a buffer
*
* When an extension DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY is defined, it
* points to this extension to define a copy timestamp query submission. This
* CPU job will copy the timestamp queries results to a BO with the offset
* and stride defined in the extension.
*/
struct drm_v3d_copy_timestamp_query {
struct drm_v3d_extension base;
/* Define if should write to buffer using 64 or 32 bits */
__u8 do_64bit;
/* Define if it can write to buffer even if the query is not available */
__u8 do_partial;
/* Define if it should write availability bit to buffer */
__u8 availability_bit;
/* mbz */
__u8 pad;
/* Offset of the buffer in the BO */
__u32 offset;
/* Stride of the buffer in the BO */
__u32 stride;
/* Number of queries */
__u32 count;
/* Array of queries' offsets within the timestamp BO for their value */
__u64 offsets;
/* Array of timestamp's syncobjs to indicate its availability */
__u64 syncs;
};
/**
* struct drm_v3d_reset_performance_query - ioctl extension for the CPU job to
* reset performance queries
*
* When an extension DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY is defined, it
* points to this extension to define a reset performance submission. This CPU
* job will reset the performance queries by resetting the values of the
* performance monitors. Moreover, it will reset the syncobj to reset query
* availability.
*/
struct drm_v3d_reset_performance_query {
struct drm_v3d_extension base;
/* Array of performance queries's syncobjs to indicate its availability */
__u64 syncs;
/* Number of queries */
__u32 count;
/* Number of performance monitors */
__u32 nperfmons;
/* Array of u64 user-pointers that point to an array of kperfmon_ids */
__u64 kperfmon_ids;
};
/**
* struct drm_v3d_copy_performance_query - ioctl extension for the CPU job to copy
* performance query results to a buffer
*
* When an extension DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY is defined, it
* points to this extension to define a copy performance query submission. This
* CPU job will copy the performance queries results to a BO with the offset
* and stride defined in the extension.
*/
struct drm_v3d_copy_performance_query {
struct drm_v3d_extension base;
/* Define if should write to buffer using 64 or 32 bits */
__u8 do_64bit;
/* Define if it can write to buffer even if the query is not available */
__u8 do_partial;
/* Define if it should write availability bit to buffer */
__u8 availability_bit;
/* mbz */
__u8 pad;
/* Offset of the buffer in the BO */
__u32 offset;
/* Stride of the buffer in the BO */
__u32 stride;
/* Number of performance monitors */
__u32 nperfmons;
/* Number of performance counters related to this query pool */
__u32 ncounters;
/* Number of queries */
__u32 count;
/* Array of performance queries's syncobjs to indicate its availability */
__u64 syncs;
/* Array of u64 user-pointers that point to an array of kperfmon_ids */
__u64 kperfmon_ids;
};
struct drm_v3d_submit_cpu {
/* Pointer to a u32 array of the BOs that are referenced by the job.
*
* For DRM_V3D_EXT_ID_CPU_INDIRECT_CSD, it must contain only one BO,
* that contains the workgroup counts.
*
* For DRM_V3D_EXT_ID_TIMESTAMP_QUERY, it must contain only one BO,
* that will contain the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY, it must contain only
* one BO, that contains the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY, it must contain two
* BOs. The first is the BO where the timestamp queries will be written
* to. The second is the BO that contains the timestamp.
*
* For DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY, it must contain no
* BOs.
*
* For DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY, it must contain one
* BO, where the performance queries will be written.
*/
__u64 bo_handles;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
__u32 flags;
/* Pointer to an array of ioctl extensions*/
__u64 extensions;
};
/* The performance counters index represented by this enum are deprecated and
* must no longer be used. These counters are only valid for V3D 4.2.
*
* In order to check for performance counter information,
* use DRM_IOCTL_V3D_PERFMON_GET_COUNTER.
*
* Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance
* counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following
* parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS.
*/
enum {
V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
V3D_PERFCNT_FEP_VALID_PRIMS,
V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
V3D_PERFCNT_FEP_VALID_QUADS,
V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
V3D_PERFCNT_TLB_QUADS_ZERO_COV,
V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
V3D_PERFCNT_TLB_QUADS_WRITTEN,
V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
V3D_PERFCNT_PTB_PRIM_CLIP,
V3D_PERFCNT_PTB_PRIM_REV,
V3D_PERFCNT_QPU_IDLE_CYCLES,
V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
V3D_PERFCNT_QPU_IC_HIT,
V3D_PERFCNT_QPU_IC_MISS,
V3D_PERFCNT_QPU_UC_HIT,
V3D_PERFCNT_QPU_UC_MISS,
V3D_PERFCNT_TMU_TCACHE_ACCESS,
V3D_PERFCNT_TMU_TCACHE_MISS,
V3D_PERFCNT_VPM_VDW_STALL,
V3D_PERFCNT_VPM_VCD_STALL,
V3D_PERFCNT_BIN_ACTIVE,
V3D_PERFCNT_RDR_ACTIVE,
V3D_PERFCNT_L2T_HITS,
V3D_PERFCNT_L2T_MISSES,
V3D_PERFCNT_CYCLE_COUNT,
V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
V3D_PERFCNT_PTB_PRIMS_BINNED,
V3D_PERFCNT_AXI_WRITES_WATCH_0,
V3D_PERFCNT_AXI_READS_WATCH_0,
V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
V3D_PERFCNT_AXI_WRITES_WATCH_1,
V3D_PERFCNT_AXI_READS_WATCH_1,
V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
V3D_PERFCNT_TLB_PARTIAL_QUADS,
V3D_PERFCNT_TMU_CONFIG_ACCESSES,
V3D_PERFCNT_L2T_NO_ID_STALL,
V3D_PERFCNT_L2T_COM_QUE_STALL,
V3D_PERFCNT_L2T_TMU_WRITES,
V3D_PERFCNT_TMU_ACTIVE_CYCLES,
V3D_PERFCNT_TMU_STALLED_CYCLES,
V3D_PERFCNT_CLE_ACTIVE,
V3D_PERFCNT_L2T_TMU_READS,
V3D_PERFCNT_L2T_CLE_READS,
V3D_PERFCNT_L2T_VCD_READS,
V3D_PERFCNT_L2T_TMUCFG_READS,
V3D_PERFCNT_L2T_SLC0_READS,
V3D_PERFCNT_L2T_SLC1_READS,
V3D_PERFCNT_L2T_SLC2_READS,
V3D_PERFCNT_L2T_TMU_W_MISSES,
V3D_PERFCNT_L2T_TMU_R_MISSES,
V3D_PERFCNT_L2T_CLE_MISSES,
V3D_PERFCNT_L2T_VCD_MISSES,
V3D_PERFCNT_L2T_TMUCFG_MISSES,
V3D_PERFCNT_L2T_SLC0_MISSES,
V3D_PERFCNT_L2T_SLC1_MISSES,
V3D_PERFCNT_L2T_SLC2_MISSES,
V3D_PERFCNT_CORE_MEM_WRITES,
V3D_PERFCNT_L2T_MEM_WRITES,
V3D_PERFCNT_PTB_MEM_WRITES,
V3D_PERFCNT_TLB_MEM_WRITES,
V3D_PERFCNT_CORE_MEM_READS,
V3D_PERFCNT_L2T_MEM_READS,
V3D_PERFCNT_PTB_MEM_READS,
V3D_PERFCNT_PSE_MEM_READS,
V3D_PERFCNT_TLB_MEM_READS,
V3D_PERFCNT_GMP_MEM_READS,
V3D_PERFCNT_PTB_W_MEM_WORDS,
V3D_PERFCNT_TLB_W_MEM_WORDS,
V3D_PERFCNT_PSE_R_MEM_WORDS,
V3D_PERFCNT_TLB_R_MEM_WORDS,
V3D_PERFCNT_TMU_MRU_HITS,
V3D_PERFCNT_COMPUTE_ACTIVE,
V3D_PERFCNT_NUM,
};
#define DRM_V3D_MAX_PERF_COUNTERS 32
struct drm_v3d_perfmon_create {
__u32 id;
__u32 ncounters;
__u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
};
struct drm_v3d_perfmon_destroy {
__u32 id;
};
/*
* Returns the values of the performance counters tracked by this
* perfmon (as an array of ncounters u64 values).
*
* No implicit synchronization is performed, so the user has to
* guarantee that any jobs using this perfmon have already been
* completed (probably by blocking on the seqno returned by the
* last exec that used the perfmon).
*/
struct drm_v3d_perfmon_get_values {
__u32 id;
__u32 pad;
__u64 values_ptr;
};
#define DRM_V3D_PERFCNT_MAX_NAME 64
#define DRM_V3D_PERFCNT_MAX_CATEGORY 32
#define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256
/**
* struct drm_v3d_perfmon_get_counter - ioctl to get the description of a
* performance counter
*
* As userspace needs to retrieve information about the performance counters
* available, this IOCTL allows users to get information about a performance
* counter (name, category and description).
*/
struct drm_v3d_perfmon_get_counter {
/*
* Counter ID
*
* Must be smaller than the maximum number of performance counters, which
* can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS.
*/
__u8 counter;
/* Name of the counter */
__u8 name[DRM_V3D_PERFCNT_MAX_NAME];
/* Category of the counter */
__u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY];
/* Description of the counter */
__u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION];
/* mbz */
__u8 reserved[7];
};
#define DRM_V3D_PERFMON_CLEAR_GLOBAL 0x0001
/**
* struct drm_v3d_perfmon_set_global - ioctl to define a global performance
* monitor
*
* The global performance monitor will be used for all jobs. If a global
* performance monitor is defined, jobs with a self-defined performance
* monitor won't be allowed.
*/
struct drm_v3d_perfmon_set_global {
__u32 flags;
__u32 id;
};
#if defined(__cplusplus)
}
#endif
#endif /* _V3D_DRM_H_ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/vc4_drm.h
+442
View File
@@ -0,0 +1,442 @@
/*
* Copyright © 2014-2015 Broadcom
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#ifndef _VC4_DRM_H_
#define _VC4_DRM_H_
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define DRM_VC4_SUBMIT_CL 0x00
#define DRM_VC4_WAIT_SEQNO 0x01
#define DRM_VC4_WAIT_BO 0x02
#define DRM_VC4_CREATE_BO 0x03
#define DRM_VC4_MMAP_BO 0x04
#define DRM_VC4_CREATE_SHADER_BO 0x05
#define DRM_VC4_GET_HANG_STATE 0x06
#define DRM_VC4_GET_PARAM 0x07
#define DRM_VC4_SET_TILING 0x08
#define DRM_VC4_GET_TILING 0x09
#define DRM_VC4_LABEL_BO 0x0a
#define DRM_VC4_GEM_MADVISE 0x0b
#define DRM_VC4_PERFMON_CREATE 0x0c
#define DRM_VC4_PERFMON_DESTROY 0x0d
#define DRM_VC4_PERFMON_GET_VALUES 0x0e
#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)
#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)
#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)
struct drm_vc4_submit_rcl_surface {
__u32 hindex; /* Handle index, or ~0 if not present. */
__u32 offset; /* Offset to start of buffer. */
/*
* Bits for either render config (color_write) or load/store packet.
* Bits should all be 0 for MSAA load/stores.
*/
__u16 bits;
#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
__u16 flags;
};
/**
* struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
* engine.
*
* Drivers typically use GPU BOs to store batchbuffers / command lists and
* their associated state. However, because the VC4 lacks an MMU, we have to
* do validation of memory accesses by the GPU commands. If we were to store
* our commands in BOs, we'd need to do uncached readback from them to do the
* validation process, which is too expensive. Instead, userspace accumulates
* commands and associated state in plain memory, then the kernel copies the
* data to its own address space, and then validates and stores it in a GPU
* BO.
*/
struct drm_vc4_submit_cl {
/* Pointer to the binner command list.
*
* This is the first set of commands executed, which runs the
* coordinate shader to determine where primitives land on the screen,
* then writes out the state updates and draw calls necessary per tile
* to the tile allocation BO.
*/
__u64 bin_cl;
/* Pointer to the shader records.
*
* Shader records are the structures read by the hardware that contain
* pointers to uniforms, shaders, and vertex attributes. The
* reference to the shader record has enough information to determine
* how many pointers are necessary (fixed number for shaders/uniforms,
* and an attribute count), so those BO indices into bo_handles are
* just stored as __u32s before each shader record passed in.
*/
__u64 shader_rec;
/* Pointer to uniform data and texture handles for the textures
* referenced by the shader.
*
* For each shader state record, there is a set of uniform data in the
* order referenced by the record (FS, VS, then CS). Each set of
* uniform data has a __u32 index into bo_handles per texture
* sample operation, in the order the QPU_W_TMUn_S writes appear in
* the program. Following the texture BO handle indices is the actual
* uniform data.
*
* The individual uniform state blocks don't have sizes passed in,
* because the kernel has to determine the sizes anyway during shader
* code validation.
*/
__u64 uniforms;
__u64 bo_handles;
/* Size in bytes of the binner command list. */
__u32 bin_cl_size;
/* Size in bytes of the set of shader records. */
__u32 shader_rec_size;
/* Number of shader records.
*
* This could just be computed from the contents of shader_records and
* the address bits of references to them from the bin CL, but it
* keeps the kernel from having to resize some allocations it makes.
*/
__u32 shader_rec_count;
/* Size in bytes of the uniform state. */
__u32 uniforms_size;
/* Number of BO handles passed in (size is that times 4). */
__u32 bo_handle_count;
/* RCL setup: */
__u16 width;
__u16 height;
__u8 min_x_tile;
__u8 min_y_tile;
__u8 max_x_tile;
__u8 max_y_tile;
struct drm_vc4_submit_rcl_surface color_read;
struct drm_vc4_submit_rcl_surface color_write;
struct drm_vc4_submit_rcl_surface zs_read;
struct drm_vc4_submit_rcl_surface zs_write;
struct drm_vc4_submit_rcl_surface msaa_color_write;
struct drm_vc4_submit_rcl_surface msaa_zs_write;
__u32 clear_color[2];
__u32 clear_z;
__u8 clear_s;
__u32 pad:24;
#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
/* By default, the kernel gets to choose the order that the tiles are
* rendered in. If this is set, then the tiles will be rendered in a
* raster order, with the right-to-left vs left-to-right and
* top-to-bottom vs bottom-to-top dictated by
* VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
* blits to be implemented using the 3D engine.
*/
#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
__u32 flags;
/* Returned value of the seqno of this render job (for the
* wait ioctl).
*/
__u64 seqno;
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
/* Syncobj handle to wait on. If set, processing of this render job
* will not start until the syncobj is signaled. 0 means ignore.
*/
__u32 in_sync;
/* Syncobj handle to export fence to. If set, the fence in the syncobj
* will be replaced with a fence that signals upon completion of this
* render job. 0 means ignore.
*/
__u32 out_sync;
__u32 pad2;
};
/**
* struct drm_vc4_wait_seqno - ioctl argument for waiting for
* DRM_VC4_SUBMIT_CL completion using its returned seqno.
*
* timeout_ns is the timeout in nanoseconds, where "0" means "don't
* block, just return the status."
*/
struct drm_vc4_wait_seqno {
__u64 seqno;
__u64 timeout_ns;
};
/**
* struct drm_vc4_wait_bo - ioctl argument for waiting for
* completion of the last DRM_VC4_SUBMIT_CL on a BO.
*
* This is useful for cases where multiple processes might be
* rendering to a BO and you want to wait for all rendering to be
* completed.
*/
struct drm_vc4_wait_bo {
__u32 handle;
__u32 pad;
__u64 timeout_ns;
};
/**
* struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_vc4_create_bo {
__u32 size;
__u32 flags;
/** Returned GEM handle for the BO. */
__u32 handle;
__u32 pad;
};
/**
* struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
*
* This doesn't actually perform an mmap. Instead, it returns the
* offset you need to use in an mmap on the DRM device node. This
* means that tools like valgrind end up knowing about the mapped
* memory.
*
* There are currently no values for the flags argument, but it may be
* used in a future extension.
*/
struct drm_vc4_mmap_bo {
/** Handle for the object being mapped. */
__u32 handle;
__u32 flags;
/** offset into the drm node to use for subsequent mmap call. */
__u64 offset;
};
/**
* struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
* shader BOs.
*
* Since allowing a shader to be overwritten while it's also being
* executed from would allow privlege escalation, shaders must be
* created using this ioctl, and they can't be mmapped later.
*/
struct drm_vc4_create_shader_bo {
/* Size of the data argument. */
__u32 size;
/* Flags, currently must be 0. */
__u32 flags;
/* Pointer to the data. */
__u64 data;
/** Returned GEM handle for the BO. */
__u32 handle;
/* Pad, must be 0. */
__u32 pad;
};
struct drm_vc4_get_hang_state_bo {
__u32 handle;
__u32 paddr;
__u32 size;
__u32 pad;
};
/**
* struct drm_vc4_hang_state - ioctl argument for collecting state
* from a GPU hang for analysis.
*/
struct drm_vc4_get_hang_state {
/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
__u64 bo;
/**
* On input, the size of the bo array. Output is the number
* of bos to be returned.
*/
__u32 bo_count;
__u32 start_bin, start_render;
__u32 ct0ca, ct0ea;
__u32 ct1ca, ct1ea;
__u32 ct0cs, ct1cs;
__u32 ct0ra0, ct1ra0;
__u32 bpca, bpcs;
__u32 bpoa, bpos;
__u32 vpmbase;
__u32 dbge;
__u32 fdbgo;
__u32 fdbgb;
__u32 fdbgr;
__u32 fdbgs;
__u32 errstat;
/* Pad that we may save more registers into in the future. */
__u32 pad[16];
};
#define DRM_VC4_PARAM_V3D_IDENT0 0
#define DRM_VC4_PARAM_V3D_IDENT1 1
#define DRM_VC4_PARAM_V3D_IDENT2 2
#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7
#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8
struct drm_vc4_get_param {
__u32 param;
__u32 pad;
__u64 value;
};
struct drm_vc4_get_tiling {
__u32 handle;
__u32 flags;
__u64 modifier;
};
struct drm_vc4_set_tiling {
__u32 handle;
__u32 flags;
__u64 modifier;
};
/**
* struct drm_vc4_label_bo - Attach a name to a BO for debug purposes.
*/
struct drm_vc4_label_bo {
__u32 handle;
__u32 len;
__u64 name;
};
/*
* States prefixed with '__' are internal states and cannot be passed to the
* DRM_IOCTL_VC4_GEM_MADVISE ioctl.
*/
#define VC4_MADV_WILLNEED 0
#define VC4_MADV_DONTNEED 1
#define __VC4_MADV_PURGED 2
#define __VC4_MADV_NOTSUPP 3
struct drm_vc4_gem_madvise {
__u32 handle;
__u32 madv;
__u32 retained;
__u32 pad;
};
enum {
VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER,
VC4_PERFCNT_FEP_VALID_PRIMS_RENDER,
VC4_PERFCNT_FEP_CLIPPED_QUADS,
VC4_PERFCNT_FEP_VALID_QUADS,
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL,
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL,
VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL,
VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE,
VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE,
VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF,
VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT,
VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING,
VC4_PERFCNT_PSE_PRIMS_REVERSED,
VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD,
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS,
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT,
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS,
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT,
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS,
VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED,
VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS,
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED,
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED,
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT,
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS,
VC4_PERFCNT_NUM_EVENTS,
};
#define DRM_VC4_MAX_PERF_COUNTERS 16
struct drm_vc4_perfmon_create {
__u32 id;
__u32 ncounters;
__u8 events[DRM_VC4_MAX_PERF_COUNTERS];
};
struct drm_vc4_perfmon_destroy {
__u32 id;
};
/*
* Returns the values of the performance counters tracked by this
* perfmon (as an array of ncounters u64 values).
*
* No implicit synchronization is performed, so the user has to
* guarantee that any jobs using this perfmon have already been
* completed (probably by blocking on the seqno returned by the
* last exec that used the perfmon).
*/
struct drm_vc4_perfmon_get_values {
__u32 id;
__u64 values_ptr;
};
#if defined(__cplusplus)
}
#endif
#endif /* _VC4_DRM_H_ */
local/recipes/dev/mesa-clc/source/include/drm-uapi/virtgpu_drm.h
+276
View File
@@ -0,0 +1,276 @@
/*
* Copyright 2013 Red Hat
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIRTGPU_DRM_H
#define VIRTGPU_DRM_H
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints.
*
* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
* compatibility Keep fields aligned to their size
*/
#define DRM_VIRTGPU_MAP 0x01
#define DRM_VIRTGPU_EXECBUFFER 0x02
#define DRM_VIRTGPU_GETPARAM 0x03
#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
#define DRM_VIRTGPU_RESOURCE_INFO 0x05
#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
#define DRM_VIRTGPU_WAIT 0x08
#define DRM_VIRTGPU_GET_CAPS 0x09
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
#define VIRTGPU_EXECBUF_RING_IDX 0x04
#define VIRTGPU_EXECBUF_FLAGS (\
VIRTGPU_EXECBUF_FENCE_FD_IN |\
VIRTGPU_EXECBUF_FENCE_FD_OUT |\
VIRTGPU_EXECBUF_RING_IDX |\
0)
struct drm_virtgpu_map {
__u64 offset; /* use for mmap system call */
__u32 handle;
__u32 pad;
};
#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
0)
struct drm_virtgpu_execbuffer_syncobj {
__u32 handle;
__u32 flags;
__u64 point;
};
/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
struct drm_virtgpu_execbuffer {
__u32 flags;
__u32 size;
__u64 command; /* void* */
__u64 bo_handles;
__u32 num_bo_handles;
__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
__u32 num_in_syncobjs;
__u32 num_out_syncobjs;
__u64 in_syncobjs;
__u64 out_syncobjs;
};
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
struct drm_virtgpu_getparam {
__u64 param;
__u64 value;
};
/* NO_BO flags? NO resource flag? */
/* resource flag for y_0_top */
struct drm_virtgpu_resource_create {
__u32 target;
__u32 format;
__u32 bind;
__u32 width;
__u32 height;
__u32 depth;
__u32 array_size;
__u32 last_level;
__u32 nr_samples;
__u32 flags;
__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
__u32 res_handle; /* returned by kernel */
__u32 size; /* validate transfer in the host */
__u32 stride; /* validate transfer in the host */
};
struct drm_virtgpu_resource_info {
__u32 bo_handle;
__u32 res_handle;
__u32 size;
__u32 blob_mem;
};
struct drm_virtgpu_3d_box {
__u32 x;
__u32 y;
__u32 z;
__u32 w;
__u32 h;
__u32 d;
};
struct drm_virtgpu_3d_transfer_to_host {
__u32 bo_handle;
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
struct drm_virtgpu_3d_transfer_from_host {
__u32 bo_handle;
struct drm_virtgpu_3d_box box;
__u32 level;
__u32 offset;
__u32 stride;
__u32 layer_stride;
};
#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
struct drm_virtgpu_3d_wait {
__u32 handle; /* 0 is an invalid handle */
__u32 flags;
};
#define VIRTGPU_DRM_CAPSET_VIRGL 1
#define VIRTGPU_DRM_CAPSET_VIRGL2 2
#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
#define VIRTGPU_DRM_CAPSET_VENUS 4
#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
#define VIRTGPU_DRM_CAPSET_DRM 6
struct drm_virtgpu_get_caps {
__u32 cap_set_id;
__u32 cap_set_ver;
__u64 addr;
__u32 size;
__u32 pad;
};
struct drm_virtgpu_resource_create_blob {
#define VIRTGPU_BLOB_MEM_GUEST 0x0001
#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
/* zero is invalid blob_mem */
__u32 blob_mem;
__u32 blob_flags;
__u32 bo_handle;
__u32 res_handle;
__u64 size;
/*
* for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
* VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
*/
__u32 pad;
__u32 cmd_size;
__u64 cmd;
__u64 blob_id;
};
#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004
struct drm_virtgpu_context_set_param {
__u64 param;
__u64 value;
};
struct drm_virtgpu_context_init {
__u32 num_params;
__u32 pad;
/* pointer to drm_virtgpu_context_set_param array */
__u64 ctx_set_params;
};
/*
* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
* effect. The event size is sizeof(drm_event), since there is no additional
* payload.
*/
#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
#define DRM_IOCTL_VIRTGPU_MAP \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
struct drm_virtgpu_execbuffer)
#define DRM_IOCTL_VIRTGPU_GETPARAM \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
struct drm_virtgpu_getparam)
#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
struct drm_virtgpu_resource_create)
#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
struct drm_virtgpu_resource_info)
#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
struct drm_virtgpu_3d_transfer_from_host)
#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
struct drm_virtgpu_3d_transfer_to_host)
#define DRM_IOCTL_VIRTGPU_WAIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
struct drm_virtgpu_3d_wait)
#define DRM_IOCTL_VIRTGPU_GET_CAPS \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
struct drm_virtgpu_get_caps)
#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
struct drm_virtgpu_resource_create_blob)
#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
struct drm_virtgpu_context_init)
#if defined(__cplusplus)
}
#endif
#endif
local/recipes/dev/mesa-clc/source/include/drm-uapi/xe_drm.h
+2459
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