vasilito/RedBear-OS
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel: comprehensive workaround port from Linux 7.1

Browse Source
This commit is contained in:
Admin Pupkin
2026-06-03 08:40:10 +03:00
parent d48ef7f26a
commit 3fa4e9c895
2 changed files with 46 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files
local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
+4
View File
@@ -191,6 +191,7 @@ pub const GEN12_PSS_MODE2_FD_END_COLLECT: u32 = 1 << 8;
// GEN12_PSS_CHICKEN
pub const GEN12_PSS_CHICKEN_VF_PREFETCH_TLB_DIS: u32 = 1 << 4;
pub const VF_PREFETCH_TLB_DIS: u32 = 1 << 5;
// GEN12_CACHE_MODE_1
pub const GEN12_CACHE_MODE_1_MSAA_OPTIMIZATION_REDUC_DISABLE: u32 = 1 << 16;
@@ -243,6 +244,8 @@ pub const COMMON_SLICE_CHICKEN4: usize = 0x7300;
pub const VF_PREEMPTION: usize = 0x83A4;
pub const DRAW_WATERMARK: usize = 0x26C0;
pub const GEN10_SAMPLER_MODE: usize = 0xB11C;
pub const GEN10_DFR_RATIO_EN_AND_CHICKEN: usize = 0x9550;
pub const DFR_DISABLE: u32 = 1 << 9;
pub const GEN11_LSN_UNSLCVC: usize = 0xB018;
pub const GEN8_GAMW_ECO_DEV_RW_IA: usize = 0x4080;
pub const UNSLICE_UNIT_LEVEL_CLKGATE: usize = 0x9434;
@@ -317,6 +320,7 @@ pub const GEN12_DISABLE_EARLY_READ: u32 = 1 << 15;
pub const GEN12_PUSH_CONST_DEREF_HOLD_DIS: u32 = 1 << 1;
pub const GEN12_DISABLE_TDL_PUSH: u32 = 1 << 4;
pub const GEN12_FF_TESSELATION_DOP_GATE_DISABLE: u32 = 1 << 4;
pub const GEN12_DOP_CLOCK_GATE_RENDER_ENABLE: u32 = 1 << 1;
pub const FF_DOP_CLOCK_GATE_DISABLE: u32 = 1 << 1;
pub const ENABLE_SMALLPL: u32 = 1 << 12;
pub const GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE: u32 = 1 << 17;
local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
+42 -25
View File
@@ -316,33 +316,41 @@ fn icl_gt_workarounds_init(wal: &mut WorkaroundList) {
}
fn gen12_gt_workarounds_init(wal: &mut WorkaroundList, stepping: u8) {
// Gen12 inherits Gen9 workarounds plus additional ones.
gen9_gt_workarounds_init(wal, stepping);
/* Wa_14017192718:gen12 */
wa_write_or(wal, GEN11_GT_SCRATCH, 1 << 8, "Wa_14017192718");
/* Wa_14012688713:gen12 */
wa_write_or(wal, GEN11_GT_SCRATCH, 1 << 9, "Wa_14012688713");
/* Wa_16013039831:gen12 */
wa_masked_en(wal, GEN8_ROW_CHICKEN, GEN9_ENABLE_ROW_CHICKEN, "Wa_16013039831");
/* Wa_14013676891:gen12 */
wa_write_or(wal, GEN8_SAMPLER_MODE, 1 << 8, "Wa_14013676891");
/* Wa_16012751909:gen12 */
wa_write_or(wal, GEN12_COMMON_SLICE_CHICKEN2, GEN12_CSC2_SCOREBOARD_STALL_FLUSH_CONTROL, "Wa_16012751909");
/* Wa_16012322899:gen12 */
wa_write_or(wal, GEN7_HALF_SLICE_CHICKEN1, GEN8_HSH_CHICKEN3_DOP_GATING_DISABLE, "Wa_16012322899");
wa_write_or(wal, VDBOX_CGCTL3F10, IECPUNIT_CLKGATE_DIS, "Wa_14011060649");
wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE, "Wa_14011059788");
wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, 0, 0, "Wa_14015795083");
wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_render");
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_comp");
wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_vdbx");
wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_vebx");
wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE, "Wa_1509235366");
wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE, "Wa_14010648519");
if stepping == 0 {
/* Wa_16012650089:gen12_a0 */
wa_write_or(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 1 << 8, "Wa_16012650089");
}
}
fn xelpg_gt_workarounds_init(wal: &mut WorkaroundList, _stepping: u8) {
wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB, "Wa_14018575942");
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329");
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082");
}
fn xelpmp_gt_workarounds_init(wal: &mut WorkaroundList) {
wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB, "Wa_14018778641");
wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_xelpmp");
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082_xelpmp");
}
// ---------------------------------------------------------------------------
// Context workaround tables (Gen6 – Gen12)
// ---------------------------------------------------------------------------
@@ -360,6 +368,8 @@ pub fn build_ctx_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
IntelGeneration::Gen9 => skl_ctx_workarounds_init(&mut wal),
IntelGeneration::Gen9_5 => icl_ctx_workarounds_init(&mut wal),
IntelGeneration::Gen12 => gen12_ctx_workarounds_init(&mut wal),
IntelGeneration::Gen12_7 => xelpg_ctx_workarounds_init(&mut wal),
IntelGeneration::GenXe2 => xelpg_ctx_workarounds_init(&mut wal),
_ => {}
}
@@ -466,6 +476,19 @@ fn dg2_ctx_workarounds_init(wal: &mut WorkaroundList) {
wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT, "Wa_14019877138");
}
fn xelpg_ctx_workarounds_init(wal: &mut WorkaroundList) {
wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP, "TBIMR_FAST_CLIP_xelpg");
wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 0x7f, "L3_PWM_TIMER_xelpg");
wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128, "FF_MODE2_xelpg");
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, "DRAW_WATERMARK_xelpg");
wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000, "Wa_14014947963_xelpg");
wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, MSC_MSAA_REODER_BUF_BYPASS_DISABLE, "Wa_16013271637_xelpg");
wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS, "Wa_18019627453_xelpg");
wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL, "Wa_18018764978_xelpg");
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE, "Wa_18019271663_xelpg");
wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT, "Wa_14019877138_xelpg");
}
// ---------------------------------------------------------------------------
// Engine workaround tables
// ---------------------------------------------------------------------------
@@ -493,7 +516,7 @@ pub fn build_engine_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList
}
fn add_render_compute_tuning_settings(wal: &mut WorkaroundList, gen: IntelGeneration) {
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7) {
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512, "RT_CTRL_TUNING");
}
if gen == IntelGeneration::Gen12 {
@@ -508,21 +531,15 @@ fn general_render_compute_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE, "WaSetIndirectStateOverride");
}
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7) {
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH, "Wa_14017856879");
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING, "Wa_14020495402");
}
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DISABLE_128B_EVICTION_COMMAND_UDW, "Wa_22013037850");
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE, "Wa_18017747507");
}
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE, "Wa_22014226127");
}
if gen == IntelGeneration::GenXe2 {
if gen == IntelGeneration::Gen12 {
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, "Wa_14015227452");
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8, "Wa_22015475538");
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3, "Wa_18028616096");
@@ -532,16 +549,16 @@ fn general_render_compute_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration
fn rcs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
general_render_compute_wa_init(wal, gen);
if matches!(gen, IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
if matches!(gen, IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7) {
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, ENABLE_EU_COUNT_FOR_TDL_FLUSH, "Wa_22014600077");
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB, "Wa_1509727124");
}
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7) {
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION, "Wa_22012856258");
}
if gen == IntelGeneration::GenXe2 {
if gen == IntelGeneration::Gen12 {
wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK, "Wa_22010960976");
wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, REG_MASKED_FIELD_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), 0, "Wa_14015150844");
}