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Fix duplicate atomic_t typedef conflicting with types.h

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Admin Pupkin
2026-05-31 05:50:29 +03:00
parent 98326148ef
commit 3431bbfeb2
6455 changed files with 7049323 additions and 203 deletions
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local/recipes/gpu/amdgpu-source/include/linux/platform_data/ad5761.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AD5721, AD5721R, AD5761, AD5761R, Voltage Output Digital to Analog Converter
*
* Copyright 2016 Qtechnology A/S
* 2016 Ricardo Ribalda <ribalda@kernel.org>
*/
#ifndef __LINUX_PLATFORM_DATA_AD5761_H__
#define __LINUX_PLATFORM_DATA_AD5761_H__
/**
* enum ad5761_voltage_range - Voltage range the AD5761 is configured for.
* @AD5761_VOLTAGE_RANGE_M10V_10V: -10V to 10V
* @AD5761_VOLTAGE_RANGE_0V_10V: 0V to 10V
* @AD5761_VOLTAGE_RANGE_M5V_5V: -5V to 5V
* @AD5761_VOLTAGE_RANGE_0V_5V: 0V to 5V
* @AD5761_VOLTAGE_RANGE_M2V5_7V5: -2.5V to 7.5V
* @AD5761_VOLTAGE_RANGE_M3V_3V: -3V to 3V
* @AD5761_VOLTAGE_RANGE_0V_16V: 0V to 16V
* @AD5761_VOLTAGE_RANGE_0V_20V: 0V to 20V
*/
enum ad5761_voltage_range {
AD5761_VOLTAGE_RANGE_M10V_10V,
AD5761_VOLTAGE_RANGE_0V_10V,
AD5761_VOLTAGE_RANGE_M5V_5V,
AD5761_VOLTAGE_RANGE_0V_5V,
AD5761_VOLTAGE_RANGE_M2V5_7V5,
AD5761_VOLTAGE_RANGE_M3V_3V,
AD5761_VOLTAGE_RANGE_0V_16V,
AD5761_VOLTAGE_RANGE_0V_20V,
};
/**
* struct ad5761_platform_data - AD5761 DAC driver platform data
* @voltage_range: Voltage range the AD5761 is configured for
*/
struct ad5761_platform_data {
enum ad5761_voltage_range voltage_range;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ad7266.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AD7266/65 SPI ADC driver
*
* Copyright 2012 Analog Devices Inc.
*/
#ifndef __IIO_ADC_AD7266_H__
#define __IIO_ADC_AD7266_H__
/**
* enum ad7266_range - AD7266 reference voltage range
* @AD7266_RANGE_VREF: Device is configured for input range 0V - VREF
* (RANGE pin set to low)
* @AD7266_RANGE_2VREF: Device is configured for input range 0V - 2VREF
* (RANGE pin set to high)
*/
enum ad7266_range {
AD7266_RANGE_VREF,
AD7266_RANGE_2VREF,
};
/**
* enum ad7266_mode - AD7266 sample mode
* @AD7266_MODE_DIFF: Device is configured for full differential mode
* (SGL/DIFF pin set to low, AD0 pin set to low)
* @AD7266_MODE_PSEUDO_DIFF: Device is configured for pseudo differential mode
* (SGL/DIFF pin set to low, AD0 pin set to high)
* @AD7266_MODE_SINGLE_ENDED: Device is configured for single-ended mode
* (SGL/DIFF pin set to high)
*/
enum ad7266_mode {
AD7266_MODE_DIFF,
AD7266_MODE_PSEUDO_DIFF,
AD7266_MODE_SINGLE_ENDED,
};
/**
* struct ad7266_platform_data - Platform data for the AD7266 driver
* @range: Reference voltage range the device is configured for
* @mode: Sample mode the device is configured for
* @fixed_addr: Whether the address pins are hard-wired
*/
struct ad7266_platform_data {
enum ad7266_range range;
enum ad7266_mode mode;
bool fixed_addr;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ad7791.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_PLATFORM_DATA_AD7791__
#define __LINUX_PLATFORM_DATA_AD7791__
/**
* struct ad7791_platform_data - AD7791 device platform data
* @buffered: If set to true configure the device for buffered input mode.
* @burnout_current: If set to true the 100mA burnout current is enabled.
* @unipolar: If set to true sample in unipolar mode, if set to false sample in
* bipolar mode.
*/
struct ad7791_platform_data {
bool buffered;
bool burnout_current;
bool unipolar;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ad7793.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* AD7792/AD7793 SPI ADC driver
*
* Copyright 2011 Analog Devices Inc.
*/
#ifndef __LINUX_PLATFORM_DATA_AD7793_H__
#define __LINUX_PLATFORM_DATA_AD7793_H__
/**
* enum ad7793_clock_source - AD7793 clock source selection
* @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
* @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
* @AD7793_CLK_SRC_EXT: Use external clock.
* @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
*/
enum ad7793_clock_source {
AD7793_CLK_SRC_INT,
AD7793_CLK_SRC_INT_CO,
AD7793_CLK_SRC_EXT,
AD7793_CLK_SRC_EXT_DIV2,
};
/**
* enum ad7793_bias_voltage - AD7793 bias voltage selection
* @AD7793_BIAS_VOLTAGE_DISABLED: Bias voltage generator disabled
* @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
* @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
* @AD7793_BIAS_VOLTAGE_AIN3: Bias voltage connected to AIN3(-).
* Only valid for AD7795/AD7796.
*/
enum ad7793_bias_voltage {
AD7793_BIAS_VOLTAGE_DISABLED,
AD7793_BIAS_VOLTAGE_AIN1,
AD7793_BIAS_VOLTAGE_AIN2,
AD7793_BIAS_VOLTAGE_AIN3,
};
/**
* enum ad7793_refsel - AD7793 reference voltage selection
* @AD7793_REFSEL_REFIN1: External reference applied between REFIN1(+)
* and REFIN1(-).
* @AD7793_REFSEL_REFIN2: External reference applied between REFIN2(+)
* and REFIN1(-). Only valid for AD7795/AD7796.
* @AD7793_REFSEL_INTERNAL: Internal 1.17 V reference.
*/
enum ad7793_refsel {
AD7793_REFSEL_REFIN1 = 0,
AD7793_REFSEL_REFIN2 = 1,
AD7793_REFSEL_INTERNAL = 2,
};
/**
* enum ad7793_current_source_direction - AD7793 excitation current direction
* @AD7793_IEXEC1_IOUT1_IEXEC2_IOUT2: Current source IEXC1 connected to pin
* IOUT1, current source IEXC2 connected to pin IOUT2.
* @AD7793_IEXEC1_IOUT2_IEXEC2_IOUT1: Current source IEXC2 connected to pin
* IOUT1, current source IEXC1 connected to pin IOUT2.
* @AD7793_IEXEC1_IEXEC2_IOUT1: Both current sources connected to pin IOUT1.
* Only valid when the current sources are set to 10 uA or 210 uA.
* @AD7793_IEXEC1_IEXEC2_IOUT2: Both current sources connected to Pin IOUT2.
* Only valid when the current ources are set to 10 uA or 210 uA.
*/
enum ad7793_current_source_direction {
AD7793_IEXEC1_IOUT1_IEXEC2_IOUT2 = 0,
AD7793_IEXEC1_IOUT2_IEXEC2_IOUT1 = 1,
AD7793_IEXEC1_IEXEC2_IOUT1 = 2,
AD7793_IEXEC1_IEXEC2_IOUT2 = 3,
};
/**
* enum ad7793_excitation_current - AD7793 excitation current selection
* @AD7793_IX_DISABLED: Excitation current Disabled.
* @AD7793_IX_10uA: Enable 10 micro-ampere excitation current.
* @AD7793_IX_210uA: Enable 210 micro-ampere excitation current.
* @AD7793_IX_1mA: Enable 1 milli-Ampere excitation current.
*/
enum ad7793_excitation_current {
AD7793_IX_DISABLED = 0,
AD7793_IX_10uA = 1,
AD7793_IX_210uA = 2,
AD7793_IX_1mA = 3,
};
/**
* struct ad7793_platform_data - AD7793 platform data
* @clock_src: Clock source selection
* @burnout_current: If set to true the 100nA burnout current is enabled.
* @boost_enable: Enable boost for the bias voltage generator.
* @buffered: If set to true configure the device for buffered input mode.
* @unipolar: If set to true sample in unipolar mode, if set to false sample in
* bipolar mode.
* @refsel: Reference voltage selection
* @bias_voltage: Bias voltage selection
* @exitation_current: Excitation current selection
* @current_source_direction: Excitation current direction selection
*/
struct ad7793_platform_data {
enum ad7793_clock_source clock_src;
bool burnout_current;
bool boost_enable;
bool buffered;
bool unipolar;
enum ad7793_refsel refsel;
enum ad7793_bias_voltage bias_voltage;
enum ad7793_excitation_current exitation_current;
enum ad7793_current_source_direction current_source_direction;
};
#endif /* IIO_ADC_AD7793_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ad7887.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* AD7887 SPI ADC driver
*
* Copyright 2010 Analog Devices Inc.
*/
#ifndef IIO_ADC_AD7887_H_
#define IIO_ADC_AD7887_H_
/**
* struct ad7887_platform_data - AD7887 ADC driver platform data
* @en_dual: Whether to use dual channel mode. If set to true AIN1 becomes the
* second input channel, and Vref is internally connected to Vdd. If set to
* false the device is used in single channel mode and AIN1/Vref is used as
* VREF input.
*/
struct ad7887_platform_data {
bool en_dual;
};
#endif /* IIO_ADC_AD7887_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/adau17x1.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Driver for ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781 codecs
*
* Copyright 2011-2014 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#ifndef __LINUX_PLATFORM_DATA_ADAU17X1_H__
#define __LINUX_PLATFORM_DATA_ADAU17X1_H__
/**
* enum adau17x1_micbias_voltage - Microphone bias voltage
* @ADAU17X1_MICBIAS_0_90_AVDD: 0.9 * AVDD
* @ADAU17X1_MICBIAS_0_65_AVDD: 0.65 * AVDD
*/
enum adau17x1_micbias_voltage {
ADAU17X1_MICBIAS_0_90_AVDD = 0,
ADAU17X1_MICBIAS_0_65_AVDD = 1,
};
/**
* enum adau1761_digmic_jackdet_pin_mode - Configuration of the JACKDET/MICIN pin
* @ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE: Disable the pin
* @ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC: Configure the pin for usage as
* digital microphone input.
* @ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT: Configure the pin for jack
* insertion detection.
*/
enum adau1761_digmic_jackdet_pin_mode {
ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE,
ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC,
ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT,
};
/**
* adau1761_jackdetect_debounce_time - Jack insertion detection debounce time
* @ADAU1761_JACKDETECT_DEBOUNCE_5MS: 5 milliseconds
* @ADAU1761_JACKDETECT_DEBOUNCE_10MS: 10 milliseconds
* @ADAU1761_JACKDETECT_DEBOUNCE_20MS: 20 milliseconds
* @ADAU1761_JACKDETECT_DEBOUNCE_40MS: 40 milliseconds
*/
enum adau1761_jackdetect_debounce_time {
ADAU1761_JACKDETECT_DEBOUNCE_5MS = 0,
ADAU1761_JACKDETECT_DEBOUNCE_10MS = 1,
ADAU1761_JACKDETECT_DEBOUNCE_20MS = 2,
ADAU1761_JACKDETECT_DEBOUNCE_40MS = 3,
};
/**
* enum adau1761_output_mode - Output mode configuration
* @ADAU1761_OUTPUT_MODE_HEADPHONE: Headphone output
* @ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS: Capless headphone output
* @ADAU1761_OUTPUT_MODE_LINE: Line output
*/
enum adau1761_output_mode {
ADAU1761_OUTPUT_MODE_HEADPHONE,
ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
ADAU1761_OUTPUT_MODE_LINE,
};
/**
* struct adau1761_platform_data - ADAU1761 Codec driver platform data
* @input_differential: If true the input pins will be configured in
* differential mode.
* @lineout_mode: Output mode for the LOUT/ROUT pins
* @headphone_mode: Output mode for the LHP/RHP pins
* @digmic_jackdetect_pin_mode: JACKDET/MICIN pin configuration
* @jackdetect_debounce_time: Jack insertion detection debounce time.
* Note: This value will only be used, if the JACKDET/MICIN pin is configured
* for jack insertion detection.
* @jackdetect_active_low: If true the jack insertion detection is active low.
* Othwise it will be active high.
* @micbias_voltage: Microphone voltage bias
*/
struct adau1761_platform_data {
bool input_differential;
enum adau1761_output_mode lineout_mode;
enum adau1761_output_mode headphone_mode;
enum adau1761_digmic_jackdet_pin_mode digmic_jackdetect_pin_mode;
enum adau1761_jackdetect_debounce_time jackdetect_debounce_time;
bool jackdetect_active_low;
enum adau17x1_micbias_voltage micbias_voltage;
};
/**
* struct adau1781_platform_data - ADAU1781 Codec driver platform data
* @left_input_differential: If true configure the left input as
* differential input.
* @right_input_differential: If true configure the right input as differntial
* input.
* @use_dmic: If true configure the MIC pins as digital microphone pins instead
* of analog microphone pins.
* @micbias_voltage: Microphone voltage bias
*/
struct adau1781_platform_data {
bool left_input_differential;
bool right_input_differential;
bool use_dmic;
enum adau17x1_micbias_voltage micbias_voltage;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/adp8860.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Definitions and platform data for Analog Devices
* Backlight drivers ADP8860
*
* Copyright 2009-2010 Analog Devices Inc.
*/
#ifndef __LINUX_I2C_ADP8860_H
#define __LINUX_I2C_ADP8860_H
#include <linux/leds.h>
#include <linux/types.h>
#define ID_ADP8860 8860
#define ADP8860_MAX_BRIGHTNESS 0x7F
#define FLAG_OFFT_SHIFT 8
/*
* LEDs subdevice platform data
*/
#define ADP8860_LED_DIS_BLINK (0 << FLAG_OFFT_SHIFT)
#define ADP8860_LED_OFFT_600ms (1 << FLAG_OFFT_SHIFT)
#define ADP8860_LED_OFFT_1200ms (2 << FLAG_OFFT_SHIFT)
#define ADP8860_LED_OFFT_1800ms (3 << FLAG_OFFT_SHIFT)
#define ADP8860_LED_ONT_200ms 0
#define ADP8860_LED_ONT_600ms 1
#define ADP8860_LED_ONT_800ms 2
#define ADP8860_LED_ONT_1200ms 3
#define ADP8860_LED_D7 (7)
#define ADP8860_LED_D6 (6)
#define ADP8860_LED_D5 (5)
#define ADP8860_LED_D4 (4)
#define ADP8860_LED_D3 (3)
#define ADP8860_LED_D2 (2)
#define ADP8860_LED_D1 (1)
/*
* Backlight subdevice platform data
*/
#define ADP8860_BL_D7 (1 << 6)
#define ADP8860_BL_D6 (1 << 5)
#define ADP8860_BL_D5 (1 << 4)
#define ADP8860_BL_D4 (1 << 3)
#define ADP8860_BL_D3 (1 << 2)
#define ADP8860_BL_D2 (1 << 1)
#define ADP8860_BL_D1 (1 << 0)
#define ADP8860_FADE_T_DIS 0 /* Fade Timer Disabled */
#define ADP8860_FADE_T_300ms 1 /* 0.3 Sec */
#define ADP8860_FADE_T_600ms 2
#define ADP8860_FADE_T_900ms 3
#define ADP8860_FADE_T_1200ms 4
#define ADP8860_FADE_T_1500ms 5
#define ADP8860_FADE_T_1800ms 6
#define ADP8860_FADE_T_2100ms 7
#define ADP8860_FADE_T_2400ms 8
#define ADP8860_FADE_T_2700ms 9
#define ADP8860_FADE_T_3000ms 10
#define ADP8860_FADE_T_3500ms 11
#define ADP8860_FADE_T_4000ms 12
#define ADP8860_FADE_T_4500ms 13
#define ADP8860_FADE_T_5000ms 14
#define ADP8860_FADE_T_5500ms 15 /* 5.5 Sec */
#define ADP8860_FADE_LAW_LINEAR 0
#define ADP8860_FADE_LAW_SQUARE 1
#define ADP8860_FADE_LAW_CUBIC1 2
#define ADP8860_FADE_LAW_CUBIC2 3
#define ADP8860_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
#define ADP8860_BL_AMBL_FILT_160ms 1
#define ADP8860_BL_AMBL_FILT_320ms 2
#define ADP8860_BL_AMBL_FILT_640ms 3
#define ADP8860_BL_AMBL_FILT_1280ms 4
#define ADP8860_BL_AMBL_FILT_2560ms 5
#define ADP8860_BL_AMBL_FILT_5120ms 6
#define ADP8860_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
/*
* Blacklight current 0..30mA
*/
#define ADP8860_BL_CUR_mA(I) ((I * 127) / 30)
/*
* L2 comparator current 0..1106uA
*/
#define ADP8860_L2_COMP_CURR_uA(I) ((I * 255) / 1106)
/*
* L3 comparator current 0..138uA
*/
#define ADP8860_L3_COMP_CURR_uA(I) ((I * 255) / 138)
struct adp8860_backlight_platform_data {
u8 bl_led_assign; /* 1 = Backlight 0 = Individual LED */
u8 bl_fade_in; /* Backlight Fade-In Timer */
u8 bl_fade_out; /* Backlight Fade-Out Timer */
u8 bl_fade_law; /* fade-on/fade-off transfer characteristic */
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
u8 abml_filt; /* Light sensor filter time */
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
/**
* Independent Current Sinks / LEDS
* Sinks not assigned to the Backlight can be exposed to
* user space using the LEDS CLASS interface
*/
int num_leds;
struct led_info *leds;
u8 led_fade_in; /* LED Fade-In Timer */
u8 led_fade_out; /* LED Fade-Out Timer */
u8 led_fade_law; /* fade-on/fade-off transfer characteristic */
u8 led_on_time;
/**
* Gain down disable. Setting this option does not allow the
* charge pump to switch to lower gains. NOT AVAILABLE on ADP8860
* 1 = the charge pump doesn't switch down in gain until all LEDs are 0.
* The charge pump switches up in gain as needed. This feature is
* useful if the ADP8863 charge pump is used to drive an external load.
* This feature must be used when utilizing small fly capacitors
* (0402 or smaller).
* 0 = the charge pump automatically switches up and down in gain.
* This provides optimal efficiency, but is not suitable for driving
* loads that are not connected through the ADP8863 diode drivers.
* Additionally, the charge pump fly capacitors should be low ESR
* and sized 0603 or greater.
*/
u8 gdwn_dis;
};
#endif /* __LINUX_I2C_ADP8860_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/adp8870.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Definitions and platform data for Analog Devices
* Backlight drivers ADP8870
*
* Copyright 2009-2010 Analog Devices Inc.
*/
#ifndef __LINUX_I2C_ADP8870_H
#define __LINUX_I2C_ADP8870_H
#define ID_ADP8870 8870
#define ADP8870_MAX_BRIGHTNESS 0x7F
#define FLAG_OFFT_SHIFT 8
/*
* LEDs subdevice platform data
*/
#define ADP8870_LED_DIS_BLINK (0 << FLAG_OFFT_SHIFT)
#define ADP8870_LED_OFFT_600ms (1 << FLAG_OFFT_SHIFT)
#define ADP8870_LED_OFFT_1200ms (2 << FLAG_OFFT_SHIFT)
#define ADP8870_LED_OFFT_1800ms (3 << FLAG_OFFT_SHIFT)
#define ADP8870_LED_ONT_200ms 0
#define ADP8870_LED_ONT_600ms 1
#define ADP8870_LED_ONT_800ms 2
#define ADP8870_LED_ONT_1200ms 3
#define ADP8870_LED_D7 (7)
#define ADP8870_LED_D6 (6)
#define ADP8870_LED_D5 (5)
#define ADP8870_LED_D4 (4)
#define ADP8870_LED_D3 (3)
#define ADP8870_LED_D2 (2)
#define ADP8870_LED_D1 (1)
/*
* Backlight subdevice platform data
*/
#define ADP8870_BL_D7 (1 << 6)
#define ADP8870_BL_D6 (1 << 5)
#define ADP8870_BL_D5 (1 << 4)
#define ADP8870_BL_D4 (1 << 3)
#define ADP8870_BL_D3 (1 << 2)
#define ADP8870_BL_D2 (1 << 1)
#define ADP8870_BL_D1 (1 << 0)
#define ADP8870_FADE_T_DIS 0 /* Fade Timer Disabled */
#define ADP8870_FADE_T_300ms 1 /* 0.3 Sec */
#define ADP8870_FADE_T_600ms 2
#define ADP8870_FADE_T_900ms 3
#define ADP8870_FADE_T_1200ms 4
#define ADP8870_FADE_T_1500ms 5
#define ADP8870_FADE_T_1800ms 6
#define ADP8870_FADE_T_2100ms 7
#define ADP8870_FADE_T_2400ms 8
#define ADP8870_FADE_T_2700ms 9
#define ADP8870_FADE_T_3000ms 10
#define ADP8870_FADE_T_3500ms 11
#define ADP8870_FADE_T_4000ms 12
#define ADP8870_FADE_T_4500ms 13
#define ADP8870_FADE_T_5000ms 14
#define ADP8870_FADE_T_5500ms 15 /* 5.5 Sec */
#define ADP8870_FADE_LAW_LINEAR 0
#define ADP8870_FADE_LAW_SQUARE 1
#define ADP8870_FADE_LAW_CUBIC1 2
#define ADP8870_FADE_LAW_CUBIC2 3
#define ADP8870_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
#define ADP8870_BL_AMBL_FILT_160ms 1
#define ADP8870_BL_AMBL_FILT_320ms 2
#define ADP8870_BL_AMBL_FILT_640ms 3
#define ADP8870_BL_AMBL_FILT_1280ms 4
#define ADP8870_BL_AMBL_FILT_2560ms 5
#define ADP8870_BL_AMBL_FILT_5120ms 6
#define ADP8870_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
/*
* Blacklight current 0..30mA
*/
#define ADP8870_BL_CUR_mA(I) ((I * 127) / 30)
/*
* L2 comparator current 0..1106uA
*/
#define ADP8870_L2_COMP_CURR_uA(I) ((I * 255) / 1106)
/*
* L3 comparator current 0..551uA
*/
#define ADP8870_L3_COMP_CURR_uA(I) ((I * 255) / 551)
/*
* L4 comparator current 0..275uA
*/
#define ADP8870_L4_COMP_CURR_uA(I) ((I * 255) / 275)
/*
* L5 comparator current 0..138uA
*/
#define ADP8870_L5_COMP_CURR_uA(I) ((I * 255) / 138)
struct adp8870_backlight_platform_data {
u8 bl_led_assign; /* 1 = Backlight 0 = Individual LED */
u8 pwm_assign; /* 1 = Enables PWM mode */
u8 bl_fade_in; /* Backlight Fade-In Timer */
u8 bl_fade_out; /* Backlight Fade-Out Timer */
u8 bl_fade_law; /* fade-on/fade-off transfer characteristic */
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
u8 abml_filt; /* Light sensor filter time */
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_bright_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_bright_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l4_indoor_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l4_indor_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l5_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l5_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
u8 l4_trip; /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
u8 l4_hyst; /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
u8 l5_trip; /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
u8 l5_hyst; /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
/**
* Independent Current Sinks / LEDS
* Sinks not assigned to the Backlight can be exposed to
* user space using the LEDS CLASS interface
*/
int num_leds;
struct led_info *leds;
u8 led_fade_in; /* LED Fade-In Timer */
u8 led_fade_out; /* LED Fade-Out Timer */
u8 led_fade_law; /* fade-on/fade-off transfer characteristic */
u8 led_on_time;
};
#endif /* __LINUX_I2C_ADP8870_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ads7828.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI ADS7828 A/D Converter platform data definition
*
* Copyright (c) 2012 Savoir-faire Linux Inc.
* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
*
* For further information, see the Documentation/hwmon/ads7828.rst file.
*/
#ifndef _PDATA_ADS7828_H
#define _PDATA_ADS7828_H
/**
* struct ads7828_platform_data - optional ADS7828 connectivity info
* @diff_input: Differential input mode.
* @ext_vref: Use an external voltage reference.
* @vref_mv: Voltage reference value, if external.
*/
struct ads7828_platform_data {
bool diff_input;
bool ext_vref;
unsigned int vref_mv;
};
#endif /* _PDATA_ADS7828_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/amd_qdma.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
*/
#ifndef _PLATDATA_AMD_QDMA_H
#define _PLATDATA_AMD_QDMA_H
#include <linux/dmaengine.h>
/**
* struct qdma_queue_info - DMA queue information. This information is used to
* match queue when DMA channel is requested
* @dir: Channel transfer direction
*/
struct qdma_queue_info {
enum dma_transfer_direction dir;
};
#define QDMA_FILTER_PARAM(qinfo) ((void *)(qinfo))
struct dma_slave_map;
/**
* struct qdma_platdata - Platform specific data for QDMA engine
* @max_mm_channels: Maximum number of MM DMA channels in each direction
* @device_map: DMA slave map
* @irq_index: The index of first IRQ
* @dma_dev: The device pointer for dma operations
*/
struct qdma_platdata {
u32 max_mm_channels;
u32 irq_index;
struct dma_slave_map *device_map;
struct device *dma_dev;
};
#endif /* _PLATDATA_AMD_QDMA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/amd_xdma.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2022, Advanced Micro Devices, Inc.
*/
#ifndef _PLATDATA_AMD_XDMA_H
#define _PLATDATA_AMD_XDMA_H
#include <linux/dmaengine.h>
/**
* struct xdma_chan_info - DMA channel information
* This information is used to match channel when request dma channel
* @dir: Channel transfer direction
*/
struct xdma_chan_info {
enum dma_transfer_direction dir;
};
#define XDMA_FILTER_PARAM(chan_info) ((void *)(chan_info))
struct dma_slave_map;
/**
* struct xdma_platdata - platform specific data for XDMA engine
* @max_dma_channels: Maximum dma channels in each direction
*/
struct xdma_platdata {
u32 max_dma_channels;
u32 device_map_cnt;
struct dma_slave_map *device_map;
};
#endif /* _PLATDATA_AMD_XDMA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ams-delta-fiq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* include/linux/platform_data/ams-delta-fiq.h
*
* Taken from the original Amstrad modifications to fiq.h
*
* Copyright (c) 2004 Amstrad Plc
* Copyright (c) 2006 Matt Callow
* Copyright (c) 2010 Janusz Krzysztofik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H
#define __LINUX_PLATFORM_DATA_AMS_DELTA_FIQ_H
/*
* These are the offsets from the beginning of the fiq_buffer. They are put here
* since the buffer and header need to be accessed by drivers servicing devices
* which generate GPIO interrupts - e.g. keyboard, modem, hook switch.
*/
#define FIQ_MASK 0
#define FIQ_STATE 1
#define FIQ_KEYS_CNT 2
#define FIQ_TAIL_OFFSET 3
#define FIQ_HEAD_OFFSET 4
#define FIQ_BUF_LEN 5
#define FIQ_KEY 6
#define FIQ_MISSED_KEYS 7
#define FIQ_BUFFER_START 8
#define FIQ_GPIO_INT_MASK 9
#define FIQ_KEYS_HICNT 10
#define FIQ_IRQ_PEND 11
#define FIQ_SIR_CODE_L1 12
#define IRQ_SIR_CODE_L2 13
#define FIQ_CNT_INT_00 14
#define FIQ_CNT_INT_KEY 15
#define FIQ_CNT_INT_MDM 16
#define FIQ_CNT_INT_03 17
#define FIQ_CNT_INT_HSW 18
#define FIQ_CNT_INT_05 19
#define FIQ_CNT_INT_06 20
#define FIQ_CNT_INT_07 21
#define FIQ_CNT_INT_08 22
#define FIQ_CNT_INT_09 23
#define FIQ_CNT_INT_10 24
#define FIQ_CNT_INT_11 25
#define FIQ_CNT_INT_12 26
#define FIQ_CNT_INT_13 27
#define FIQ_CNT_INT_14 28
#define FIQ_CNT_INT_15 29
#define FIQ_CIRC_BUFF 30 /*Start of circular buffer */
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/apds990x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is part of the APDS990x sensor driver.
* Chip is combined proximity and ambient light sensor.
*
* Copyright (C) 2010 Nokia Corporation and/or its subsidiary(-ies).
*
* Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
*/
#ifndef __APDS990X_H__
#define __APDS990X_H__
#define APDS_IRLED_CURR_12mA 0x3
#define APDS_IRLED_CURR_25mA 0x2
#define APDS_IRLED_CURR_50mA 0x1
#define APDS_IRLED_CURR_100mA 0x0
/**
* struct apds990x_chip_factors - defines effect of the cover window
* @ga: Total glass attenuation
* @cf1: clear channel factor 1 for raw to lux conversion
* @irf1: IR channel factor 1 for raw to lux conversion
* @cf2: clear channel factor 2 for raw to lux conversion
* @irf2: IR channel factor 2 for raw to lux conversion
* @df: device factor for conversion formulas
*
* Structure for tuning ALS calculation to match with environment.
* Values depend on the material above the sensor and the sensor
* itself. If the GA is zero, driver will use uncovered sensor default values
* format: decimal value * APDS_PARAM_SCALE except df which is plain integer.
*/
struct apds990x_chip_factors {
int ga;
int cf1;
int irf1;
int cf2;
int irf2;
int df;
};
#define APDS_PARAM_SCALE 4096
/**
* struct apds990x_platform_data - platform data for apsd990x.c driver
* @cf: chip factor data
* @pdrive: IR-led driving current
* @ppcount: number of IR pulses used for proximity estimation
* @setup_resources: interrupt line setup call back function
* @release_resources: interrupt line release call back function
*
* Proximity detection result depends heavily on correct ppcount, pdrive
* and cover window.
*
*/
struct apds990x_platform_data {
struct apds990x_chip_factors cf;
u8 pdrive;
u8 ppcount;
int (*setup_resources)(void);
int (*release_resources)(void);
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/arm-ux500-pm.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2010-2013
* Author: Rickard Andersson <rickard.andersson@stericsson.com> for
* ST-Ericsson.
* Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
*/
#ifndef ARM_UX500_PM_H
#define ARM_UX500_PM_H
int prcmu_gic_decouple(void);
int prcmu_gic_recouple(void);
bool prcmu_gic_pending_irq(void);
bool prcmu_pending_irq(void);
bool prcmu_is_cpu_in_wfi(int cpu);
int prcmu_copy_gic_settings(void);
void ux500_pm_init(u32 phy_base, u32 size);
#endif /* ARM_UX500_PM_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/asoc-imx-ssi.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __MACH_SSI_H
#define __MACH_SSI_H
struct snd_ac97;
extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end;
extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer;
struct imx_ssi_platform_data {
unsigned int flags;
#define IMX_SSI_DMA (1 << 0)
#define IMX_SSI_USE_AC97 (1 << 1)
#define IMX_SSI_NET (1 << 2)
#define IMX_SSI_SYN (1 << 3)
#define IMX_SSI_USE_I2S_SLAVE (1 << 4)
void (*ac97_reset) (struct snd_ac97 *ac97);
void (*ac97_warm_reset)(struct snd_ac97 *ac97);
};
extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
#endif /* __MACH_SSI_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/asoc-kirkwood.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PLAT_AUDIO_H
#define __PLAT_AUDIO_H
struct kirkwood_asoc_platform_data {
int burst;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/asoc-pxa.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SOC_PXA_AUDIO_H__
#define __SOC_PXA_AUDIO_H__
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
/*
* @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
* a -1 value means no gpio will be used for reset
* @codec_pdata: AC97 codec platform_data
* reset_gpio should only be specified for pxa27x CPUs where a silicon
* bug prevents correct operation of the reset line. If not specified,
* the default behaviour on these CPUs is to consider gpio 113 as the
* AC97 reset line, which is the default on most boards.
*/
typedef struct {
int (*startup)(struct snd_pcm_substream *, void *);
void (*shutdown)(struct snd_pcm_substream *, void *);
void (*suspend)(void *);
void (*resume)(void *);
void *priv;
int reset_gpio;
void *codec_pdata[AC97_BUS_MAX_DEVICES];
} pxa2xx_audio_ops_t;
extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/asoc-s3c.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2009 Samsung Electronics Co. Ltd
* Author: Jaswinder Singh <jassi.brar@samsung.com>
*/
/* The machine init code calls s3c*_ac97_setup_gpio with
* one of these defines in order to select appropriate bank
* of GPIO for AC97 pins
*/
#define S3C64XX_AC97_GPD 0
#define S3C64XX_AC97_GPE 1
#include <linux/dmaengine.h>
struct samsung_i2s_type {
/* If the Primary DAI has 5.1 Channels */
#define QUIRK_PRI_6CHAN (1 << 0)
/* If the I2S block has a Stereo Overlay Channel */
#define QUIRK_SEC_DAI (1 << 1)
/*
* If the I2S block has no internal prescalar or MUX (I2SMOD[10] bit)
* The Machine driver must provide suitably set clock to the I2S block.
*/
#define QUIRK_NO_MUXPSR (1 << 2)
#define QUIRK_NEED_RSTCLR (1 << 3)
#define QUIRK_SUPPORTS_TDM (1 << 4)
#define QUIRK_SUPPORTS_IDMA (1 << 5)
/* Quirks of the I2S controller */
u32 quirks;
dma_addr_t idma_addr;
};
/**
* struct s3c_audio_pdata - common platform data for audio device drivers
* @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
*/
struct s3c_audio_pdata {
int (*cfg_gpio)(struct platform_device *);
dma_filter_fn dma_filter;
void *dma_playback;
void *dma_capture;
void *dma_play_sec;
void *dma_capture_mic;
struct samsung_i2s_type type;
};
local/recipes/gpu/amdgpu-source/include/linux/platform_data/asoc-ti-mcbsp.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Defines for Multi-Channel Buffered Serial Port
*
* Copyright (C) 2002 RidgeRun, Inc.
* Author: Steve Johnson
*/
#ifndef __ASOC_TI_MCBSP_H
#define __ASOC_TI_MCBSP_H
#include <linux/spinlock.h>
#include <linux/clk.h>
/* Platform specific configuration */
struct omap_mcbsp_ops {
void (*request)(unsigned int);
void (*free)(unsigned int);
};
struct omap_mcbsp_platform_data {
struct omap_mcbsp_ops *ops;
u16 buffer_size;
u8 reg_size;
u8 reg_step;
/* McBSP platform and instance specific features */
bool has_wakeup; /* Wakeup capability */
bool has_ccr; /* Transceiver has configuration control registers */
int (*force_ick_on)(struct clk *clk, bool force_on);
};
void omap3_mcbsp_init_pdata_callback(struct omap_mcbsp_platform_data *pdata);
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ata-pxa.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Generic PXA PATA driver
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __MACH_PATA_PXA_H__
#define __MACH_PATA_PXA_H__
struct pata_pxa_pdata {
/* PXA DMA DREQ<0:2> pin */
uint32_t dma_dreq;
/* Register shift */
uint32_t reg_shift;
/* IRQ flags */
uint32_t irq_flags;
};
#endif /* __MACH_PATA_PXA_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/atmel.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* atmel platform data
*/
#ifndef __ATMEL_H__
#define __ATMEL_H__
/* FIXME: this needs a better location, but gets stuff building again */
#ifdef CONFIG_ATMEL_PM
extern int at91_suspend_entering_slow_clock(void);
#else
static inline int at91_suspend_entering_slow_clock(void)
{
return 0;
}
#endif
#endif /* __ATMEL_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/b53.h
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/*
* B53 platform data
*
* Copyright (C) 2013 Jonas Gorski <jogo@openwrt.org>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __B53_H
#define __B53_H
#include <linux/types.h>
#include <linux/platform_data/dsa.h>
struct b53_platform_data {
/* Must be first such that dsa_register_switch() can access it */
struct dsa_chip_data cd;
u32 chip_id;
u16 enabled_ports;
/* only used by MMAP'd driver */
unsigned big_endian:1;
void __iomem *regs;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/bcm7038_wdt.h
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#ifndef __BCM7038_WDT_PDATA_H
#define __BCM7038_WDT_PDATA_H
struct bcm7038_wdt_platform_data {
const char *clk_name;
};
#endif /* __BCM7038_WDT_PDATA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/bd6107.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* bd6107.h - Rohm BD6107 LEDs Driver
*/
#ifndef __BD6107_H__
#define __BD6107_H__
struct device;
struct bd6107_platform_data {
struct device *dev;
unsigned int def_value;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/bh1770glc.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is part of the ROHM BH1770GLC / OSRAM SFH7770 sensor driver.
* Chip is combined proximity and ambient light sensor.
*
* Copyright (C) 2010 Nokia Corporation and/or its subsidiary(-ies).
*
* Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
*/
#ifndef __BH1770_H__
#define __BH1770_H__
/**
* struct bh1770_platform_data - platform data for bh1770glc driver
* @led_def_curr: IR led driving current.
* @glass_attenuation: Attenuation factor for covering window.
* @setup_resources: Call back for interrupt line setup function
* @release_resources: Call back for interrupte line release function
*
* Example of glass attenuation: 16384 * 385 / 100 means attenuation factor
* of 3.85. i.e. light_above_sensor = light_above_cover_window / 3.85
*/
struct bh1770_platform_data {
#define BH1770_LED_5mA 0
#define BH1770_LED_10mA 1
#define BH1770_LED_20mA 2
#define BH1770_LED_50mA 3
#define BH1770_LED_100mA 4
#define BH1770_LED_150mA 5
#define BH1770_LED_200mA 6
__u8 led_def_curr;
#define BH1770_NEUTRAL_GA 16384 /* 16384 / 16384 = 1 */
__u32 glass_attenuation;
int (*setup_resources)(void);
int (*release_resources)(void);
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/brcmfmac.h
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/*
* Copyright (c) 2016 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _LINUX_BRCMFMAC_PLATFORM_H
#define _LINUX_BRCMFMAC_PLATFORM_H
#define BRCMFMAC_PDATA_NAME "brcmfmac"
#define BRCMFMAC_COUNTRY_BUF_SZ 4
/*
* Platform specific driver functions and data. Through the platform specific
* device data functions and data can be provided to help the brcmfmac driver to
* operate with the device in combination with the used platform.
*/
/**
* Note: the brcmfmac can be loaded as module or be statically built-in into
* the kernel. If built-in then do note that it uses module_init (and
* module_exit) routines which equal device_initcall. So if you intend to
* create a module with the platform specific data for the brcmfmac and have
* it built-in to the kernel then use a higher initcall then device_initcall
* (see init.h). If this is not done then brcmfmac will load without problems
* but will not pickup the platform data.
*
* When the driver does not "detect" platform driver data then it will continue
* without reporting anything and just assume there is no data needed. Which is
* probably true for most platforms.
*/
/**
* enum brcmf_bus_type - Bus type identifier. Currently SDIO, USB and PCIE are
* supported.
*/
enum brcmf_bus_type {
BRCMF_BUSTYPE_SDIO,
BRCMF_BUSTYPE_USB,
BRCMF_BUSTYPE_PCIE
};
/**
* struct brcmfmac_sdio_pd - SDIO Device specific platform data.
*
* @txglomsz: SDIO txglom size. Use 0 if default of driver is to be
* used.
* @drive_strength: is the preferred drive_strength to be used for the SDIO
* pins. If 0 then a default value will be used. This is
* the target drive strength, the exact drive strength
* which will be used depends on the capabilities of the
* device.
* @oob_irq_supported: does the board have support for OOB interrupts. SDIO
* in-band interrupts are relatively slow and for having
* less overhead on interrupt processing an out of band
* interrupt can be used. If the HW supports this then
* enable this by setting this field to true and configure
* the oob related fields.
* @oob_irq_nr,
* @oob_irq_flags: the OOB interrupt information. The values are used for
* registering the irq using request_irq function.
* @broken_sg_support: flag for broken sg list support of SDIO host controller.
* Set this to true if the SDIO host controller has higher
* align requirement than 32 bytes for each scatterlist
* item.
* @sd_head_align: alignment requirement for start of data buffer.
* @sd_sgentry_align: length alignment requirement for each sg entry.
* @reset: This function can get called if the device communication
* broke down. This functionality is particularly useful in
* case of SDIO type devices. It is possible to reset a
* dongle via sdio data interface, but it requires that
* this is fully functional. This function is chip/module
* specific and this function should return only after the
* complete reset has completed.
*/
struct brcmfmac_sdio_pd {
int txglomsz;
unsigned int drive_strength;
bool oob_irq_supported;
unsigned int oob_irq_nr;
unsigned long oob_irq_flags;
bool broken_sg_support;
unsigned short sd_head_align;
unsigned short sd_sgentry_align;
void (*reset)(void);
};
/**
* struct brcmfmac_pd_cc_entry - Struct for translating user space country code
* (iso3166) to firmware country code and
* revision.
*
* @iso3166: iso3166 alpha 2 country code string.
* @cc: firmware country code string.
* @rev: firmware country code revision.
*/
struct brcmfmac_pd_cc_entry {
char iso3166[BRCMFMAC_COUNTRY_BUF_SZ];
char cc[BRCMFMAC_COUNTRY_BUF_SZ];
s32 rev;
};
/**
* struct brcmfmac_pd_cc - Struct for translating country codes as set by user
* space to a country code and rev which can be used by
* firmware.
*
* @table_size: number of entries in table (> 0)
* @table: array of 1 or more elements with translation information.
*/
struct brcmfmac_pd_cc {
int table_size;
struct brcmfmac_pd_cc_entry table[];
};
/**
* struct brcmfmac_pd_device - Device specific platform data. (id/rev/bus_type)
* is the unique identifier of the device.
*
* @id: ID of the device for which this data is. In case of SDIO
* or PCIE this is the chipid as identified by chip.c In
* case of USB this is the chipid as identified by the
* device query.
* @rev: chip revision, see id.
* @bus_type: The type of bus. Some chipid/rev exist for different bus
* types. Each bus type has its own set of settings.
* @feature_disable: Bitmask of features to disable (override), See feature.c
* in brcmfmac for details.
* @country_codes: If available, pointer to struct for translating country
* codes.
* @bus: Bus specific (union) device settings. Currently only
* SDIO.
*/
struct brcmfmac_pd_device {
unsigned int id;
unsigned int rev;
enum brcmf_bus_type bus_type;
unsigned int feature_disable;
struct brcmfmac_pd_cc *country_codes;
union {
struct brcmfmac_sdio_pd sdio;
} bus;
};
/**
* struct brcmfmac_platform_data - BRCMFMAC specific platform data.
*
* @power_on: This function is called by the brcmfmac driver when the module
* gets loaded. This can be particularly useful for low power
* devices. The platform spcific routine may for example decide to
* power up the complete device. If there is no use-case for this
* function then provide NULL.
* @power_off: This function is called by the brcmfmac when the module gets
* unloaded. At this point the devices can be powered down or
* otherwise be reset. So if an actual power_off is not supported
* but reset is supported by the devices then reset the devices
* when this function gets called. This can be particularly useful
* for low power devices. If there is no use-case for this
* function then provide NULL.
*/
struct brcmfmac_platform_data {
void (*power_on)(void);
void (*power_off)(void);
char *fw_alternative_path;
int device_count;
struct brcmfmac_pd_device devices[];
};
#endif /* _LINUX_BRCMFMAC_PLATFORM_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/brcmnand.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef BRCMNAND_PLAT_DATA_H
#define BRCMNAND_PLAT_DATA_H
struct brcmnand_platform_data {
int chip_select;
const char * const *part_probe_types;
unsigned int ecc_stepsize;
unsigned int ecc_strength;
};
#endif /* BRCMNAND_PLAT_DATA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/clk-da8xx-cfgchip.h
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// SPDX-License-Identifier: GPL-2.0
/*
* clk-da8xx-cfgchip - TI DaVinci DA8xx CFGCHIP clock driver
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#ifndef __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
#define __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__
#include <linux/regmap.h>
/**
* da8xx_cfgchip_clk_platform_data
* @cfgchip: CFGCHIP syscon regmap
*/
struct da8xx_cfgchip_clk_platform_data {
struct regmap *cfgchip;
};
#endif /* __LINUX_PLATFORM_DATA_CLK_DA8XX_CFGCHIP_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/clk-fch.h
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/* SPDX-License-Identifier: MIT */
/*
* clock framework for AMD misc clocks
*
* Copyright 2018 Advanced Micro Devices, Inc.
*/
#ifndef __CLK_FCH_H
#define __CLK_FCH_H
#include <linux/compiler.h>
struct fch_clk_data {
void __iomem *base;
char *name;
};
#endif /* __CLK_FCH_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/cpuidle-exynos.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*/
#ifndef __CPUIDLE_EXYNOS_H
#define __CPUIDLE_EXYNOS_H
struct cpuidle_exynos_data {
int (*cpu0_enter_aftr)(void);
int (*cpu1_powerdown)(void);
void (*pre_enter_aftr)(void);
void (*post_enter_aftr)(void);
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/cros_ec_chardev.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* ChromeOS EC device interface.
*
* Copyright (C) 2014 Google, Inc.
*/
#ifndef _UAPI_LINUX_CROS_EC_DEV_H_
#define _UAPI_LINUX_CROS_EC_DEV_H_
#include <linux/bits.h>
#include <linux/ioctl.h>
#include <linux/types.h>
#include <linux/platform_data/cros_ec_commands.h>
#define CROS_EC_DEV_VERSION "1.0.0"
/**
* struct cros_ec_readmem - Struct used to read mapped memory.
* @offset: Within EC_LPC_ADDR_MEMMAP region.
* @bytes: Number of bytes to read. Zero means "read a string" (including '\0')
* At most only EC_MEMMAP_SIZE bytes can be read.
* @buffer: Where to store the result. The ioctl returns the number of bytes
* read or negative on error.
*/
struct cros_ec_readmem {
uint32_t offset;
uint32_t bytes;
uint8_t buffer[EC_MEMMAP_SIZE];
};
#define CROS_EC_DEV_IOC 0xEC
#define CROS_EC_DEV_IOCXCMD _IOWR(CROS_EC_DEV_IOC, 0, struct cros_ec_command)
#define CROS_EC_DEV_IOCRDMEM _IOWR(CROS_EC_DEV_IOC, 1, struct cros_ec_readmem)
#define CROS_EC_DEV_IOCEVENTMASK _IO(CROS_EC_DEV_IOC, 2)
#endif /* _CROS_EC_DEV_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/cros_ec_commands.h
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local/recipes/gpu/amdgpu-source/include/linux/platform_data/cros_ec_proto.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* ChromeOS Embedded Controller protocol interface.
*
* Copyright (C) 2012 Google, Inc
*/
#ifndef __LINUX_CROS_EC_PROTO_H
#define __LINUX_CROS_EC_PROTO_H
#include <linux/device.h>
#include <linux/lockdep_types.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/platform_data/cros_ec_commands.h>
#define CROS_EC_DEV_NAME "cros_ec"
#define CROS_EC_DEV_FP_NAME "cros_fp"
#define CROS_EC_DEV_ISH_NAME "cros_ish"
#define CROS_EC_DEV_PD_NAME "cros_pd"
#define CROS_EC_DEV_SCP_NAME "cros_scp"
#define CROS_EC_DEV_TP_NAME "cros_tp"
#define CROS_EC_DEV_EC_INDEX 0
#define CROS_EC_DEV_PD_INDEX 1
/*
* The EC is unresponsive for a time after a reboot command. Add a
* simple delay to make sure that the bus stays locked.
*/
#define EC_REBOOT_DELAY_MS 50
/*
* Max bus-specific overhead incurred by request/responses.
*
* Request:
* - I2C requires 1 byte (see struct ec_host_request_i2c).
* - ISHTP requires 4 bytes (see struct cros_ish_out_msg).
*
* Response:
* - I2C requires 2 bytes (see struct ec_host_response_i2c).
* - ISHTP requires 4 bytes (see struct cros_ish_in_msg).
* - SPI requires 32 bytes (see EC_MSG_PREAMBLE_COUNT).
*/
#define EC_PROTO_VERSION_UNKNOWN 0
#define EC_MAX_REQUEST_OVERHEAD 4
#define EC_MAX_RESPONSE_OVERHEAD 32
/*
* ACPI notify value for MKBP host event.
*/
#define ACPI_NOTIFY_CROS_EC_MKBP 0x80
/*
* EC panic is not covered by the standard (0-F) ACPI notify values.
* Arbitrarily choosing B0 to notify ec panic, which is in the 84-BF
* device specific ACPI notify range.
*/
#define ACPI_NOTIFY_CROS_EC_PANIC 0xB0
/*
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
*/
enum {
EC_MSG_TX_HEADER_BYTES = 3,
EC_MSG_TX_TRAILER_BYTES = 1,
EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES +
EC_MSG_TX_TRAILER_BYTES,
EC_MSG_RX_PROTO_BYTES = 3,
/* Max length of messages for proto 2*/
EC_PROTO2_MSG_BYTES = EC_PROTO2_MAX_PARAM_SIZE +
EC_MSG_TX_PROTO_BYTES,
EC_MAX_MSG_BYTES = 64 * 1024,
};
/**
* struct cros_ec_command - Information about a ChromeOS EC command.
* @version: Command version number (often 0).
* @command: Command to send (EC_CMD_...).
* @outsize: Outgoing length in bytes.
* @insize: Max number of bytes to accept from the EC.
* @result: EC's response to the command (separate from communication failure).
* @data: Where to put the incoming data from EC and outgoing data to EC.
*/
struct cros_ec_command {
uint32_t version;
uint32_t command;
uint32_t outsize;
uint32_t insize;
uint32_t result;
uint8_t data[];
};
/**
* struct cros_ec_device - Information about a ChromeOS EC device.
* @phys_name: Name of physical comms layer (e.g. 'i2c-4').
* @dev: Device pointer for physical comms device
* @cros_class: The class structure for this device.
* @cmd_readmem: Direct read of the EC memory-mapped region, if supported.
* @offset: Is within EC_LPC_ADDR_MEMMAP region.
* @bytes: Number of bytes to read. zero means "read a string" (including
* the trailing '\0'). At most only EC_MEMMAP_SIZE bytes can be
* read. Caller must ensure that the buffer is large enough for the
* result when reading a string.
* @max_request: Max size of message requested.
* @max_response: Max size of message response.
* @max_passthru: Max sice of passthru message.
* @proto_version: The protocol version used for this device.
* @priv: Private data.
* @irq: Interrupt to use.
* @id: Device id.
* @din: Input buffer (for data from EC). This buffer will always be
* dword-aligned and include enough space for up to 7 word-alignment
* bytes also, so we can ensure that the body of the message is always
* dword-aligned (64-bit). We use this alignment to keep ARM and x86
* happy. Probably word alignment would be OK, there might be a small
* performance advantage to using dword.
* @dout: Output buffer (for data to EC). This buffer will always be
* dword-aligned and include enough space for up to 7 word-alignment
* bytes also, so we can ensure that the body of the message is always
* dword-aligned (64-bit). We use this alignment to keep ARM and x86
* happy. Probably word alignment would be OK, there might be a small
* performance advantage to using dword.
* @din_size: Size of din buffer to allocate (zero to use static din).
* @dout_size: Size of dout buffer to allocate (zero to use static dout).
* @wake_enabled: True if this device can wake the system from sleep.
* @suspended: True if this device had been suspended.
* @registered: True if this device had been registered.
* @cmd_xfer: Send command to EC and get response.
* Returns the number of bytes received if the communication
* succeeded, but that doesn't mean the EC was happy with the
* command. The caller should check msg.result for the EC's result
* code.
* @pkt_xfer: Send packet to EC and get response.
* @lockdep_key: Lockdep class for each instance. Unused if CONFIG_LOCKDEP is
* not enabled.
* @lock: One transaction at a time.
* @mkbp_event_supported: 0 if MKBP not supported. Otherwise its value is
* the maximum supported version of the MKBP host event
* command + 1.
* @host_sleep_v1: True if this EC supports the sleep v1 command.
* @event_notifier: Interrupt event notifier for transport devices.
* @event_data: Raw payload transferred with the MKBP event.
* @event_size: Size in bytes of the event data.
* @host_event_wake_mask: Mask of host events that cause wake from suspend.
* @suspend_timeout_ms: The timeout in milliseconds between when sleep event
* is received and when the EC will declare sleep
* transition failure if the sleep signal is not
* asserted. See also struct
* ec_params_host_sleep_event_v1 in cros_ec_commands.h.
* @last_resume_result: The number of sleep power signal transitions that
* occurred since the suspend message. The high bit
* indicates a timeout occurred. See also struct
* ec_response_host_sleep_event_v1 in cros_ec_commands.h.
* @last_event_time: exact time from the hard irq when we got notified of
* a new event.
* @notifier_ready: The notifier_block to let the kernel re-query EC
* communication protocol when the EC sends
* EC_HOST_EVENT_INTERFACE_READY.
* @ec: The platform_device used by the mfd driver to interface with the
* main EC.
* @pd: The platform_device used by the mfd driver to interface with the
* PD behind an EC.
* @panic_notifier: EC panic notifier.
*/
struct cros_ec_device {
/* These are used by other drivers that want to talk to the EC */
const char *phys_name;
struct device *dev;
struct class *cros_class;
int (*cmd_readmem)(struct cros_ec_device *ec, unsigned int offset,
unsigned int bytes, void *dest);
/* These are used to implement the platform-specific interface */
u16 max_request;
u16 max_response;
u16 max_passthru;
u16 proto_version;
void *priv;
int irq;
u8 *din;
u8 *dout;
int din_size;
int dout_size;
bool wake_enabled;
bool suspended;
bool registered;
int (*cmd_xfer)(struct cros_ec_device *ec,
struct cros_ec_command *msg);
int (*pkt_xfer)(struct cros_ec_device *ec,
struct cros_ec_command *msg);
struct lock_class_key lockdep_key;
struct mutex lock;
u8 mkbp_event_supported;
bool host_sleep_v1;
struct blocking_notifier_head event_notifier;
struct ec_response_get_next_event_v3 event_data;
int event_size;
u32 host_event_wake_mask;
u32 last_resume_result;
u16 suspend_timeout_ms;
ktime_t last_event_time;
struct notifier_block notifier_ready;
/* The platform devices used by the mfd driver */
struct platform_device *ec;
struct platform_device *pd;
struct blocking_notifier_head panic_notifier;
};
/**
* struct cros_ec_platform - ChromeOS EC platform information.
* @ec_name: Name of EC device (e.g. 'cros-ec', 'cros-pd', ...)
* used in /dev/ and sysfs.
* @cmd_offset: Offset to apply for each command. Set when
* registering a device behind another one.
*/
struct cros_ec_platform {
const char *ec_name;
u16 cmd_offset;
};
/**
* struct cros_ec_dev - ChromeOS EC device entry point.
* @class_dev: Device structure used in sysfs.
* @ec_dev: cros_ec_device structure to talk to the physical device.
* @dev: Pointer to the platform device.
* @debug_info: cros_ec_debugfs structure for debugging information.
* @has_kb_wake_angle: True if at least 2 accelerometer are connected to the EC.
* @cmd_offset: Offset to apply for each command.
* @features: Features supported by the EC.
*/
struct cros_ec_dev {
struct device class_dev;
struct cros_ec_device *ec_dev;
struct device *dev;
struct cros_ec_debugfs *debug_info;
bool has_kb_wake_angle;
u16 cmd_offset;
struct ec_response_get_features features;
};
#define to_cros_ec_dev(dev) container_of(dev, struct cros_ec_dev, class_dev)
int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
int cros_ec_check_result(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev,
struct cros_ec_command *msg);
int cros_ec_rwsig_continue(struct cros_ec_device *ec_dev);
int cros_ec_query_all(struct cros_ec_device *ec_dev);
int cros_ec_get_next_event(struct cros_ec_device *ec_dev,
bool *wake_event,
bool *has_more_events);
u32 cros_ec_get_host_event(struct cros_ec_device *ec_dev);
bool cros_ec_check_features(struct cros_ec_dev *ec, int feature);
int cros_ec_get_sensor_count(struct cros_ec_dev *ec);
int cros_ec_cmd(struct cros_ec_device *ec_dev, unsigned int version, int command, const void *outdata,
size_t outsize, void *indata, size_t insize);
int cros_ec_cmd_readmem(struct cros_ec_device *ec_dev, u8 offset, u8 size, void *dest);
int cros_ec_get_cmd_versions(struct cros_ec_device *ec_dev, u16 cmd);
bool cros_ec_device_registered(struct cros_ec_device *ec_dev);
/**
* cros_ec_get_time_ns() - Return time in ns.
*
* This is the function used to record the time for last_event_time in struct
* cros_ec_device during the hard irq.
*
* Return: ktime_t format since boot.
*/
static inline ktime_t cros_ec_get_time_ns(void)
{
return ktime_get_boottime_ns();
}
#endif /* __LINUX_CROS_EC_PROTO_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/cros_ec_sensorhub.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Chrome OS EC MEMS Sensor Hub driver.
*
* Copyright 2019 Google LLC
*/
#ifndef __LINUX_PLATFORM_DATA_CROS_EC_SENSORHUB_H
#define __LINUX_PLATFORM_DATA_CROS_EC_SENSORHUB_H
#include <linux/ktime.h>
#include <linux/mutex.h>
#include <linux/notifier.h>
#include <linux/platform_data/cros_ec_commands.h>
struct iio_dev;
/**
* struct cros_ec_sensor_platform - ChromeOS EC sensor platform information.
* @sensor_num: Id of the sensor, as reported by the EC.
*/
struct cros_ec_sensor_platform {
u8 sensor_num;
};
/**
* typedef cros_ec_sensorhub_push_data_cb_t - Callback function to send datum
* to specific sensors.
*
* @indio_dev: The IIO device that will process the sample.
* @data: Vector array of the ring sample.
* @timestamp: Timestamp in host timespace when the sample was acquired by
* the EC.
*/
typedef int (*cros_ec_sensorhub_push_data_cb_t)(struct iio_dev *indio_dev,
s16 *data,
s64 timestamp);
struct cros_ec_sensorhub_sensor_push_data {
struct iio_dev *indio_dev;
cros_ec_sensorhub_push_data_cb_t push_data_cb;
};
enum {
CROS_EC_SENSOR_LAST_TS,
CROS_EC_SENSOR_NEW_TS,
CROS_EC_SENSOR_ALL_TS
};
struct cros_ec_sensors_ring_sample {
u8 sensor_id;
u8 flag;
s16 vector[3];
s64 timestamp;
} __packed;
/* State used for cros_ec_ring_fix_overflow */
struct cros_ec_sensors_ec_overflow_state {
s64 offset;
s64 last;
};
/* Length of the filter, how long to remember entries for */
#define CROS_EC_SENSORHUB_TS_HISTORY_SIZE 64
/**
* struct cros_ec_sensors_ts_filter_state - Timestamp filetr state.
*
* @x_offset: x is EC interrupt time. x_offset its last value.
* @y_offset: y is the difference between AP and EC time, y_offset its last
* value.
* @x_history: The past history of x, relative to x_offset.
* @y_history: The past history of y, relative to y_offset.
* @m_history: rate between y and x.
* @history_len: Amount of valid historic data in the arrays.
* @temp_buf: Temporary buffer used when updating the filter.
* @median_m: median value of m_history
* @median_error: final error to apply to AP interrupt timestamp to get the
* "true timestamp" the event occurred.
*/
struct cros_ec_sensors_ts_filter_state {
s64 x_offset, y_offset;
s64 x_history[CROS_EC_SENSORHUB_TS_HISTORY_SIZE];
s64 y_history[CROS_EC_SENSORHUB_TS_HISTORY_SIZE];
s64 m_history[CROS_EC_SENSORHUB_TS_HISTORY_SIZE];
int history_len;
s64 temp_buf[CROS_EC_SENSORHUB_TS_HISTORY_SIZE];
s64 median_m;
s64 median_error;
};
/* struct cros_ec_sensors_ts_batch_state - State of batch of a single sensor.
*
* Use to store information to batch data using median fileter information.
*
* @penul_ts: last but one batch timestamp (penultimate timestamp).
* Used for timestamp spreading calculations
* when a batch shows up.
* @penul_len: last but one batch length.
* @last_ts: Last batch timestam.
* @last_len: Last batch length.
* @newest_sensor_event: Last sensor timestamp.
*/
struct cros_ec_sensors_ts_batch_state {
s64 penul_ts;
int penul_len;
s64 last_ts;
int last_len;
s64 newest_sensor_event;
};
/*
* struct cros_ec_sensorhub - Sensor Hub device data.
*
* @dev: Device object, mostly used for logging.
* @ec: Embedded Controller where the hub is located.
* @sensor_num: Number of MEMS sensors present in the EC.
* @msg: Structure to send FIFO requests.
* @params: Pointer to parameters in msg.
* @resp: Pointer to responses in msg.
* @cmd_lock : Lock for sending msg.
* @notifier: Notifier to kick the FIFO interrupt.
* @ring: Preprocessed ring to store events.
* @fifo_timestamp: Array for event timestamp and spreading.
* @fifo_info: Copy of FIFO information coming from the EC.
* @fifo_size: Size of the ring.
* @batch_state: Per sensor information of the last batches received.
* @overflow_a: For handling timestamp overflow for a time (sensor events)
* @overflow_b: For handling timestamp overflow for b time (ec interrupts)
* @filter: Medium fileter structure.
* @tight_timestamps: Set to truen when EC support tight timestamping:
* The timestamps reported from the EC have low jitter.
* Timestamps also come before every sample. Set either
* by feature bits coming from the EC or userspace.
* @future_timestamp_count: Statistics used to compute shaved time.
* This occurs when timestamp interpolation from EC
* time to AP time accidentally puts timestamps in
* the future. These timestamps are clamped to
* `now` and these count/total_ns maintain the
* statistics for how much time was removed in a
* given period.
* @future_timestamp_total_ns: Total amount of time shaved.
* @push_data: Array of callback to send datums to iio sensor object.
*/
struct cros_ec_sensorhub {
struct device *dev;
struct cros_ec_dev *ec;
int sensor_num;
struct cros_ec_command *msg;
struct ec_params_motion_sense *params;
struct ec_response_motion_sense *resp;
struct mutex cmd_lock; /* Lock for protecting msg structure. */
struct notifier_block notifier;
struct cros_ec_sensors_ring_sample *ring;
ktime_t fifo_timestamp[CROS_EC_SENSOR_ALL_TS];
struct ec_response_motion_sense_fifo_info *fifo_info;
int fifo_size;
struct cros_ec_sensors_ts_batch_state *batch_state;
struct cros_ec_sensors_ec_overflow_state overflow_a;
struct cros_ec_sensors_ec_overflow_state overflow_b;
struct cros_ec_sensors_ts_filter_state filter;
int tight_timestamps;
s32 future_timestamp_count;
s64 future_timestamp_total_ns;
struct cros_ec_sensorhub_sensor_push_data *push_data;
};
int cros_ec_sensorhub_register_push_data(struct cros_ec_sensorhub *sensorhub,
u8 sensor_num,
struct iio_dev *indio_dev,
cros_ec_sensorhub_push_data_cb_t cb);
void cros_ec_sensorhub_unregister_push_data(struct cros_ec_sensorhub *sensorhub,
u8 sensor_num);
int cros_ec_sensorhub_ring_allocate(struct cros_ec_sensorhub *sensorhub);
int cros_ec_sensorhub_ring_add(struct cros_ec_sensorhub *sensorhub);
void cros_ec_sensorhub_ring_remove(void *arg);
int cros_ec_sensorhub_ring_fifo_enable(struct cros_ec_sensorhub *sensorhub,
bool on);
#endif /* __LINUX_PLATFORM_DATA_CROS_EC_SENSORHUB_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/cros_usbpd_notify.h
+17
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// SPDX-License-Identifier: GPL-2.0-only
/*
* ChromeOS EC Power Delivery Notifier Driver
*
* Copyright 2020 Google LLC
*/
#ifndef __LINUX_PLATFORM_DATA_CROS_USBPD_NOTIFY_H
#define __LINUX_PLATFORM_DATA_CROS_USBPD_NOTIFY_H
#include <linux/notifier.h>
int cros_usbpd_register_notify(struct notifier_block *nb);
void cros_usbpd_unregister_notify(struct notifier_block *nb);
#endif /* __LINUX_PLATFORM_DATA_CROS_USBPD_NOTIFY_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/crypto-ux500.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
*/
#ifndef _CRYPTO_UX500_H
#define _CRYPTO_UX500_H
#include <linux/dmaengine.h>
#include <linux/platform_data/dma-ste-dma40.h>
struct hash_platform_data {
void *mem_to_engine;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
struct cryp_platform_data {
struct stedma40_chan_cfg mem_to_engine;
struct stedma40_chan_cfg engine_to_mem;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/davinci-cpufreq.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* TI DaVinci CPUFreq platform support.
*
* Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
*/
#ifndef _MACH_DAVINCI_CPUFREQ_H
#define _MACH_DAVINCI_CPUFREQ_H
#include <linux/cpufreq.h>
struct davinci_cpufreq_config {
struct cpufreq_frequency_table *freq_table;
int (*set_voltage)(unsigned int index);
int (*init)(void);
};
#ifdef CONFIG_CPU_FREQ
int davinci_cpufreq_init(void);
#else
static inline int davinci_cpufreq_init(void) { return 0; }
#endif
#endif /* _MACH_DAVINCI_CPUFREQ_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/davinci_asp.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TI DaVinci Audio Serial Port support
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __DAVINCI_ASP_H
#define __DAVINCI_ASP_H
#include <linux/genalloc.h>
struct davinci_mcasp_pdata {
u32 tx_dma_offset;
u32 rx_dma_offset;
int asp_chan_q; /* event queue number for ASP channel */
int ram_chan_q; /* event queue number for RAM channel */
/*
* Allowing this is more efficient and eliminates left and right swaps
* caused by underruns, but will swap the left and right channels
* when compared to previous behavior.
*/
unsigned enable_channel_combine:1;
unsigned sram_size_playback;
unsigned sram_size_capture;
struct gen_pool *sram_pool;
/*
* This flag works when both clock and FS are outputs for the cpu
* and makes clock more accurate (FS is not symmetrical and the
* clock is very fast.
* The clock becoming faster is named
* i2s continuous serial clock (I2S_SCK) and it is an externally
* visible bit clock.
*
* first line : WordSelect
* second line : ContinuousSerialClock
* third line: SerialData
*
* SYMMETRICAL APPROACH:
* _______________________ LEFT
* _| RIGHT |______________________|
* _ _ _ _ _ _ _ _
* _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
* _ _ _ _ _ _ _ _
* _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
*
* ACCURATE CLOCK APPROACH:
* ______________ LEFT
* _| RIGHT |_______________________________|
* _ _ _ _ _ _ _ _ _
* _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
* _ _ _ _ dummy cycles
* _/ \_ ... _/ \_/ \_ ... _/ \__________________
* \_/ \_/ \_/ \_/
*
*/
bool i2s_accurate_sck;
/* McASP specific fields */
int tdm_slots_tx;
int tdm_slots_rx;
u8 op_mode;
u8 dismod;
u8 num_serializer;
u8 *serial_dir;
u8 version;
u8 txnumevt;
u8 rxnumevt;
int tx_dma_channel;
int rx_dma_channel;
};
/* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
#define snd_platform_data davinci_mcasp_pdata
enum {
MCASP_VERSION_1 = 0, /* DM646x */
MCASP_VERSION_2, /* DA8xx/OMAPL1x */
MCASP_VERSION_3, /* TI81xx/AM33xx */
MCASP_VERSION_4, /* DRA7xxx */
MCASP_VERSION_OMAP, /* OMAP4/5 */
};
#define INACTIVE_MODE 0
#define TX_MODE 1
#define RX_MODE 2
#define DAVINCI_MCASP_IIS_MODE 0
#define DAVINCI_MCASP_DIT_MODE 1
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dma-dw.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Driver for the Synopsys DesignWare DMA Controller
*
* Copyright (C) 2007 Atmel Corporation
* Copyright (C) 2010-2011 ST Microelectronics
*/
#ifndef _PLATFORM_DATA_DMA_DW_H
#define _PLATFORM_DATA_DMA_DW_H
#include <linux/bits.h>
#include <linux/types.h>
#define DW_DMA_MAX_NR_MASTERS 4
#define DW_DMA_MAX_NR_CHANNELS 8
#define DW_DMA_MIN_BURST 1
#define DW_DMA_MAX_BURST 256
struct device;
/**
* struct dw_dma_slave - Controller-specific information about a slave
*
* @dma_dev: required DMA master device
* @src_id: src request line
* @dst_id: dst request line
* @m_master: memory master for transfers on allocated channel
* @p_master: peripheral master for transfers on allocated channel
* @channels: mask of the channels permitted for allocation (zero value means any)
* @hs_polarity:set active low polarity of handshake interface
*/
struct dw_dma_slave {
struct device *dma_dev;
u8 src_id;
u8 dst_id;
u8 m_master;
u8 p_master;
u8 channels;
bool hs_polarity;
};
/**
* struct dw_dma_platform_data - Controller configuration parameters
* @nr_masters: Number of AHB masters supported by the controller
* @nr_channels: Number of channels supported by hardware (max 8)
* @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller
* @data_width: Maximum data width supported by hardware per AHB master
* (in bytes, power of 2)
* @multi_block: Multi block transfers supported by hardware per channel.
* @max_burst: Maximum value of burst transaction size supported by hardware
* per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
* @protctl: Protection control signals setting per channel.
* @quirks: Optional platform quirks.
*/
struct dw_dma_platform_data {
u32 nr_masters;
u32 nr_channels;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
u32 chan_allocation_order;
#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
u32 chan_priority;
u32 block_size;
u32 data_width[DW_DMA_MAX_NR_MASTERS];
u32 multi_block[DW_DMA_MAX_NR_CHANNELS];
u32 max_burst[DW_DMA_MAX_NR_CHANNELS];
#define CHAN_PROTCTL_PRIVILEGED BIT(0)
#define CHAN_PROTCTL_BUFFERABLE BIT(1)
#define CHAN_PROTCTL_CACHEABLE BIT(2)
#define CHAN_PROTCTL_MASK GENMASK(2, 0)
u32 protctl;
#define DW_DMA_QUIRK_XBAR_PRESENT BIT(0)
u32 quirks;
};
#endif /* _PLATFORM_DATA_DMA_DW_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dma-hsu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Driver for the High Speed UART DMA
*
* Copyright (C) 2015 Intel Corporation
*/
#ifndef _PLATFORM_DATA_DMA_HSU_H
#define _PLATFORM_DATA_DMA_HSU_H
struct device;
struct hsu_dma_slave {
struct device *dma_dev;
int chan_id;
};
#endif /* _PLATFORM_DATA_DMA_HSU_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dma-iop32x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright © 2006, Intel Corporation.
*/
#ifndef IOP_ADMA_H
#define IOP_ADMA_H
#include <linux/types.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#define IOP_ADMA_SLOT_SIZE 32
#define IOP_ADMA_THRESHOLD 4
#ifdef DEBUG
#define IOP_PARANOIA 1
#else
#define IOP_PARANOIA 0
#endif
#define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
#define DMA0_ID 0
#define DMA1_ID 1
#define AAU_ID 2
/**
* struct iop_adma_device - internal representation of an ADMA device
* @pdev: Platform device
* @id: HW ADMA Device selector
* @dma_desc_pool: base of DMA descriptor region (DMA address)
* @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
* @common: embedded struct dma_device
*/
struct iop_adma_device {
struct platform_device *pdev;
int id;
dma_addr_t dma_desc_pool;
void *dma_desc_pool_virt;
struct dma_device common;
};
/**
* struct iop_adma_chan - internal representation of an ADMA device
* @pending: allows batching of hardware operations
* @lock: serializes enqueue/dequeue operations to the slot pool
* @mmr_base: memory mapped register base
* @chain: device chain view of the descriptors
* @device: parent device
* @common: common dmaengine channel object members
* @last_used: place holder for allocation to continue from where it left off
* @all_slots: complete domain of slots usable by the channel
* @slots_allocated: records the actual size of the descriptor slot pool
* @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
*/
struct iop_adma_chan {
int pending;
spinlock_t lock; /* protects the descriptor slot pool */
void __iomem *mmr_base;
struct list_head chain;
struct iop_adma_device *device;
struct dma_chan common;
struct iop_adma_desc_slot *last_used;
struct list_head all_slots;
int slots_allocated;
struct tasklet_struct irq_tasklet;
};
/**
* struct iop_adma_desc_slot - IOP-ADMA software descriptor
* @slot_node: node on the iop_adma_chan.all_slots list
* @chain_node: node on the op_adma_chan.chain list
* @hw_desc: virtual address of the hardware descriptor chain
* @phys: hardware address of the hardware descriptor chain
* @group_head: first operation in a transaction
* @slot_cnt: total slots used in an transaction (group of operations)
* @slots_per_op: number of slots per operation
* @idx: pool index
* @tx_list: list of descriptors that are associated with one operation
* @async_tx: support for the async_tx api
* @group_list: list of slots that make up a multi-descriptor transaction
* for example transfer lengths larger than the supported hw max
* @xor_check_result: result of zero sum
* @crc32_result: result crc calculation
*/
struct iop_adma_desc_slot {
struct list_head slot_node;
struct list_head chain_node;
void *hw_desc;
struct iop_adma_desc_slot *group_head;
u16 slot_cnt;
u16 slots_per_op;
u16 idx;
struct list_head tx_list;
struct dma_async_tx_descriptor async_tx;
union {
u32 *xor_check_result;
u32 *crc32_result;
u32 *pq_check_result;
};
};
struct iop_adma_platform_data {
int hw_id;
dma_cap_mask_t cap_mask;
size_t pool_size;
};
#define to_iop_sw_desc(addr_hw_desc) \
container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
#define iop_hw_desc_slot_idx(hw_desc, idx) \
( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dma-mcf-edma.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Freescale eDMA platform data, ColdFire SoC's family.
*
* Copyright (c) 2017 Angelo Dureghello <angelo@sysam.it>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_PLATFORM_DATA_MCF_EDMA_H__
#define __LINUX_PLATFORM_DATA_MCF_EDMA_H__
struct dma_slave_map;
bool mcf_edma_filter_fn(struct dma_chan *chan, void *param);
#define MCF_EDMA_FILTER_PARAM(ch) ((void *)ch)
/**
* struct mcf_edma_platform_data - platform specific data for eDMA engine
*
* @dma_channels: The number of eDMA channels.
* @slave_map: Slave device map
* @slavecnt: Number of entries in @slave_map
*/
struct mcf_edma_platform_data {
int dma_channels;
const struct dma_slave_map *slave_map;
int slavecnt;
};
#endif /* __LINUX_PLATFORM_DATA_MCF_EDMA_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dma-mv_xor.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Marvell XOR platform device data definition file.
*/
#ifndef __DMA_MV_XOR_H
#define __DMA_MV_XOR_H
#include <linux/dmaengine.h>
#include <linux/mbus.h>
#define MV_XOR_NAME "mv_xor"
struct mv_xor_channel_data {
dma_cap_mask_t cap_mask;
};
struct mv_xor_platform_data {
struct mv_xor_channel_data *channels;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dmtimer-omap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* DMTIMER platform data for TI OMAP platforms
*
* Copyright (C) 2012 Texas Instruments
* Author: Jon Hunter <jon-hunter@ti.com>
*/
#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__
#define __PLATFORM_DATA_DMTIMER_OMAP_H__
struct omap_dm_timer_ops {
struct omap_dm_timer *(*request_by_node)(struct device_node *np);
struct omap_dm_timer *(*request_specific)(int timer_id);
struct omap_dm_timer *(*request)(void);
int (*free)(struct omap_dm_timer *timer);
void (*enable)(struct omap_dm_timer *timer);
void (*disable)(struct omap_dm_timer *timer);
int (*get_irq)(struct omap_dm_timer *timer);
int (*set_int_enable)(struct omap_dm_timer *timer,
unsigned int value);
int (*set_int_disable)(struct omap_dm_timer *timer, u32 mask);
struct clk *(*get_fclk)(struct omap_dm_timer *timer);
int (*start)(struct omap_dm_timer *timer);
int (*stop)(struct omap_dm_timer *timer);
int (*set_source)(struct omap_dm_timer *timer, int source);
int (*set_load)(struct omap_dm_timer *timer, unsigned int value);
int (*set_match)(struct omap_dm_timer *timer, int enable,
unsigned int match);
int (*set_pwm)(struct omap_dm_timer *timer, int def_on,
int toggle, int trigger, int autoreload);
int (*get_pwm_status)(struct omap_dm_timer *timer);
int (*set_cap)(struct omap_dm_timer *timer,
int autoreload, bool config_period);
int (*get_cap_status)(struct omap_dm_timer *timer);
int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler);
unsigned int (*read_counter)(struct omap_dm_timer *timer);
unsigned int (*read_cap)(struct omap_dm_timer *timer, bool is_period);
int (*write_counter)(struct omap_dm_timer *timer,
unsigned int value);
unsigned int (*read_status)(struct omap_dm_timer *timer);
int (*write_status)(struct omap_dm_timer *timer,
unsigned int value);
};
struct dmtimer_platform_data {
/* set_timer_src - Only used for OMAP1 devices */
int (*set_timer_src)(struct platform_device *pdev, int source);
u32 timer_capability;
u32 timer_errata;
int (*get_context_loss_count)(struct device *);
const struct omap_dm_timer_ops *timer_ops;
};
#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ds620.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_DS620_H
#define _LINUX_DS620_H
#include <linux/types.h>
#include <linux/i2c.h>
/* platform data for the DS620 temperature sensor and thermostat */
struct ds620_platform_data {
/*
* Thermostat output pin PO mode:
* 0 = always low (default)
* 1 = PO_LOW
* 2 = PO_HIGH
*
* (see Documentation/hwmon/ds620.rst)
*/
int pomode;
};
#endif /* _LINUX_DS620_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/dsa.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DSA_PDATA_H
#define __DSA_PDATA_H
struct device;
#define DSA_MAX_PORTS 12
struct dsa_chip_data {
/*
* Reference to network devices
*/
struct device *netdev[DSA_MAX_PORTS];
/* set to size of eeprom if supported by the switch */
int eeprom_len;
/*
* The names of the switch's ports. Use "cpu" to
* designate the switch port that the cpu is connected to,
* "dsa" to indicate that this port is a DSA link to
* another switch, NULL to indicate the port is unused,
* or any other string to indicate this is a physical port.
*/
char *port_names[DSA_MAX_PORTS];
};
#endif /* __DSA_PDATA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/edma.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* TI EDMA definitions
*
* Copyright (C) 2006-2013 Texas Instruments.
*/
/*
* This EDMA3 programming framework exposes two basic kinds of resource:
*
* Channel Triggers transfers, usually from a hardware event but
* also manually or by "chaining" from DMA completions.
* Each channel is coupled to a Parameter RAM (PaRAM) slot.
*
* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
* "set"), source and destination addresses, a link to a
* next PaRAM slot (if any), options for the transfer, and
* instructions for updating those addresses. There are
* more than twice as many slots as event channels.
*
* Each PaRAM set describes a sequence of transfers, either for one large
* buffer or for several discontiguous smaller buffers. An EDMA transfer
* is driven only from a channel, which performs the transfers specified
* in its PaRAM slot until there are no more transfers. When that last
* transfer completes, the "link" field may be used to reload the channel's
* PaRAM slot with a new transfer descriptor.
*
* The EDMA Channel Controller (CC) maps requests from channels into physical
* Transfer Controller (TC) requests when the channel triggers (by hardware
* or software events, or by chaining). The two physical DMA channels provided
* by the TCs are thus shared by many logical channels.
*
* DaVinci hardware also has a "QDMA" mechanism which is not currently
* supported through this interface. (DSP firmware uses it though.)
*/
#ifndef EDMA_H_
#define EDMA_H_
enum dma_event_q {
EVENTQ_0 = 0,
EVENTQ_1 = 1,
EVENTQ_2 = 2,
EVENTQ_3 = 3,
EVENTQ_DEFAULT = -1
};
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
#define EDMA_CTLR(i) ((i) >> 16)
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
#define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
struct edma_rsv_info {
const s16 (*rsv_chans)[2];
const s16 (*rsv_slots)[2];
};
struct dma_slave_map;
/* platform_data for EDMA driver */
struct edma_soc_info {
/*
* Default queue is expected to be a low-priority queue.
* This way, long transfers on the default queue started
* by the codec engine will not cause audio defects.
*/
enum dma_event_q default_queue;
/* Resource reservation for other cores */
struct edma_rsv_info *rsv;
/* List of channels allocated for memcpy, terminated with -1 */
s32 *memcpy_channels;
s8 (*queue_priority_mapping)[2];
const s16 (*xbar_chans)[2];
const struct dma_slave_map *slave_map;
int slavecnt;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/elm.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* BCH Error Location Module
*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ELM_H
#define __ELM_H
enum bch_ecc {
BCH4_ECC = 0,
BCH8_ECC,
BCH16_ECC,
};
/* ELM support 8 error syndrome process */
#define ERROR_VECTOR_MAX 8
/**
* struct elm_errorvec - error vector for elm
* @error_reported: set true for vectors error is reported
* @error_uncorrectable: number of uncorrectable errors
* @error_count: number of correctable errors in the sector
* @error_loc: buffer for error location
*
*/
struct elm_errorvec {
bool error_reported;
bool error_uncorrectable;
int error_count;
int error_loc[16];
};
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)
void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc,
struct elm_errorvec *err_vec);
int elm_config(struct device *dev, enum bch_ecc bch_type,
int ecc_steps, int ecc_step_size, int ecc_syndrome_size);
#else
static inline void
elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc,
struct elm_errorvec *err_vec)
{
}
static inline int elm_config(struct device *dev, enum bch_ecc bch_type,
int ecc_steps, int ecc_step_size,
int ecc_syndrome_size)
{
return -ENOSYS;
}
#endif /* CONFIG_MTD_NAND_OMAP_BCH */
#endif /* __ELM_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/emc2305.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_PLATFORM_DATA_EMC2305__
#define __LINUX_PLATFORM_DATA_EMC2305__
#define EMC2305_PWM_MAX 5
/**
* struct emc2305_platform_data - EMC2305 driver platform data
* @max_state: maximum cooling state of the cooling device;
* @pwm_num: number of active channels;
* @pwm_output_mask: PWM output mask
* @pwm_polarity_mask: PWM polarity mask
* @pwm_separate: separate PWM settings for every channel;
* @pwm_min: array of minimum PWM per channel;
* @pwm_freq: array of PWM frequency per channel
*/
struct emc2305_platform_data {
u8 max_state;
u8 pwm_num;
u8 pwm_output_mask;
u8 pwm_polarity_mask;
bool pwm_separate;
u8 pwm_min[EMC2305_PWM_MAX];
u16 pwm_freq[EMC2305_PWM_MAX];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/emif_plat.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Definitions for TI EMIF device platform data
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* Aneesh V <aneesh@ti.com>
*/
#ifndef __EMIF_PLAT_H
#define __EMIF_PLAT_H
/* Low power modes - EMIF_PWR_MGMT_CTRL */
#define EMIF_LP_MODE_DISABLE 0
#define EMIF_LP_MODE_CLOCK_STOP 1
#define EMIF_LP_MODE_SELF_REFRESH 2
#define EMIF_LP_MODE_PWR_DN 4
/* Hardware capabilities */
#define EMIF_HW_CAPS_LL_INTERFACE 0x00000001
/*
* EMIF IP Revisions
* EMIF4D - Used in OMAP4
* EMIF4D5 - Used in OMAP5
*/
#define EMIF_4D 1
#define EMIF_4D5 2
/*
* PHY types
* ATTILAPHY - Used in OMAP4
* INTELLIPHY - Used in OMAP5
*/
#define EMIF_PHY_TYPE_ATTILAPHY 1
#define EMIF_PHY_TYPE_INTELLIPHY 2
/* Custom config requests */
#define EMIF_CUSTOM_CONFIG_LPMODE 0x00000001
#define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL 0x00000002
#define EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART 0x00000004
#ifndef __ASSEMBLY__
/**
* struct ddr_device_info - All information about the DDR device except AC
* timing parameters
* @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
* @density: Device density
* @io_width: Bus width
* @cs1_used: Whether there is a DDR device attached to the second
* chip-select(CS1) of this EMIF instance
* @cal_resistors_per_cs: Whether there is one calibration resistor per
* chip-select or whether it's a single one for both
* @manufacturer: Manufacturer name string
*/
struct ddr_device_info {
u32 type;
u32 density;
u32 io_width;
u32 cs1_used;
u32 cal_resistors_per_cs;
char manufacturer[10];
};
/**
* struct emif_custom_configs - Custom configuration parameters/policies
* passed from the platform layer
* @mask: Mask to indicate which configs are requested
* @lpmode: LPMODE to be used in PWR_MGMT_CTRL register
* @lpmode_timeout_performance: Timeout before LPMODE entry when higher
* performance is desired at the cost of power (typically
* at higher OPPs)
* @lpmode_timeout_power: Timeout before LPMODE entry when better power
* savings is desired and performance is not important
* (typically at lower loads indicated by lower OPPs)
* @lpmode_freq_threshold: The DDR frequency threshold to identify between
* the above two cases:
* timeout = (freq >= lpmode_freq_threshold) ?
* lpmode_timeout_performance :
* lpmode_timeout_power;
* @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal
* temperature(in milliseconds). When temperature is high
* polling is done 4 times as frequently.
*/
struct emif_custom_configs {
u32 mask;
u32 lpmode;
u32 lpmode_timeout_performance;
u32 lpmode_timeout_power;
u32 lpmode_freq_threshold;
u32 temp_alert_poll_interval_ms;
};
/**
* struct emif_platform_data - Platform data passed on EMIF platform
* device creation. Used by the driver.
* @hw_caps: Hw capabilities of the EMIF IP in the respective SoC
* @device_info: Device info structure containing information such
* as type, bus width, density etc
* @timings: Timings information from device datasheet passed
* as an array of 'struct lpddr2_timings'. Can be NULL
* if if default timings are ok
* @timings_arr_size: Size of the timings array. Depends on the number
* of different frequencies for which timings data
* is provided
* @min_tck: Minimum value of some timing parameters in terms
* of number of cycles. Can be NULL if default values
* are ok
* @custom_configs: Custom configurations requested by SoC or board
* code and the data for them. Can be NULL if default
* configurations done by the driver are ok. See
* documentation for 'struct emif_custom_configs' for
* more details
*/
struct emif_platform_data {
u32 hw_caps;
struct ddr_device_info *device_info;
const struct lpddr2_timings *timings;
u32 timings_arr_size;
const struct lpddr2_min_tck *min_tck;
struct emif_custom_configs *custom_configs;
u32 ip_rev;
u32 phy_type;
};
#endif /* __ASSEMBLY__ */
#endif /* __LINUX_EMIF_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/g762.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Platform data structure for g762 fan controller driver
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
*/
#ifndef __LINUX_PLATFORM_DATA_G762_H__
#define __LINUX_PLATFORM_DATA_G762_H__
/*
* Following structure can be used to set g762 driver platform specific data
* during board init. Note that passing a sparse structure is possible but
* will result in non-specified attributes to be set to default value, hence
* overloading those installed during boot (e.g. by u-boot).
*/
struct g762_platform_data {
u32 fan_startv;
u32 fan_gear_mode;
u32 pwm_polarity;
u32 clk_freq;
};
#endif /* __LINUX_PLATFORM_DATA_G762_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gpio-htc-egpio.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* HTC simple EGPIO irq and gpio extender
*/
#ifndef __HTC_EGPIO_H__
#define __HTC_EGPIO_H__
/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
#define HTC_EGPIO_OUTPUT (~0)
#define HTC_EGPIO_INPUT 0
/**
* struct htc_egpio_chip - descriptor to create gpio_chip for register range
* @reg_start: index of first register
* @gpio_base: gpio number of first pin in this register range
* @num_gpios: number of gpios in this register range, max BITS_PER_LONG
* (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
* @direction: bitfield, '0' = input, '1' = output,
*/
struct htc_egpio_chip {
int reg_start;
int gpio_base;
int num_gpios;
unsigned long direction;
unsigned long initial_values;
};
/**
* struct htc_egpio_platform_data - description provided by the arch
* @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
* @num_irqs: number of irqs
* @reg_width: number of bits per register, either 8 or 16 bit
* @bus_width: alignment of the registers, either 16 or 32 bit
* @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
* @ack_register: location of the irq/ack register
* @chip: pointer to array of htc_egpio_chip descriptors
* @num_chips: number of egpio chip descriptors
*/
struct htc_egpio_platform_data {
int bus_width;
int reg_width;
int irq_base;
int num_irqs;
int invert_acks;
int ack_register;
struct htc_egpio_chip *chip;
int num_chips;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gpio-omap.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* OMAP GPIO handling defines and functions
*
* Copyright (C) 2003-2005 Nokia Corporation
*
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*/
#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H
#ifndef __ASSEMBLER__
#include <linux/io.h>
#include <linux/platform_device.h>
#endif
#define OMAP1_MPUIO_BASE 0xfffb5000
/*
* These are the omap15xx/16xx offsets. The omap7xx offset are
* OMAP_MPUIO_ / 2 offsets below.
*/
#define OMAP_MPUIO_INPUT_LATCH 0x00
#define OMAP_MPUIO_OUTPUT 0x04
#define OMAP_MPUIO_IO_CNTL 0x08
#define OMAP_MPUIO_KBR_LATCH 0x10
#define OMAP_MPUIO_KBC 0x14
#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
#define OMAP_MPUIO_KBD_INT 0x20
#define OMAP_MPUIO_GPIO_INT 0x24
#define OMAP_MPUIO_KBD_MASKIT 0x28
#define OMAP_MPUIO_GPIO_MASKIT 0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
#define OMAP_MPUIO_LATCH 0x34
#define OMAP34XX_NR_GPIOS 6
/*
* OMAP1510 GPIO registers
*/
#define OMAP1510_GPIO_DATA_INPUT 0x00
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
#define OMAP1510_GPIO_DIR_CONTROL 0x08
#define OMAP1510_GPIO_INT_CONTROL 0x0c
#define OMAP1510_GPIO_INT_MASK 0x10
#define OMAP1510_GPIO_INT_STATUS 0x14
#define OMAP1510_GPIO_PIN_CONTROL 0x18
#define OMAP1510_IH_GPIO_BASE 64
/*
* OMAP1610 specific GPIO registers
*/
#define OMAP1610_GPIO_REVISION 0x0000
#define OMAP1610_GPIO_SYSCONFIG 0x0010
#define OMAP1610_GPIO_SYSSTATUS 0x0014
#define OMAP1610_GPIO_IRQSTATUS1 0x0018
#define OMAP1610_GPIO_IRQENABLE1 0x001c
#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
#define OMAP1610_GPIO_DATAIN 0x002c
#define OMAP1610_GPIO_DATAOUT 0x0030
#define OMAP1610_GPIO_DIRECTION 0x0034
#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
/*
* OMAP7XX specific GPIO registers
*/
#define OMAP7XX_GPIO_DATA_INPUT 0x00
#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
#define OMAP7XX_GPIO_DIR_CONTROL 0x08
#define OMAP7XX_GPIO_INT_CONTROL 0x0c
#define OMAP7XX_GPIO_INT_MASK 0x10
#define OMAP7XX_GPIO_INT_STATUS 0x14
/*
* omap2+ specific GPIO registers
*/
#define OMAP24XX_GPIO_REVISION 0x0000
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
#define OMAP24XX_GPIO_IRQENABLE2 0x002c
#define OMAP24XX_GPIO_IRQENABLE1 0x001c
#define OMAP24XX_GPIO_WAKE_EN 0x0020
#define OMAP24XX_GPIO_CTRL 0x0030
#define OMAP24XX_GPIO_OE 0x0034
#define OMAP24XX_GPIO_DATAIN 0x0038
#define OMAP24XX_GPIO_DATAOUT 0x003c
#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
#define OMAP24XX_GPIO_RISINGDETECT 0x0048
#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
#define OMAP24XX_GPIO_SETWKUENA 0x0084
#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
#define OMAP24XX_GPIO_SETDATAOUT 0x0094
#define OMAP4_GPIO_REVISION 0x0000
#define OMAP4_GPIO_SYSCONFIG 0x0010
#define OMAP4_GPIO_EOI 0x0020
#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
#define OMAP4_GPIO_IRQSTATUS0 0x002c
#define OMAP4_GPIO_IRQSTATUS1 0x0030
#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
#define OMAP4_GPIO_IRQWAKEN0 0x0044
#define OMAP4_GPIO_IRQWAKEN1 0x0048
#define OMAP4_GPIO_IRQENABLE1 0x011c
#define OMAP4_GPIO_WAKE_EN 0x0120
#define OMAP4_GPIO_IRQSTATUS2 0x0128
#define OMAP4_GPIO_IRQENABLE2 0x012c
#define OMAP4_GPIO_CTRL 0x0130
#define OMAP4_GPIO_OE 0x0134
#define OMAP4_GPIO_DATAIN 0x0138
#define OMAP4_GPIO_DATAOUT 0x013c
#define OMAP4_GPIO_LEVELDETECT0 0x0140
#define OMAP4_GPIO_LEVELDETECT1 0x0144
#define OMAP4_GPIO_RISINGDETECT 0x0148
#define OMAP4_GPIO_FALLINGDETECT 0x014c
#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
#define OMAP4_GPIO_SETIRQENABLE1 0x0164
#define OMAP4_GPIO_CLEARWKUENA 0x0180
#define OMAP4_GPIO_SETWKUENA 0x0184
#define OMAP4_GPIO_CLEARDATAOUT 0x0190
#define OMAP4_GPIO_SETDATAOUT 0x0194
#define OMAP_MAX_GPIO_LINES 192
#ifndef __ASSEMBLER__
struct omap_gpio_reg_offs {
u16 revision;
u16 sysconfig;
u16 direction;
u16 datain;
u16 dataout;
u16 set_dataout;
u16 clr_dataout;
u16 irqstatus;
u16 irqstatus2;
u16 irqstatus_raw0;
u16 irqstatus_raw1;
u16 irqenable;
u16 irqenable2;
u16 set_irqenable;
u16 clr_irqenable;
u16 debounce;
u16 debounce_en;
u16 ctrl;
u16 wkup_en;
u16 leveldetect0;
u16 leveldetect1;
u16 risingdetect;
u16 fallingdetect;
u16 irqctrl;
u16 edgectrl1;
u16 edgectrl2;
u16 pinctrl;
bool irqenable_inv;
};
struct omap_gpio_platform_data {
int bank_type;
int bank_width; /* GPIO bank width */
int bank_stride; /* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
bool loses_context; /* whether the bank would ever lose context */
bool is_mpuio; /* whether the bank is of type MPUIO */
u32 non_wakeup_gpios;
const struct omap_gpio_reg_offs *regs;
/* Return context loss count due to PM states changing */
int (*get_context_loss_count)(struct device *dev);
};
#endif /* __ASSEMBLER__ */
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gpio/gpio-amd-fch.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* AMD FCH gpio driver platform-data
*
* Copyright (C) 2018 metux IT consult
* Author: Enrico Weigelt <info@metux.net>
*
*/
#ifndef __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H
#define __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H
#define AMD_FCH_GPIO_DRIVER_NAME "gpio_amd_fch"
/*
* gpio register index definitions
*/
#define AMD_FCH_GPIO_REG_GPIO49 0x40
#define AMD_FCH_GPIO_REG_GPIO50 0x41
#define AMD_FCH_GPIO_REG_GPIO51 0x42
#define AMD_FCH_GPIO_REG_GPIO55_DEVSLP0 0x43
#define AMD_FCH_GPIO_REG_GPIO57 0x44
#define AMD_FCH_GPIO_REG_GPIO58 0x45
#define AMD_FCH_GPIO_REG_GPIO59_DEVSLP1 0x46
#define AMD_FCH_GPIO_REG_GPIO64 0x47
#define AMD_FCH_GPIO_REG_GPIO68 0x48
#define AMD_FCH_GPIO_REG_GPIO66_SPKR 0x5B
#define AMD_FCH_GPIO_REG_GPIO71 0x4D
#define AMD_FCH_GPIO_REG_GPIO32_GE1 0x59
#define AMD_FCH_GPIO_REG_GPIO33_GE2 0x5A
#define AMT_FCH_GPIO_REG_GEVT22 0x09
/*
* struct amd_fch_gpio_pdata - GPIO chip platform data
* @gpio_num: number of entries
* @gpio_reg: array of gpio registers
* @gpio_names: array of gpio names
*/
struct amd_fch_gpio_pdata {
int gpio_num;
int *gpio_reg;
const char * const *gpio_names;
};
#endif /* __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gpio_backlight.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* gpio_backlight.h - Simple GPIO-controlled backlight
*/
#ifndef __GPIO_BACKLIGHT_H__
#define __GPIO_BACKLIGHT_H__
struct device;
struct gpio_backlight_platform_data {
struct device *dev;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gpmc-omap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* OMAP GPMC Platform data
*
* Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
* Roger Quadros <rogerq@ti.com>
*/
#ifndef _GPMC_OMAP_H_
#define _GPMC_OMAP_H_
/* Maximum Number of Chip Selects */
#define GPMC_CS_NUM 8
/* bool type time settings */
struct gpmc_bool_timings {
bool cycle2cyclediffcsen;
bool cycle2cyclesamecsen;
bool we_extra_delay;
bool oe_extra_delay;
bool adv_extra_delay;
bool cs_extra_delay;
bool time_para_granularity;
};
/*
* Note that all values in this struct are in nanoseconds except sync_clk
* (which is in picoseconds), while the register values are in gpmc_fck cycles.
*/
struct gpmc_timings {
/* Minimum clock period for synchronous mode (in picoseconds) */
u32 sync_clk;
/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
u32 cs_on; /* Assertion time */
u32 cs_rd_off; /* Read deassertion time */
u32 cs_wr_off; /* Write deassertion time */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
u32 adv_on; /* Assertion time */
u32 adv_rd_off; /* Read deassertion time */
u32 adv_wr_off; /* Write deassertion time */
u32 adv_aad_mux_on; /* ADV assertion time for AAD */
u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
/* WE signals timings corresponding to GPMC_CONFIG4 */
u32 we_on; /* WE assertion time */
u32 we_off; /* WE deassertion time */
/* OE signals timings corresponding to GPMC_CONFIG4 */
u32 oe_on; /* OE assertion time */
u32 oe_off; /* OE deassertion time */
u32 oe_aad_mux_on; /* OE assertion time for AAD */
u32 oe_aad_mux_off; /* OE deassertion time for AAD */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
u32 page_burst_access; /* Multiple access word delay */
u32 access; /* Start-cycle to first data valid delay */
u32 rd_cycle; /* Total read cycle time */
u32 wr_cycle; /* Total write cycle time */
u32 bus_turnaround;
u32 cycle2cycle_delay;
u32 wait_monitoring;
u32 clk_activation;
/* The following are only on OMAP3430 */
u32 wr_access; /* WRACCESSTIME */
u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
struct gpmc_bool_timings bool_timings;
};
/* Device timings in picoseconds */
struct gpmc_device_timings {
u32 t_ceasu; /* address setup to CS valid */
u32 t_avdasu; /* address setup to ADV valid */
/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
* of tusb using these timings even for sync whilst
* ideally for adv_rd/(wr)_off it should have considered
* t_avdh instead. This indirectly necessitates r/w
* variations of t_avdp as it is possible to have one
* sync & other async
*/
u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
u32 t_avdp_w;
u32 t_aavdh; /* address hold time */
u32 t_oeasu; /* address setup to OE valid */
u32 t_aa; /* access time from ADV assertion */
u32 t_iaa; /* initial access time */
u32 t_oe; /* access time from OE assertion */
u32 t_ce; /* access time from CS asertion */
u32 t_rd_cycle; /* read cycle time */
u32 t_cez_r; /* read CS deassertion to high Z */
u32 t_cez_w; /* write CS deassertion to high Z */
u32 t_oez; /* OE deassertion to high Z */
u32 t_weasu; /* address setup to WE valid */
u32 t_wpl; /* write assertion time */
u32 t_wph; /* write deassertion time */
u32 t_wr_cycle; /* write cycle time */
u32 clk;
u32 t_bacc; /* burst access valid clock to output delay */
u32 t_ces; /* CS setup time to clk */
u32 t_avds; /* ADV setup time to clk */
u32 t_avdh; /* ADV hold time from clk */
u32 t_ach; /* address hold time from clk */
u32 t_rdyo; /* clk to ready valid */
u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
u32 t_ce_avd; /* CS on to ADV on delay */
/* XXX: check the possibility of combining
* cyc_aavhd_oe & cyc_aavdh_we
*/
u8 cyc_aavdh_oe;/* read address hold time in cycles */
u8 cyc_aavdh_we;/* write address hold time in cycles */
u8 cyc_oe; /* access time from OE assertion in cycles */
u8 cyc_wpl; /* write deassertion time in cycles */
u32 cyc_iaa; /* initial access time in cycles */
/* extra delays */
bool ce_xdelay;
bool avd_xdelay;
bool oe_xdelay;
bool we_xdelay;
};
#define GPMC_BURST_4 4 /* 4 word burst */
#define GPMC_BURST_8 8 /* 8 word burst */
#define GPMC_BURST_16 16 /* 16 word burst */
#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
/* Wait pin polarity values */
#define GPMC_WAITPINPOLARITY_INVALID UINT_MAX
#define GPMC_WAITPINPOLARITY_ACTIVE_LOW 0
#define GPMC_WAITPINPOLARITY_ACTIVE_HIGH 1
#define GPMC_WAITPIN_INVALID UINT_MAX
struct gpmc_settings {
bool burst_wrap; /* enables wrap bursting */
bool burst_read; /* enables read page/burst mode */
bool burst_write; /* enables write page/burst mode */
bool device_nand; /* device is NAND */
bool sync_read; /* enables synchronous reads */
bool sync_write; /* enables synchronous writes */
bool wait_on_read; /* monitor wait on reads */
bool wait_on_write; /* monitor wait on writes */
u32 burst_len; /* page/burst length */
u32 device_width; /* device bus width (8 or 16 bit) */
u32 mux_add_data; /* multiplex address & data */
u32 wait_pin; /* wait-pin to be used */
u32 wait_pin_polarity;
};
/* Data for each chip select */
struct gpmc_omap_cs_data {
bool valid; /* data is valid */
bool is_nand; /* device within this CS is NAND */
struct gpmc_settings *settings;
struct gpmc_device_timings *device_timings;
struct gpmc_timings *gpmc_timings;
struct platform_device *pdev; /* device within this CS region */
unsigned int pdata_size;
};
struct gpmc_omap_platform_data {
struct gpmc_omap_cs_data cs[GPMC_CS_NUM];
};
#endif /* _GPMC_OMAP_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/gsc_hwmon.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _GSC_HWMON_H
#define _GSC_HWMON_H
enum gsc_hwmon_mode {
mode_temperature,
mode_voltage_24bit,
mode_voltage_raw,
mode_voltage_16bit,
mode_fan,
mode_max,
};
/**
* struct gsc_hwmon_channel - configuration parameters
* @reg: I2C register offset
* @mode: channel mode
* @name: channel name
* @mvoffset: voltage offset
* @vdiv: voltage divider array (2 resistor values in milli-ohms)
*/
struct gsc_hwmon_channel {
unsigned int reg;
unsigned int mode;
const char *name;
unsigned int mvoffset;
unsigned int vdiv[2];
};
/**
* struct gsc_hwmon_platform_data - platform data for gsc_hwmon driver
* @nchannels: number of elements in @channels array
* @vreference: voltage reference (mV)
* @resolution: ADC bit resolution
* @fan_base: register base for FAN controller
* @channels: array of gsc_hwmon_channel structures describing channels
*/
struct gsc_hwmon_platform_data {
int nchannels;
unsigned int resolution;
unsigned int vreference;
unsigned int fan_base;
struct gsc_hwmon_channel channels[] __counted_by(nchannels);
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/hirschmann-hellcreek.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Hirschmann Hellcreek TSN switch platform data.
*
* Copyright (C) 2020 Linutronix GmbH
* Author Kurt Kanzenbach <kurt@linutronix.de>
*/
#ifndef _HIRSCHMANN_HELLCREEK_H_
#define _HIRSCHMANN_HELLCREEK_H_
#include <linux/types.h>
struct hellcreek_platform_data {
const char *name; /* Switch name */
int num_ports; /* Amount of switch ports */
int is_100_mbits; /* Is it configured to 100 or 1000 mbit/s */
int qbv_support; /* Qbv support on front TSN ports */
int qbv_on_cpu_port; /* Qbv support on the CPU port */
int qbu_support; /* Qbu support on front TSN ports */
u16 module_id; /* Module identificaton */
};
#endif /* _HIRSCHMANN_HELLCREEK_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/hsmmc-omap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MMC definitions for OMAP2
*
* Copyright (C) 2006 Nokia Corporation
*/
/*
* struct omap_hsmmc_dev_attr.flags possibilities
*
* OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
* operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
* should be set if this is the case. See for example Section 22.5.3
* "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
* Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
*
* OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
* don't work correctly on some MMC controller instances on some
* OMAP3 SoCs; this flag should be set if this is the case. See
* for example Advisory 2.1.1.128 "MMC: Multiple Block Read
* Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
* Revision F (October 2010) (SPRZ278F).
*/
#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)
#define OMAP_HSMMC_SWAKEUP_MISSING BIT(2)
struct omap_hsmmc_dev_attr {
u8 flags;
};
struct mmc_card;
struct omap_hsmmc_platform_data {
/* back-link to device */
struct device *dev;
/* set if your board has components or wiring that limits the
* maximum frequency on the MMC bus */
unsigned int max_freq;
/* Integrating attributes from the omap_hwmod layer */
u8 controller_flags;
/* Register offset deviation */
u16 reg_offset;
/*
* 4/8 wires and any additional host capabilities
* need to OR'd all capabilities (ref. linux/mmc/host.h)
*/
u32 caps; /* Used for the MMC driver on 2430 and later */
u32 pm_caps; /* PM capabilities of the mmc */
/* nonremovable e.g. eMMC */
unsigned nonremovable:1;
/* eMMC does not handle power off when not in sleep state */
unsigned no_regulator_off_init:1;
/* we can put the features above into this variable */
#define HSMMC_HAS_PBIAS (1 << 0)
#define HSMMC_HAS_UPDATED_RESET (1 << 1)
#define HSMMC_HAS_HSPE_SUPPORT (1 << 2)
unsigned features;
/* string specifying a particular variant of hardware */
char *version;
const char *name;
u32 ocr_mask;
};
local/recipes/gpu/amdgpu-source/include/linux/platform_data/huawei-gaokun-ec.h
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Huawei Matebook E Go Embedded Controller
*
* Copyright (C) 2024-2025 Pengyu Luo <mitltlatltl@gmail.com>
*/
#ifndef __HUAWEI_GAOKUN_EC_H__
#define __HUAWEI_GAOKUN_EC_H__
#define GAOKUN_UCSI_CCI_SIZE 4
#define GAOKUN_UCSI_MSGI_SIZE 16
#define GAOKUN_UCSI_READ_SIZE (GAOKUN_UCSI_CCI_SIZE + GAOKUN_UCSI_MSGI_SIZE)
#define GAOKUN_UCSI_WRITE_SIZE 24 /* 8B CTRL, 16B MSGO */
#define GAOKUN_UCSI_NO_PORT_UPDATE (-1)
#define GAOKUN_SMART_CHARGE_DATA_SIZE 4 /* mode, delay, start, end */
/* -------------------------------------------------------------------------- */
struct gaokun_ec;
struct gaokun_ucsi_reg;
struct notifier_block;
#define GAOKUN_MOD_NAME "huawei_gaokun_ec"
#define GAOKUN_DEV_PSY "psy"
#define GAOKUN_DEV_UCSI "ucsi"
/* -------------------------------------------------------------------------- */
/* Common API */
int gaokun_ec_register_notify(struct gaokun_ec *ec,
struct notifier_block *nb);
void gaokun_ec_unregister_notify(struct gaokun_ec *ec,
struct notifier_block *nb);
int gaokun_ec_read(struct gaokun_ec *ec, const u8 *req,
size_t resp_len, u8 *resp);
int gaokun_ec_write(struct gaokun_ec *ec, const u8 *req);
int gaokun_ec_read_byte(struct gaokun_ec *ec, const u8 *req, u8 *byte);
/* -------------------------------------------------------------------------- */
/* API for PSY */
int gaokun_ec_psy_multi_read(struct gaokun_ec *ec, u8 reg,
size_t resp_len, u8 *resp);
static inline int gaokun_ec_psy_read_byte(struct gaokun_ec *ec,
u8 reg, u8 *byte)
{
return gaokun_ec_psy_multi_read(ec, reg, sizeof(*byte), byte);
}
static inline int gaokun_ec_psy_read_word(struct gaokun_ec *ec,
u8 reg, u16 *word)
{
return gaokun_ec_psy_multi_read(ec, reg, sizeof(*word), (u8 *)word);
}
int gaokun_ec_psy_get_smart_charge(struct gaokun_ec *ec,
u8 resp[GAOKUN_SMART_CHARGE_DATA_SIZE]);
int gaokun_ec_psy_set_smart_charge(struct gaokun_ec *ec,
const u8 req[GAOKUN_SMART_CHARGE_DATA_SIZE]);
int gaokun_ec_psy_get_smart_charge_enable(struct gaokun_ec *ec, bool *on);
int gaokun_ec_psy_set_smart_charge_enable(struct gaokun_ec *ec, bool on);
/* -------------------------------------------------------------------------- */
/* API for UCSI */
int gaokun_ec_ucsi_read(struct gaokun_ec *ec, u8 resp[GAOKUN_UCSI_READ_SIZE]);
int gaokun_ec_ucsi_write(struct gaokun_ec *ec,
const u8 req[GAOKUN_UCSI_WRITE_SIZE]);
int gaokun_ec_ucsi_get_reg(struct gaokun_ec *ec, struct gaokun_ucsi_reg *ureg);
int gaokun_ec_ucsi_pan_ack(struct gaokun_ec *ec, int port_id);
#endif /* __HUAWEI_GAOKUN_EC_H__ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-gpio.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* i2c-gpio interface to platform code
*
* Copyright (C) 2007 Atmel Corporation
*/
#ifndef _LINUX_I2C_GPIO_H
#define _LINUX_I2C_GPIO_H
/**
* struct i2c_gpio_platform_data - Platform-dependent data for i2c-gpio
* @udelay: signal toggle delay. SCL frequency is (500 / udelay) kHz
* @timeout: clock stretching timeout in jiffies. If the slave keeps
* SCL low for longer than this, the transfer will time out.
* @sda_is_open_drain: SDA is configured as open drain, i.e. the pin
* isn't actively driven high when setting the output value high.
* gpio_get_value() must return the actual pin state even if the
* pin is configured as an output.
* @sda_is_output_only: SDA output drivers can't be turned off.
* This is for clients that can only read SDA/SCL.
* @sda_has_no_pullup: SDA is used in a non-compliant way and has no pull-up.
* Therefore disable open-drain.
* @scl_is_open_drain: SCL is set up as open drain. Same requirements
* as for sda_is_open_drain apply.
* @scl_is_output_only: SCL output drivers cannot be turned off.
* @scl_has_no_pullup: SCL is used in a non-compliant way and has no pull-up.
* Therefore disable open-drain.
*/
struct i2c_gpio_platform_data {
int udelay;
int timeout;
unsigned int sda_is_open_drain:1;
unsigned int sda_is_output_only:1;
unsigned int sda_has_no_pullup:1;
unsigned int scl_is_open_drain:1;
unsigned int scl_is_output_only:1;
unsigned int scl_has_no_pullup:1;
};
#endif /* _LINUX_I2C_GPIO_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-imx.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* i2c.h - i.MX I2C driver header file
*
* Copyright (c) 2008, Darius Augulis <augulis.darius@gmail.com>
*/
#ifndef __ASM_ARCH_I2C_H_
#define __ASM_ARCH_I2C_H_
/**
* struct imxi2c_platform_data - structure of platform data for MXC I2C driver
* @bitrate: Bus speed measured in Hz
*
**/
struct imxi2c_platform_data {
u32 bitrate;
};
#endif /* __ASM_ARCH_I2C_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-mux-gpio.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* i2c-mux-gpio interface to platform code
*
* Peter Korsgaard <peter.korsgaard@barco.com>
*/
#ifndef _LINUX_I2C_MUX_GPIO_H
#define _LINUX_I2C_MUX_GPIO_H
/* MUX has no specific idle mode */
#define I2C_MUX_GPIO_NO_IDLE ((unsigned)-1)
/**
* struct i2c_mux_gpio_platform_data - Platform-dependent data for i2c-mux-gpio
* @parent: Parent I2C bus adapter number
* @base_nr: Base I2C bus number to number adapters from or zero for dynamic
* @values: Array of bitmasks of GPIO settings (low/high) for each
* position
* @n_values: Number of multiplexer positions (busses to instantiate)
* @idle: Bitmask to write to MUX when idle or GPIO_I2CMUX_NO_IDLE if not used
* @settle_time: Delay to wait when a new bus is selected
*/
struct i2c_mux_gpio_platform_data {
int parent;
int base_nr;
const unsigned *values;
int n_values;
unsigned idle;
u32 settle_time;
};
#endif /* _LINUX_I2C_MUX_GPIO_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-mux-reg.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* I2C multiplexer using a single register
*
* Copyright 2015 Freescale Semiconductor
* York Sun <yorksun@freescale.com>
*/
#ifndef __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
#define __LINUX_PLATFORM_DATA_I2C_MUX_REG_H
/**
* struct i2c_mux_reg_platform_data - Platform-dependent data for i2c-mux-reg
* @parent: Parent I2C bus adapter number
* @base_nr: Base I2C bus number to number adapters from or zero for dynamic
* @values: Array of value for each channel
* @n_values: Number of multiplexer channels
* @little_endian: Indicating if the register is in little endian
* @write_only: Reading the register is not allowed by hardware
* @idle: Value to write to mux when idle
* @idle_in_use: indicate if idle value is in use
* @reg: Virtual address of the register to switch channel
* @reg_size: register size in bytes
*/
struct i2c_mux_reg_platform_data {
int parent;
int base_nr;
const unsigned int *values;
int n_values;
bool little_endian;
bool write_only;
u32 idle;
bool idle_in_use;
void __iomem *reg;
resource_size_t reg_size;
};
#endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REG_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-ocores.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* i2c-ocores.h - definitions for the i2c-ocores interface
*
* Peter Korsgaard <peter@korsgaard.com>
*/
#ifndef _LINUX_I2C_OCORES_H
#define _LINUX_I2C_OCORES_H
struct ocores_i2c_platform_data {
u32 reg_shift; /* register offset shift value */
u32 reg_io_width; /* register io read/write width */
u32 clock_khz; /* input clock in kHz */
u32 bus_khz; /* bus clock in kHz */
bool big_endian; /* registers are big endian */
u8 num_devices; /* number of devices in the devices list */
struct i2c_board_info const *devices; /* devices connected to the bus */
};
#endif /* _LINUX_I2C_OCORES_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-omap.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __I2C_OMAP_H__
#define __I2C_OMAP_H__
#include <linux/platform_device.h>
/*
* Version 2 of the I2C peripheral unit has a different register
* layout and extra registers. The ID register in the V2 peripheral
* unit on the OMAP4430 reports the same ID as the V1 peripheral
* unit on the OMAP3530, so we must inform the driver which IP
* version we know it is running on from platform / cpu-specific
* code using these constants in the hwmod class definition.
*/
#define OMAP_I2C_IP_VERSION_1 1
#define OMAP_I2C_IP_VERSION_2 2
/* struct omap_i2c_bus_platform_data .flags meanings */
#define OMAP_I2C_FLAG_NO_FIFO BIT(0)
#define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
#define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
/* how the CPU address bus must be translated for I2C unit access */
#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
#define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7)
#define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8)
#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
struct omap_i2c_bus_platform_data {
u32 clkrate;
u32 rev;
u32 flags;
void (*set_mpu_wkup_lat)(struct device *dev, long set);
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-pca-platform.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef I2C_PCA9564_PLATFORM_H
#define I2C_PCA9564_PLATFORM_H
struct i2c_pca9564_pf_platform_data {
int i2c_clock_speed; /* values are defined in linux/i2c-algo-pca.h */
int timeout; /* timeout in jiffies */
};
#endif /* I2C_PCA9564_PLATFORM_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-pxa.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* i2c_pxa.h
*
* Copyright (C) 2002 Intrinsyc Software Inc.
*/
#ifndef _I2C_PXA_H_
#define _I2C_PXA_H_
struct i2c_pxa_platform_data {
unsigned int class;
unsigned int use_pio :1;
unsigned int fast_mode :1;
unsigned int high_mode:1;
unsigned char master_code;
unsigned long rate;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-s3c2410.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2004-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller platform_device info
*/
#ifndef __I2C_S3C2410_H
#define __I2C_S3C2410_H __FILE__
#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
struct platform_device;
/**
* struct s3c2410_platform_i2c - Platform data for s3c I2C.
* @bus_num: The bus number to use (if possible).
* @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
* @slave_addr: The I2C address for the slave device (if enabled).
* @frequency: The desired frequency in Hz of the bus. This is
* guaranteed to not be exceeded. If the caller does
* not care, use zero and the driver will select a
* useful default.
* @sda_delay: The delay (in ns) applied to SDA edges.
* @cfg_gpio: A callback to configure the pins for I2C operation.
*/
struct s3c2410_platform_i2c {
int bus_num;
unsigned int flags;
unsigned int slave_addr;
unsigned long frequency;
unsigned int sda_delay;
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c3_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c4_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
extern struct s3c2410_platform_i2c default_i2c_data;
#endif /* __I2C_S3C2410_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/i2c-xiic.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* i2c-xiic.h
* Copyright (c) 2009 Intel Corporation
*/
/* Supports:
* Xilinx IIC
*/
#ifndef _LINUX_I2C_XIIC_H
#define _LINUX_I2C_XIIC_H
/**
* struct xiic_i2c_platform_data - Platform data of the Xilinx I2C driver
* @num_devices: Number of devices that shall be added when the driver
* is probed.
* @devices: The actuall devices to add.
*
* This purpose of this platform data struct is to be able to provide a number
* of devices that should be added to the I2C bus. The reason is that sometimes
* the I2C board info is not enough, a new PCI board can for instance be
* plugged into a standard PC, and the bus number might be unknown at
* early init time.
*/
struct xiic_i2c_platform_data {
u8 num_devices;
struct i2c_board_info const *devices;
};
#endif /* _LINUX_I2C_XIIC_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/invensense_mpu6050.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2012 Invensense, Inc.
*/
#ifndef __INV_MPU6050_PLATFORM_H_
#define __INV_MPU6050_PLATFORM_H_
/**
* struct inv_mpu6050_platform_data - Platform data for the mpu driver
* @orientation: Orientation matrix of the chip (deprecated in favor of
* mounting matrix retrieved from device-tree)
*
* Contains platform specific information on how to configure the MPU6050 to
* work on this platform. The orientation matrices are 3x3 rotation matrices
* that are applied to the data to rotate from the mounting orientation to the
* platform orientation. The values must be one of 0, 1, or -1 and each row and
* column should have exactly 1 non-zero value.
*
* Deprecated in favor of mounting matrix retrieved from device-tree.
*/
struct inv_mpu6050_platform_data {
__s8 orientation[9];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/iommu-omap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* omap iommu: main structures
*
* Copyright (C) 2008-2009 Nokia Corporation
*
* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
*/
#include <linux/platform_device.h>
struct iommu_platform_data {
const char *reset_name;
int (*assert_reset)(struct platform_device *pdev, const char *name);
int (*deassert_reset)(struct platform_device *pdev, const char *name);
int (*device_enable)(struct platform_device *pdev);
int (*device_idle)(struct platform_device *pdev);
int (*set_pwrdm_constraint)(struct platform_device *pdev, bool request,
u8 *pwrst);
};
local/recipes/gpu/amdgpu-source/include/linux/platform_data/isl9305.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* isl9305 - Intersil ISL9305 DCDC regulator
*
* Copyright 2014 Linaro Ltd
*
* Author: Mark Brown <broonie@kernel.org>
*/
#ifndef __ISL9305_H
#define __ISL9305_H
#define ISL9305_DCD1 0
#define ISL9305_DCD2 1
#define ISL9305_LDO1 2
#define ISL9305_LDO2 3
#define ISL9305_MAX_REGULATOR ISL9305_LDO2
struct regulator_init_data;
struct isl9305_pdata {
struct regulator_init_data *init_data[ISL9305_MAX_REGULATOR + 1];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/itco_wdt.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Platform data for the Intel TCO Watchdog
*/
#ifndef _ITCO_WDT_H_
#define _ITCO_WDT_H_
/* Watchdog resources */
#define ICH_RES_IO_TCO 0
#define ICH_RES_IO_SMI 1
#define ICH_RES_MEM_OFF 2
#define ICH_RES_MEM_GCS_PMC 0
/**
* struct itco_wdt_platform_data - iTCO_wdt platform data
* @name: Name of the platform
* @version: iTCO version
* @no_reboot_use_pmc: Use PMC BXT API to set and clear NO_REBOOT bit
*/
struct itco_wdt_platform_data {
char name[32];
unsigned int version;
bool no_reboot_use_pmc;
};
#endif /* _ITCO_WDT_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/keypad-omap.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
*/
#ifndef __KEYPAD_OMAP_H
#define __KEYPAD_OMAP_H
#ifndef CONFIG_ARCH_OMAP1
#warning Please update the board to use matrix-keypad driver
#define omap_readw(reg) 0
#define omap_writew(val, reg) do {} while (0)
#endif
#include <linux/input/matrix_keypad.h>
struct omap_kp_platform_data {
int rows;
int cols;
const struct matrix_keymap_data *keymap_data;
bool rep;
unsigned long delay;
bool dbounce;
};
/* Group (0..3) -- when multiple keys are pressed, only the
* keys pressed in the same group are considered as pressed. This is
* in order to workaround certain crappy HW designs that produce ghost
* keypresses. Two free bits, not used by neither row/col nor keynum,
* must be available for use as group bits. The below GROUP_SHIFT
* macro definition is based on some prior knowledge of the
* matrix_keypad defined KEY() macro internals.
*/
#define GROUP_SHIFT 14
#define GROUP_0 (0 << GROUP_SHIFT)
#define GROUP_1 (1 << GROUP_SHIFT)
#define GROUP_2 (2 << GROUP_SHIFT)
#define GROUP_3 (3 << GROUP_SHIFT)
#define GROUP_MASK GROUP_3
#if KEY_MAX & GROUP_MASK
#error Group bits in conflict with keynum bits
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lcd-mipid.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LCD_MIPID_H
#define __LCD_MIPID_H
enum mipid_test_num {
MIPID_TEST_RGB_LINES,
};
enum mipid_test_result {
MIPID_TEST_SUCCESS,
MIPID_TEST_INVALID,
MIPID_TEST_FAILED,
};
#ifdef __KERNEL__
struct mipid_platform_data {
int data_lines;
void (*set_bklight_level)(struct mipid_platform_data *pdata,
int level);
int (*get_bklight_level)(struct mipid_platform_data *pdata);
int (*get_bklight_max)(struct mipid_platform_data *pdata);
};
#endif
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/leds-lm355x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2012 Texas Instruments
*
* Simple driver for Texas Instruments LM355x LED driver chip
*
* Author: G.Shark Jeong <gshark.jeong@gmail.com>
* Daniel Jeong <daniel.jeong@ti.com>
*/
#define LM355x_NAME "leds-lm355x"
#define LM3554_NAME "leds-lm3554"
#define LM3556_NAME "leds-lm3556"
/* lm3554 : strobe def. on */
enum lm355x_strobe {
LM355x_PIN_STROBE_DISABLE = 0x00,
LM355x_PIN_STROBE_ENABLE = 0x01,
};
enum lm355x_torch {
LM355x_PIN_TORCH_DISABLE = 0,
LM3554_PIN_TORCH_ENABLE = 0x80,
LM3556_PIN_TORCH_ENABLE = 0x10,
};
enum lm355x_tx2 {
LM355x_PIN_TX_DISABLE = 0,
LM3554_PIN_TX_ENABLE = 0x20,
LM3556_PIN_TX_ENABLE = 0x40,
};
enum lm355x_ntc {
LM355x_PIN_NTC_DISABLE = 0,
LM3554_PIN_NTC_ENABLE = 0x08,
LM3556_PIN_NTC_ENABLE = 0x80,
};
enum lm355x_pmode {
LM355x_PMODE_DISABLE = 0,
LM355x_PMODE_ENABLE = 0x04,
};
/*
* struct lm3554_platform_data
* @pin_strobe: strobe input
* @pin_torch : input pin
* lm3554-tx1/torch/gpio1
* lm3556-torch
* @pin_tx2 : input pin
* lm3554-envm/tx2/gpio2
* lm3556-tx pin
* @ntc_pin : output pin
* lm3554-ledi/ntc
* lm3556-temp pin
* @pass_mode : pass mode
*/
struct lm355x_platform_data {
enum lm355x_strobe pin_strobe;
enum lm355x_torch pin_tx1;
enum lm355x_tx2 pin_tx2;
enum lm355x_ntc ntc_pin;
enum lm355x_pmode pass_mode;
};
local/recipes/gpu/amdgpu-source/include/linux/platform_data/leds-lm3642.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2012 Texas Instruments
*
* Simple driver for Texas Instruments LM3642 LED driver chip
*
* Author: G.Shark Jeong <gshark.jeong@gmail.com>
* Daniel Jeong <daniel.jeong@ti.com>
*/
#ifndef __LINUX_LM3642_H
#define __LINUX_LM3642_H
#define LM3642_NAME "leds-lm3642"
enum lm3642_torch_pin_enable {
LM3642_TORCH_PIN_DISABLE = 0x00,
LM3642_TORCH_PIN_ENABLE = 0x10,
};
enum lm3642_strobe_pin_enable {
LM3642_STROBE_PIN_DISABLE = 0x00,
LM3642_STROBE_PIN_ENABLE = 0x20,
};
enum lm3642_tx_pin_enable {
LM3642_TX_PIN_DISABLE = 0x00,
LM3642_TX_PIN_ENABLE = 0x40,
};
struct lm3642_platform_data {
enum lm3642_torch_pin_enable torch_pin;
enum lm3642_strobe_pin_enable strobe_pin;
enum lm3642_tx_pin_enable tx_pin;
};
#endif /* __LINUX_LM3642_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/leds-lp55xx.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* LP55XX Platform Data Header
*
* Copyright (C) 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*
* Derived from leds-lp5521.h, leds-lp5523.h
*/
#ifndef _LEDS_LP55XX_H
#define _LEDS_LP55XX_H
#include <linux/gpio/consumer.h>
#include <linux/led-class-multicolor.h>
/* Clock configuration */
#define LP55XX_CLOCK_AUTO 0
#define LP55XX_CLOCK_INT 1
#define LP55XX_CLOCK_EXT 2
#define LP55XX_MAX_GROUPED_CHAN 4
struct lp55xx_led_config {
const char *name;
const char *default_trigger;
u8 chan_nr;
u8 led_current; /* mA x10, 0 if led is not connected */
u8 max_current;
int num_colors;
unsigned int max_channel;
int color_id[LED_COLOR_ID_MAX];
int output_num[LED_COLOR_ID_MAX];
};
struct lp55xx_predef_pattern {
const u8 *r;
const u8 *g;
const u8 *b;
u8 size_r;
u8 size_g;
u8 size_b;
};
enum lp8501_pwr_sel {
LP8501_ALL_VDD, /* D1~9 are connected to VDD */
LP8501_6VDD_3VOUT, /* D1~6 with VDD, D7~9 with VOUT */
LP8501_3VDD_6VOUT, /* D1~6 with VOUT, D7~9 with VDD */
LP8501_ALL_VOUT, /* D1~9 are connected to VOUT */
};
/*
* struct lp55xx_platform_data
* @led_config : Configurable led class device
* @num_channels : Number of LED channels
* @label : Used for naming LEDs
* @clock_mode : Input clock mode. LP55XX_CLOCK_AUTO or _INT or _EXT
* @setup_resources : Platform specific function before enabling the chip
* @release_resources : Platform specific function after disabling the chip
* @enable_gpiod : enable GPIO descriptor
* @patterns : Predefined pattern data for RGB channels
* @num_patterns : Number of patterns
* @update_config : Value of CONFIG register
*/
struct lp55xx_platform_data {
/* LED channel configuration */
struct lp55xx_led_config *led_config;
u8 num_channels;
const char *label;
/* Clock configuration */
u8 clock_mode;
/* Charge pump mode */
u32 charge_pump_mode;
/* optional enable GPIO */
struct gpio_desc *enable_gpiod;
/* Predefined pattern data */
struct lp55xx_predef_pattern *patterns;
unsigned int num_patterns;
/* LP8501 specific */
enum lp8501_pwr_sel pwr_sel;
};
#endif /* _LEDS_LP55XX_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lenovo-yoga-c630.h
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022-2024, Linaro Ltd
* Authors:
* Bjorn Andersson
* Dmitry Baryshkov
*/
#ifndef _LENOVO_YOGA_C630_DATA_H
#define _LENOVO_YOGA_C630_DATA_H
struct yoga_c630_ec;
struct notifier_block;
#define YOGA_C630_MOD_NAME "lenovo_yoga_c630"
#define YOGA_C630_DEV_UCSI "ucsi"
#define YOGA_C630_DEV_PSY "psy"
int yoga_c630_ec_read8(struct yoga_c630_ec *ec, u8 addr);
int yoga_c630_ec_read16(struct yoga_c630_ec *ec, u8 addr);
int yoga_c630_ec_register_notify(struct yoga_c630_ec *ec, struct notifier_block *nb);
void yoga_c630_ec_unregister_notify(struct yoga_c630_ec *ec, struct notifier_block *nb);
#define YOGA_C630_UCSI_WRITE_SIZE 8
#define YOGA_C630_UCSI_CCI_SIZE 4
#define YOGA_C630_UCSI_DATA_SIZE 16
#define YOGA_C630_UCSI_READ_SIZE (YOGA_C630_UCSI_CCI_SIZE + YOGA_C630_UCSI_DATA_SIZE)
u16 yoga_c630_ec_ucsi_get_version(struct yoga_c630_ec *ec);
int yoga_c630_ec_ucsi_write(struct yoga_c630_ec *ec,
const u8 req[YOGA_C630_UCSI_WRITE_SIZE]);
int yoga_c630_ec_ucsi_read(struct yoga_c630_ec *ec,
u8 resp[YOGA_C630_UCSI_READ_SIZE]);
#define LENOVO_EC_EVENT_USB 0x20
#define LENOVO_EC_EVENT_UCSI 0x21
#define LENOVO_EC_EVENT_HPD 0x22
#define LENOVO_EC_EVENT_BAT_STATUS 0x24
#define LENOVO_EC_EVENT_BAT_INFO 0x25
#define LENOVO_EC_EVENT_BAT_ADPT_STATUS 0x37
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lm3630a_bl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Simple driver for Texas Instruments LM3630A LED Flash driver chip
* Copyright (C) 2012 Texas Instruments
*/
#ifndef __LINUX_LM3630A_H
#define __LINUX_LM3630A_H
#define LM3630A_NAME "lm3630a_bl"
enum lm3630a_pwm_ctrl {
LM3630A_PWM_DISABLE = 0x00,
LM3630A_PWM_BANK_A,
LM3630A_PWM_BANK_B,
LM3630A_PWM_BANK_ALL,
LM3630A_PWM_BANK_A_ACT_LOW = 0x05,
LM3630A_PWM_BANK_B_ACT_LOW,
LM3630A_PWM_BANK_ALL_ACT_LOW,
};
enum lm3630a_leda_ctrl {
LM3630A_LEDA_DISABLE = 0x00,
LM3630A_LEDA_ENABLE = 0x04,
LM3630A_LEDA_ENABLE_LINEAR = 0x14,
};
enum lm3630a_ledb_ctrl {
LM3630A_LEDB_DISABLE = 0x00,
LM3630A_LEDB_ON_A = 0x01,
LM3630A_LEDB_ENABLE = 0x02,
LM3630A_LEDB_ENABLE_LINEAR = 0x0A,
};
#define LM3630A_MAX_BRIGHTNESS 255
/*
*@leda_label : optional led a label.
*@leda_init_brt : led a init brightness. 4~255
*@leda_max_brt : led a max brightness. 4~255
*@leda_ctrl : led a disable, enable linear, enable exponential
*@ledb_label : optional led b label.
*@ledb_init_brt : led b init brightness. 4~255
*@ledb_max_brt : led b max brightness. 4~255
*@ledb_ctrl : led b disable, enable linear, enable exponential
*@pwm_period : pwm period
*@pwm_ctrl : pwm disable, bank a or b, active high or low
*/
struct lm3630a_platform_data {
/* led a config. */
const char *leda_label;
int leda_init_brt;
int leda_max_brt;
enum lm3630a_leda_ctrl leda_ctrl;
/* led b config. */
const char *ledb_label;
int ledb_init_brt;
int ledb_max_brt;
enum lm3630a_ledb_ctrl ledb_ctrl;
/* pwm config. */
unsigned int pwm_period;
enum lm3630a_pwm_ctrl pwm_ctrl;
};
#endif /* __LINUX_LM3630A_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lm3639_bl.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Simple driver for Texas Instruments LM3630 LED Flash driver chip
* Copyright (C) 2012 Texas Instruments
*/
#ifndef __LINUX_LM3639_H
#define __LINUX_LM3639_H
#define LM3639_NAME "lm3639_bl"
enum lm3639_pwm {
LM3639_PWM_DISABLE = 0x00,
LM3639_PWM_EN_ACTLOW = 0x48,
LM3639_PWM_EN_ACTHIGH = 0x40,
};
enum lm3639_strobe {
LM3639_STROBE_DISABLE = 0x00,
LM3639_STROBE_EN_ACTLOW = 0x10,
LM3639_STROBE_EN_ACTHIGH = 0x30,
};
enum lm3639_txpin {
LM3639_TXPIN_DISABLE = 0x00,
LM3639_TXPIN_EN_ACTLOW = 0x04,
LM3639_TXPIN_EN_ACTHIGH = 0x0C,
};
enum lm3639_fleds {
LM3639_FLED_DIASBLE_ALL = 0x00,
LM3639_FLED_EN_1 = 0x40,
LM3639_FLED_EN_2 = 0x20,
LM3639_FLED_EN_ALL = 0x60,
};
enum lm3639_bleds {
LM3639_BLED_DIASBLE_ALL = 0x00,
LM3639_BLED_EN_1 = 0x10,
LM3639_BLED_EN_2 = 0x08,
LM3639_BLED_EN_ALL = 0x18,
};
enum lm3639_bled_mode {
LM3639_BLED_MODE_EXPONETIAL = 0x00,
LM3639_BLED_MODE_LINEAR = 0x10,
};
struct lm3639_platform_data {
unsigned int max_brt_led;
unsigned int init_brt_led;
/* input pins */
enum lm3639_pwm pin_pwm;
enum lm3639_strobe pin_strobe;
enum lm3639_txpin pin_tx;
/* output pins */
enum lm3639_fleds fled_pins;
enum lm3639_bleds bled_pins;
enum lm3639_bled_mode bled_mode;
void (*pwm_set_intensity) (int brightness, int max_brightness);
int (*pwm_get_intensity) (void);
};
#endif /* __LINUX_LM3639_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lm8323.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* lm8323.h - Configuration for LM8323 keypad driver.
*/
#ifndef __LINUX_LM8323_H
#define __LINUX_LM8323_H
#include <linux/types.h>
/*
* Largest keycode that the chip can send, plus one,
* so keys can be mapped directly at the index of the
* LM8323 keycode instead of subtracting one.
*/
#define LM8323_KEYMAP_SIZE (0x7f + 1)
#define LM8323_NUM_PWMS 3
struct lm8323_platform_data {
int debounce_time; /* Time to watch for key bouncing, in ms. */
int active_time; /* Idle time until sleep, in ms. */
int size_x;
int size_y;
bool repeat;
const unsigned short *keymap;
const char *pwm_names[LM8323_NUM_PWMS];
const char *name; /* Device name. */
};
#endif /* __LINUX_LM8323_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lp855x.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* LP855x Backlight Driver
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _LP855X_H
#define _LP855X_H
#define BL_CTL_SHFT (0)
#define BRT_MODE_SHFT (1)
#define BRT_MODE_MASK (0x06)
/* Enable backlight. Only valid when BRT_MODE=10(I2C only) */
#define ENABLE_BL (1)
#define DISABLE_BL (0)
#define I2C_CONFIG(id) id ## _I2C_CONFIG
#define PWM_CONFIG(id) id ## _PWM_CONFIG
/* DEVICE CONTROL register - LP8550 */
#define LP8550_PWM_CONFIG (LP8550_PWM_ONLY << BRT_MODE_SHFT)
#define LP8550_I2C_CONFIG ((ENABLE_BL << BL_CTL_SHFT) | \
(LP8550_I2C_ONLY << BRT_MODE_SHFT))
/* DEVICE CONTROL register - LP8551 */
#define LP8551_PWM_CONFIG LP8550_PWM_CONFIG
#define LP8551_I2C_CONFIG LP8550_I2C_CONFIG
/* DEVICE CONTROL register - LP8552 */
#define LP8552_PWM_CONFIG LP8550_PWM_CONFIG
#define LP8552_I2C_CONFIG LP8550_I2C_CONFIG
/* DEVICE CONTROL register - LP8553 */
#define LP8553_PWM_CONFIG LP8550_PWM_CONFIG
#define LP8553_I2C_CONFIG LP8550_I2C_CONFIG
/* CONFIG register - LP8555 */
#define LP8555_PWM_STANDBY BIT(7)
#define LP8555_PWM_FILTER BIT(6)
#define LP8555_RELOAD_EPROM BIT(3) /* use it if EPROMs should be reset
when the backlight turns on */
#define LP8555_OFF_OPENLEDS BIT(2)
#define LP8555_PWM_CONFIG LP8555_PWM_ONLY
#define LP8555_I2C_CONFIG LP8555_I2C_ONLY
#define LP8555_COMB1_CONFIG LP8555_COMBINED1
#define LP8555_COMB2_CONFIG LP8555_COMBINED2
/* DEVICE CONTROL register - LP8556 */
#define LP8556_PWM_CONFIG (LP8556_PWM_ONLY << BRT_MODE_SHFT)
#define LP8556_COMB1_CONFIG (LP8556_COMBINED1 << BRT_MODE_SHFT)
#define LP8556_I2C_CONFIG ((ENABLE_BL << BL_CTL_SHFT) | \
(LP8556_I2C_ONLY << BRT_MODE_SHFT))
#define LP8556_COMB2_CONFIG (LP8556_COMBINED2 << BRT_MODE_SHFT)
#define LP8556_FAST_CONFIG BIT(7) /* use it if EPROMs should be maintained
when exiting the low power mode */
/* CONFIG register - LP8557 */
#define LP8557_PWM_STANDBY BIT(7)
#define LP8557_PWM_FILTER BIT(6)
#define LP8557_RELOAD_EPROM BIT(3) /* use it if EPROMs should be reset
when the backlight turns on */
#define LP8557_OFF_OPENLEDS BIT(2)
#define LP8557_PWM_CONFIG LP8557_PWM_ONLY
#define LP8557_I2C_CONFIG LP8557_I2C_ONLY
#define LP8557_COMB1_CONFIG LP8557_COMBINED1
#define LP8557_COMB2_CONFIG LP8557_COMBINED2
enum lp855x_chip_id {
LP8550,
LP8551,
LP8552,
LP8553,
LP8555,
LP8556,
LP8557,
};
enum lp8550_brighntess_source {
LP8550_PWM_ONLY,
LP8550_I2C_ONLY = 2,
};
enum lp8551_brighntess_source {
LP8551_PWM_ONLY = LP8550_PWM_ONLY,
LP8551_I2C_ONLY = LP8550_I2C_ONLY,
};
enum lp8552_brighntess_source {
LP8552_PWM_ONLY = LP8550_PWM_ONLY,
LP8552_I2C_ONLY = LP8550_I2C_ONLY,
};
enum lp8553_brighntess_source {
LP8553_PWM_ONLY = LP8550_PWM_ONLY,
LP8553_I2C_ONLY = LP8550_I2C_ONLY,
};
enum lp8555_brightness_source {
LP8555_PWM_ONLY,
LP8555_I2C_ONLY,
LP8555_COMBINED1, /* Brightness register with shaped PWM */
LP8555_COMBINED2, /* PWM with shaped brightness register */
};
enum lp8556_brightness_source {
LP8556_PWM_ONLY,
LP8556_COMBINED1, /* pwm + i2c before the shaper block */
LP8556_I2C_ONLY,
LP8556_COMBINED2, /* pwm + i2c after the shaper block */
};
enum lp8557_brightness_source {
LP8557_PWM_ONLY,
LP8557_I2C_ONLY,
LP8557_COMBINED1, /* pwm + i2c after the shaper block */
LP8557_COMBINED2, /* pwm + i2c before the shaper block */
};
struct lp855x_rom_data {
u8 addr;
u8 val;
};
/**
* struct lp855x_platform_data - lp855 platform-specific data
* @name : Backlight driver name. If it is not defined, default name is set.
* @device_control : value of DEVICE CONTROL register
* @initial_brightness : initial value of backlight brightness
* @period_ns : platform specific pwm period value. unit is nano.
* Only valid when mode is PWM_BASED.
* @size_program : total size of lp855x_rom_data
* @rom_data : list of new eeprom/eprom registers
*/
struct lp855x_platform_data {
const char *name;
u8 device_control;
u8 initial_brightness;
unsigned int period_ns;
int size_program;
struct lp855x_rom_data *rom_data;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lp8727.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* LP8727 Micro/Mini USB IC with integrated charger
*
* Copyright (C) 2011 Texas Instruments
* Copyright (C) 2011 National Semiconductor
*/
#ifndef _LP8727_H
#define _LP8727_H
enum lp8727_eoc_level {
LP8727_EOC_5P,
LP8727_EOC_10P,
LP8727_EOC_16P,
LP8727_EOC_20P,
LP8727_EOC_25P,
LP8727_EOC_33P,
LP8727_EOC_50P,
};
enum lp8727_ichg {
LP8727_ICHG_90mA,
LP8727_ICHG_100mA,
LP8727_ICHG_400mA,
LP8727_ICHG_450mA,
LP8727_ICHG_500mA,
LP8727_ICHG_600mA,
LP8727_ICHG_700mA,
LP8727_ICHG_800mA,
LP8727_ICHG_900mA,
LP8727_ICHG_1000mA,
};
/**
* struct lp8727_chg_param
* @eoc_level : end of charge level setting
* @ichg : charging current
*/
struct lp8727_chg_param {
enum lp8727_eoc_level eoc_level;
enum lp8727_ichg ichg;
};
/**
* struct lp8727_platform_data
* @get_batt_present : check battery status - exists or not
* @get_batt_level : get battery voltage (mV)
* @get_batt_capacity : get battery capacity (%)
* @get_batt_temp : get battery temperature
* @ac : charging parameters for AC type charger
* @usb : charging parameters for USB type charger
* @debounce_msec : interrupt debounce time
*/
struct lp8727_platform_data {
u8 (*get_batt_present)(void);
u16 (*get_batt_level)(void);
u8 (*get_batt_capacity)(void);
u8 (*get_batt_temp)(void);
struct lp8727_chg_param *ac;
struct lp8727_chg_param *usb;
unsigned int debounce_msec;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lp8755.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* LP8755 High Performance Power Management Unit Driver:System Interface Driver
*
* Copyright (C) 2012 Texas Instruments
*
* Author: Daniel(Geon Si) Jeong <daniel.jeong@ti.com>
* G.Shark Jeong <gshark.jeong@gmail.com>
*/
#ifndef _LP8755_H
#define _LP8755_H
#include <linux/regulator/consumer.h>
#define LP8755_NAME "lp8755-regulator"
/*
*PWR FAULT : power fault detected
*OCP : over current protect activated
*OVP : over voltage protect activated
*TEMP_WARN : thermal warning
*TEMP_SHDN : thermal shutdonw detected
*I_LOAD : current measured
*/
#define LP8755_EVENT_PWR_FAULT REGULATOR_EVENT_FAIL
#define LP8755_EVENT_OCP REGULATOR_EVENT_OVER_CURRENT
#define LP8755_EVENT_OVP 0x10000
#define LP8755_EVENT_TEMP_WARN 0x2000
#define LP8755_EVENT_TEMP_SHDN REGULATOR_EVENT_OVER_TEMP
#define LP8755_EVENT_I_LOAD 0x40000
enum lp8755_bucks {
LP8755_BUCK0 = 0,
LP8755_BUCK1,
LP8755_BUCK2,
LP8755_BUCK3,
LP8755_BUCK4,
LP8755_BUCK5,
LP8755_BUCK_MAX,
};
/**
* multiphase configuration options
*/
enum lp8755_mphase_config {
MPHASE_CONF0,
MPHASE_CONF1,
MPHASE_CONF2,
MPHASE_CONF3,
MPHASE_CONF4,
MPHASE_CONF5,
MPHASE_CONF6,
MPHASE_CONF7,
MPHASE_CONF8,
MPHASE_CONF_MAX
};
/**
* struct lp8755_platform_data
* @mphase_type : Multiphase Switcher Configurations.
* @buck_data : buck0~6 init voltage in uV
*/
struct lp8755_platform_data {
int mphase;
struct regulator_init_data *buck_data[LP8755_BUCK_MAX];
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/ltc4245.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Platform Data for LTC4245 hardware monitor chip
*
* Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
*/
#ifndef LINUX_LTC4245_H
#define LINUX_LTC4245_H
#include <linux/types.h>
struct ltc4245_platform_data {
bool use_extra_gpios;
};
#endif /* LINUX_LTC4245_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/lv5207lp.h
+16
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* lv5207lp.h - Sanyo LV5207LP LEDs Driver
*/
#ifndef __LV5207LP_H__
#define __LV5207LP_H__
struct device;
struct lv5207lp_platform_data {
struct device *dev;
unsigned int max_value;
unsigned int def_value;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/max197.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Maxim MAX197 A/D Converter Driver
*
* Copyright (c) 2012 Savoir-faire Linux Inc.
* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
*
* For further information, see the Documentation/hwmon/max197.rst file.
*/
#ifndef _PDATA_MAX197_H
#define _PDATA_MAX197_H
/**
* struct max197_platform_data - MAX197 connectivity info
* @convert: Function used to start a conversion with control byte ctrl.
* It must return the raw data, or a negative error code.
*/
struct max197_platform_data {
int (*convert)(u8 ctrl);
};
#endif /* _PDATA_MAX197_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/max3421-hcd.h
+25
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 eGauge Systems LLC
* Contributed by David Mosberger-Tang <davidm@egauge.net>
*
* Platform-data structure for MAX3421 USB HCD driver.
*
*/
#ifndef MAX3421_HCD_PLAT_H_INCLUDED
#define MAX3421_HCD_PLAT_H_INCLUDED
/*
* This structure defines the mapping of certain auxiliary functions to the
* MAX3421E GPIO pins. The chip has eight GP inputs and eight GP outputs.
* A value of 0 indicates that the pin is not used/wired to anything.
*
* At this point, the only control the max3421-hcd driver cares about is
* to control Vbus (5V to the peripheral).
*/
struct max3421_hcd_platform_data {
u8 vbus_gpout; /* pin controlling Vbus */
u8 vbus_active_level; /* level that turns on power */
};
#endif /* MAX3421_HCD_PLAT_H_INCLUDED */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/max732x.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_I2C_MAX732X_H
#define __LINUX_I2C_MAX732X_H
/* platform data for the MAX732x 8/16-bit I/O expander driver */
struct max732x_platform_data {
/* number of the first GPIO */
unsigned gpio_base;
};
#endif /* __LINUX_I2C_MAX732X_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/mdio-bcm-unimac.h
+16
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#ifndef __MDIO_BCM_UNIMAC_PDATA_H
#define __MDIO_BCM_UNIMAC_PDATA_H
struct clk;
struct unimac_mdio_pdata {
u32 phy_mask;
int (*wait_func)(void *data);
void *wait_func_data;
const char *bus_name;
struct clk *clk;
};
#define UNIMAC_MDIO_DRV_NAME "unimac-mdio"
#endif /* __MDIO_BCM_UNIMAC_PDATA_H */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/media/camera-pxa.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
camera.h - PXA camera driver header file
Copyright (C) 2003, Intel Corporation
Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
*/
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#define PXA_CAMERA_MASTER 1
#define PXA_CAMERA_DATAWIDTH_4 2
#define PXA_CAMERA_DATAWIDTH_5 4
#define PXA_CAMERA_DATAWIDTH_8 8
#define PXA_CAMERA_DATAWIDTH_9 0x10
#define PXA_CAMERA_DATAWIDTH_10 0x20
#define PXA_CAMERA_PCLK_EN 0x40
#define PXA_CAMERA_MCLK_EN 0x80
#define PXA_CAMERA_PCP 0x100
#define PXA_CAMERA_HSP 0x200
#define PXA_CAMERA_VSP 0x400
struct pxacamera_platform_data {
unsigned long flags;
unsigned long mclk_10khz;
int sensor_i2c_adapter_id;
int sensor_i2c_address;
};
extern void pxa_set_camera_info(struct pxacamera_platform_data *);
#endif /* __ASM_ARCH_CAMERA_H_ */
local/recipes/gpu/amdgpu-source/include/linux/platform_data/media/mmp-camera.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Information for the Marvell Armada MMP camera
*/
#include <media/v4l2-mediabus.h>
enum dphy3_algo {
DPHY3_ALGO_DEFAULT = 0,
DPHY3_ALGO_PXA910,
DPHY3_ALGO_PXA2128
};
struct mmp_camera_platform_data {
enum v4l2_mbus_type bus_type;
int mclk_src; /* which clock source the MCLK derives from */
int mclk_div; /* Clock Divider Value for MCLK */
/*
* MIPI support
*/
int dphy[3]; /* DPHY: CSI2_DPHY3, CSI2_DPHY5, CSI2_DPHY6 */
enum dphy3_algo dphy3_algo; /* algos for calculate CSI2_DPHY3 */
int lane; /* ccic used lane number; 0 means DVP mode */
int lane_clk;
};
local/recipes/gpu/amdgpu-source/include/linux/platform_data/media/si4713.h
+48
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/*
* include/linux/platform_data/media/si4713.h
*
* Board related data definitions for Si4713 i2c device driver.
*
* Copyright (c) 2009 Nokia Corporation
* Contact: Eduardo Valentin <eduardo.valentin@nokia.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
#ifndef SI4713_H
#define SI4713_H
/* The SI4713 I2C sensor chip has a fixed slave address of 0xc6 or 0x22. */
#define SI4713_I2C_ADDR_BUSEN_HIGH 0x63
#define SI4713_I2C_ADDR_BUSEN_LOW 0x11
/*
* Platform dependent definition
*/
struct si4713_platform_data {
bool is_platform_device;
};
/*
* Structure to query for Received Noise Level (RNL).
*/
struct si4713_rnl {
__u32 index; /* modulator index */
__u32 frequency; /* frequency to perform rnl measurement */
__s32 rnl; /* result of measurement in dBuV */
__u32 reserved[4]; /* drivers and apps must init this to 0 */
};
/*
* This is the ioctl number to query for rnl. Users must pass a
* struct si4713_rnl pointer specifying desired frequency in 'frequency' field
* following driver capabilities (i.e V4L2_TUNER_CAP_LOW).
* Driver must return measured value in the same structure, filling 'rnl' field.
*/
#define SI4713_IOC_MEASURE_RNL _IOWR('V', BASE_VIDIOC_PRIVATE + 0, \
struct si4713_rnl)
#endif /* ifndef SI4713_H*/
local/recipes/gpu/amdgpu-source/include/linux/platform_data/media/timb_radio.h
+18
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* timb_radio.h Platform struct for the Timberdale radio driver
* Copyright (c) 2009 Intel Corporation
*/
#ifndef _TIMB_RADIO_
#define _TIMB_RADIO_ 1
#include <linux/i2c.h>
struct timb_radio_platform_data {
int i2c_adapter; /* I2C adapter where the tuner and dsp are attached */
struct i2c_board_info *tuner;
struct i2c_board_info *dsp;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/media/timb_video.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* timb_video.h Platform struct for the Timberdale video driver
* Copyright (c) 2009-2010 Intel Corporation
*/
#ifndef _TIMB_VIDEO_
#define _TIMB_VIDEO_ 1
#include <linux/i2c.h>
struct timb_video_platform_data {
int dma_channel;
int i2c_adapter; /* The I2C adapter where the encoder is attached */
struct {
const char *module_name;
struct i2c_board_info *info;
} encoder;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/mfd-mcp-sa11x0.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2005 Russell King.
*/
#ifndef __MFD_MCP_SA11X0_H
#define __MFD_MCP_SA11X0_H
#include <linux/types.h>
struct mcp_plat_data {
u32 mccr0;
u32 mccr1;
unsigned int sclk_rate;
void *codec_pdata;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/microchip-ksz.h
+55
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/*
* Microchip KSZ series switch platform data
*
* Copyright (C) 2017
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __MICROCHIP_KSZ_H
#define __MICROCHIP_KSZ_H
#include <linux/types.h>
#include <linux/platform_data/dsa.h>
enum ksz_chip_id {
KSZ8463_CHIP_ID = 0x8463,
KSZ8563_CHIP_ID = 0x8563,
KSZ8795_CHIP_ID = 0x8795,
KSZ8794_CHIP_ID = 0x8794,
KSZ8765_CHIP_ID = 0x8765,
KSZ88X3_CHIP_ID = 0x8830,
KSZ8864_CHIP_ID = 0x8864,
KSZ8895_CHIP_ID = 0x8895,
KSZ9477_CHIP_ID = 0x00947700,
KSZ9896_CHIP_ID = 0x00989600,
KSZ9897_CHIP_ID = 0x00989700,
KSZ9893_CHIP_ID = 0x00989300,
KSZ9563_CHIP_ID = 0x00956300,
KSZ8567_CHIP_ID = 0x00856700,
KSZ9567_CHIP_ID = 0x00956700,
LAN9370_CHIP_ID = 0x00937000,
LAN9371_CHIP_ID = 0x00937100,
LAN9372_CHIP_ID = 0x00937200,
LAN9373_CHIP_ID = 0x00937300,
LAN9374_CHIP_ID = 0x00937400,
LAN9646_CHIP_ID = 0x00964600,
};
struct ksz_platform_data {
/* Must be first such that dsa_register_switch() can access it */
struct dsa_chip_data cd;
u32 chip_id;
};
#endif
local/recipes/gpu/amdgpu-source/include/linux/platform_data/mipi-i3c-hci.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef INCLUDE_PLATFORM_DATA_MIPI_I3C_HCI_H
#define INCLUDE_PLATFORM_DATA_MIPI_I3C_HCI_H
#include <linux/compiler_types.h>
/**
* struct mipi_i3c_hci_platform_data - Platform-dependent data for mipi_i3c_hci
* @base_regs: Register set base address (to support multi-bus instances)
*/
struct mipi_i3c_hci_platform_data {
void __iomem *base_regs;
};
#endif

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