Merge remote-tracking branch 'origin/aarch64-rebase' into riscv64
This commit is contained in:
Jeremy Soller
@@ -0,0 +1,500 @@
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use core::mem;
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use core::sync::atomic::{AtomicBool, Ordering};
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use crate::device::cpu::registers::{control_regs, tlb};
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use crate::syscall::FloatRegisters;
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/// This must be used by the kernel to ensure that context switches are done atomically
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/// Compare and exchange this to true when beginning a context switch on any CPU
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/// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch
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/// This must be done, as no locks can be held on the stack during switch
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pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
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#[derive(Clone, Debug)]
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pub struct Context {
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elr_el1: usize,
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sp_el0: usize,
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ttbr0_el1: usize, /* Pointer to U4 translation table for this Context */
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ttbr1_el1: usize, /* Pointer to P4 translation table for this Context */
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tpidr_el0: usize, /* Pointer to TLS region for this Context */
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tpidrro_el0: usize, /* Pointer to TLS (read-only) region for this Context */
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spsr_el1: usize,
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esr_el1: usize,
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fx_loadable: bool,
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fx_address: usize,
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sp: usize, /* Stack Pointer (x31) */
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lr: usize, /* Link Register (x30) */
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fp: usize, /* Frame pointer Register (x29) */
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x28: usize, /* Callee saved Register */
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x27: usize, /* Callee saved Register */
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x26: usize, /* Callee saved Register */
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x25: usize, /* Callee saved Register */
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x24: usize, /* Callee saved Register */
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x23: usize, /* Callee saved Register */
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x22: usize, /* Callee saved Register */
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x21: usize, /* Callee saved Register */
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x20: usize, /* Callee saved Register */
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x19: usize, /* Callee saved Register */
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x18: usize,
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x17: usize,
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x16: usize,
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x15: usize, /* Temporary Register */
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x14: usize, /* Temporary Register */
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x13: usize, /* Temporary Register */
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x12: usize, /* Temporary Register */
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x11: usize, /* Temporary Register */
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x10: usize, /* Temporary Register */
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x9: usize, /* Temporary Register */
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x8: usize, /* Indirect location Register */
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}
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impl Context {
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pub fn new() -> Context {
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Context {
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elr_el1: 0,
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sp_el0: 0,
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ttbr0_el1: 0,
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ttbr1_el1: 0,
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tpidr_el0: 0,
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tpidrro_el0: 0,
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spsr_el1: 0,
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esr_el1: 0,
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fx_loadable: false,
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fx_address: 0,
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sp: 0,
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lr: 0,
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fp: 0,
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x28: 0,
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x27: 0,
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x26: 0,
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x25: 0,
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x24: 0,
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x23: 0,
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x22: 0,
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x21: 0,
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x20: 0,
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x19: 0,
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x18: 0,
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x17: 0,
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x16: 0,
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x15: 0,
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x14: 0,
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x13: 0,
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x12: 0,
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x11: 0,
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x10: 0,
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x9: 0,
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x8: 0,
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}
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}
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pub fn get_page_utable(&self) -> usize {
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self.ttbr0_el1
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}
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pub fn get_page_ktable(&self) -> usize {
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self.ttbr1_el1
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}
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pub fn set_page_utable(&mut self, address: usize) {
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self.ttbr0_el1 = address;
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}
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pub fn set_page_ktable(&mut self, address: usize) {
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self.ttbr1_el1 = address;
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}
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pub fn set_stack(&mut self, address: usize) {
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self.sp = address;
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}
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pub fn set_lr(&mut self, address: usize) {
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self.lr = address;
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}
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pub fn set_tcb(&mut self, pid: usize) {
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self.tpidr_el0 = (crate::USER_TCB_OFFSET + pid * crate::PAGE_SIZE);
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}
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pub fn set_fp(&mut self, address: usize) {
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self.fp = address;
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}
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pub fn set_context_handle(&mut self) {
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let address = self as *const _ as usize;
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self.tpidrro_el0 = address;
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}
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pub fn get_context_handle(&mut self) -> usize {
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self.tpidrro_el0
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}
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pub unsafe fn signal_stack(&mut self, handler: extern fn(usize), sig: u8) {
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self.push_stack(sig as usize);
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self.push_stack(handler as usize);
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let lr = self.lr.clone();
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self.push_stack(lr);
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self.set_lr(signal_handler_wrapper as usize);
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}
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pub unsafe fn push_stack(&mut self, value: usize) {
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self.sp -= 1 * mem::size_of::<usize>();
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*(self.sp as *mut usize) = value;
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}
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pub unsafe fn pop_stack(&mut self) -> usize {
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let value = *(self.sp as *const usize);
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self.sp += 1 * mem::size_of::<usize>();
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value
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}
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pub fn get_fx_regs(&self) -> Option<FloatRegisters> {
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if !self.fx_loadable {
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return None;
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}
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let mut regs = unsafe { *(self.fx_address as *const FloatRegisters) };
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let mut new_st = regs.fp_simd_regs;
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regs.fp_simd_regs = new_st;
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Some(regs)
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}
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pub fn set_fx_regs(&mut self, mut new: FloatRegisters) -> bool {
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if !self.fx_loadable {
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return false;
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}
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{
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let old = unsafe { &*(self.fx_address as *const FloatRegisters) };
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let old_st = new.fp_simd_regs;
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let mut new_st = new.fp_simd_regs;
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for (new_st, old_st) in new_st.iter_mut().zip(&old_st) {
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*new_st = *old_st;
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}
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new.fp_simd_regs = new_st;
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// Make sure we don't use `old` from now on
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}
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unsafe {
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*(self.fx_address as *mut FloatRegisters) = new;
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}
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true
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}
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pub fn set_fx(&mut self, address: usize) {
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self.fx_address = address;
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}
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pub fn dump(&self) {
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println!("elr_el1: 0x{:016x}", self.elr_el1);
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println!("sp_el0: 0x{:016x}", self.sp_el0);
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println!("ttbr0_el1: 0x{:016x}", self.ttbr0_el1);
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println!("ttbr1_el1: 0x{:016x}", self.ttbr1_el1);
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println!("tpidr_el0: 0x{:016x}", self.tpidr_el0);
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println!("tpidrro_el0: 0x{:016x}", self.tpidrro_el0);
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println!("spsr_el1: 0x{:016x}", self.spsr_el1);
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println!("esr_el1: 0x{:016x}", self.esr_el1);
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println!("sp: 0x{:016x}", self.sp);
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println!("lr: 0x{:016x}", self.lr);
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println!("fp: 0x{:016x}", self.fp);
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println!("x28: 0x{:016x}", self.x28);
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println!("x27: 0x{:016x}", self.x27);
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println!("x26: 0x{:016x}", self.x26);
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println!("x25: 0x{:016x}", self.x25);
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println!("x24: 0x{:016x}", self.x24);
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println!("x23: 0x{:016x}", self.x23);
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println!("x22: 0x{:016x}", self.x22);
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println!("x21: 0x{:016x}", self.x21);
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println!("x20: 0x{:016x}", self.x20);
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println!("x19: 0x{:016x}", self.x19);
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println!("x18: 0x{:016x}", self.x18);
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println!("x17: 0x{:016x}", self.x17);
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println!("x16: 0x{:016x}", self.x16);
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println!("x15: 0x{:016x}", self.x15);
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println!("x14: 0x{:016x}", self.x14);
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println!("x13: 0x{:016x}", self.x13);
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println!("x12: 0x{:016x}", self.x12);
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println!("x11: 0x{:016x}", self.x11);
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println!("x10: 0x{:016x}", self.x10);
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println!("x9: 0x{:016x}", self.x9);
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println!("x8: 0x{:016x}", self.x8);
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}
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#[cold]
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#[inline(never)]
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#[naked]
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pub unsafe fn switch_to(&mut self, next: &mut Context) {
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let mut float_regs = &mut *(self.fx_address as *mut FloatRegisters);
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asm!(
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"stp q0, q1, [{0}, #16 * 0]",
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"stp q2, q3, [{0}, #16 * 2]",
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"stp q4, q5, [{0}, #16 * 4]",
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"stp q6, q7, [{0}, #16 * 6]",
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"stp q8, q9, [{0}, #16 * 8]",
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"stp q10, q11, [{0}, #16 * 10]",
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"stp q12, q13, [{0}, #16 * 12]",
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"stp q14, q15, [{0}, #16 * 14]",
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"stp q16, q17, [{0}, #16 * 16]",
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"stp q18, q19, [{0}, #16 * 18]",
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"stp q20, q21, [{0}, #16 * 20]",
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"stp q22, q23, [{0}, #16 * 22]",
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"stp q24, q25, [{0}, #16 * 24]",
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"stp q26, q27, [{0}, #16 * 26]",
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"stp q28, q29, [{0}, #16 * 28]",
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"stp q30, q31, [{0}, #16 * 30]",
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"mrs {1}, fpcr",
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"mrs {2}, fpsr",
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in(reg) &mut float_regs.fp_simd_regs,
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out(reg) float_regs.fpcr,
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out(reg) float_regs.fpsr
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);
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self.fx_loadable = true;
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if next.fx_loadable {
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let mut float_regs = &mut *(next.fx_address as *mut FloatRegisters);
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asm!(
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"ldp q0, q1, [{0}, #16 * 0]",
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"ldp q2, q3, [{0}, #16 * 2]",
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"ldp q4, q5, [{0}, #16 * 4]",
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"ldp q6, q7, [{0}, #16 * 6]",
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"ldp q8, q9, [{0}, #16 * 8]",
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"ldp q10, q11, [{0}, #16 * 10]",
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"ldp q12, q13, [{0}, #16 * 12]",
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"ldp q14, q15, [{0}, #16 * 14]",
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"ldp q16, q17, [{0}, #16 * 16]",
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"ldp q18, q19, [{0}, #16 * 18]",
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"ldp q20, q21, [{0}, #16 * 20]",
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"ldp q22, q23, [{0}, #16 * 22]",
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"ldp q24, q25, [{0}, #16 * 24]",
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"ldp q26, q27, [{0}, #16 * 26]",
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"ldp q28, q29, [{0}, #16 * 28]",
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"ldp q30, q31, [{0}, #16 * 30]",
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"msr fpcr, {1}",
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"msr fpsr, {2}",
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in(reg) &mut float_regs.fp_simd_regs,
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in(reg) float_regs.fpcr,
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in(reg) float_regs.fpsr
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);
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}
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self.ttbr0_el1 = control_regs::ttbr0_el1() as usize;
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if next.ttbr0_el1 != self.ttbr0_el1 {
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control_regs::ttbr0_el1_write(next.ttbr0_el1 as u64);
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tlb::flush_all();
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}
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llvm_asm!("mov $0, x8" : "=r"(self.x8) : : "memory" : "volatile");
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llvm_asm!("mov x8, $0" : : "r"(next.x8) :"memory" : "volatile");
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llvm_asm!("mov $0, x9" : "=r"(self.x9) : : "memory" : "volatile");
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llvm_asm!("mov x9, $0" : : "r"(next.x9) :"memory" : "volatile");
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llvm_asm!("mov $0, x10" : "=r"(self.x10) : : "memory" : "volatile");
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llvm_asm!("mov x10, $0" : : "r"(next.x10) :"memory" : "volatile");
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llvm_asm!("mov $0, x11" : "=r"(self.x11) : : "memory" : "volatile");
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llvm_asm!("mov x11, $0" : : "r"(next.x11) :"memory" : "volatile");
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llvm_asm!("mov $0, x12" : "=r"(self.x12) : : "memory" : "volatile");
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llvm_asm!("mov x12, $0" : : "r"(next.x12) :"memory" : "volatile");
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llvm_asm!("mov $0, x13" : "=r"(self.x13) : : "memory" : "volatile");
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llvm_asm!("mov x13, $0" : : "r"(next.x13) :"memory" : "volatile");
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llvm_asm!("mov $0, x14" : "=r"(self.x14) : : "memory" : "volatile");
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llvm_asm!("mov x14, $0" : : "r"(next.x14) :"memory" : "volatile");
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llvm_asm!("mov $0, x15" : "=r"(self.x15) : : "memory" : "volatile");
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llvm_asm!("mov x15, $0" : : "r"(next.x15) :"memory" : "volatile");
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llvm_asm!("mov $0, x16" : "=r"(self.x16) : : "memory" : "volatile");
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llvm_asm!("mov x16, $0" : : "r"(next.x16) :"memory" : "volatile");
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llvm_asm!("mov $0, x17" : "=r"(self.x17) : : "memory" : "volatile");
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llvm_asm!("mov x17, $0" : : "r"(next.x17) :"memory" : "volatile");
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||||
llvm_asm!("mov $0, x18" : "=r"(self.x18) : : "memory" : "volatile");
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llvm_asm!("mov x18, $0" : : "r"(next.x18) :"memory" : "volatile");
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||||
|
||||
llvm_asm!("mov $0, x19" : "=r"(self.x19) : : "memory" : "volatile");
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llvm_asm!("mov x19, $0" : : "r"(next.x19) :"memory" : "volatile");
|
||||
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llvm_asm!("mov $0, x20" : "=r"(self.x20) : : "memory" : "volatile");
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||||
llvm_asm!("mov x20, $0" : : "r"(next.x20) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x21" : "=r"(self.x21) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x21, $0" : : "r"(next.x21) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x22" : "=r"(self.x22) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x22, $0" : : "r"(next.x22) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x23" : "=r"(self.x23) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x23, $0" : : "r"(next.x23) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x24" : "=r"(self.x24) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x24, $0" : : "r"(next.x24) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x25" : "=r"(self.x25) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x25, $0" : : "r"(next.x25) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x26" : "=r"(self.x26) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x26, $0" : : "r"(next.x26) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x27" : "=r"(self.x27) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x27, $0" : : "r"(next.x27) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x28" : "=r"(self.x28) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x28, $0" : : "r"(next.x28) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x29" : "=r"(self.fp) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x29, $0" : : "r"(next.fp) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, x30" : "=r"(self.lr) : : "memory" : "volatile");
|
||||
llvm_asm!("mov x30, $0" : : "r"(next.lr) :"memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, elr_el1" : "=r"(self.elr_el1) : : "memory" : "volatile");
|
||||
llvm_asm!("msr elr_el1, $0" : : "r"(next.elr_el1) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, sp_el0" : "=r"(self.sp_el0) : : "memory" : "volatile");
|
||||
llvm_asm!("msr sp_el0, $0" : : "r"(next.sp_el0) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, tpidr_el0" : "=r"(self.tpidr_el0) : : "memory" : "volatile");
|
||||
llvm_asm!("msr tpidr_el0, $0" : : "r"(next.tpidr_el0) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, tpidrro_el0" : "=r"(self.tpidrro_el0) : : "memory" : "volatile");
|
||||
llvm_asm!("msr tpidrro_el0, $0" : : "r"(next.tpidrro_el0) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, spsr_el1" : "=r"(self.spsr_el1) : : "memory" : "volatile");
|
||||
llvm_asm!("msr spsr_el1, $0" : : "r"(next.spsr_el1) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mrs $0, esr_el1" : "=r"(self.esr_el1) : : "memory" : "volatile");
|
||||
llvm_asm!("msr esr_el1, $0" : : "r"(next.esr_el1) : "memory" : "volatile");
|
||||
|
||||
llvm_asm!("mov $0, sp" : "=r"(self.sp) : : "memory" : "volatile");
|
||||
llvm_asm!("mov sp, $0" : : "r"(next.sp) : "memory" : "volatile");
|
||||
|
||||
CONTEXT_SWITCH_LOCK.store(false, Ordering::SeqCst);
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[repr(packed)]
|
||||
pub struct SignalHandlerStack {
|
||||
x28: usize, /* Callee saved Register */
|
||||
x27: usize, /* Callee saved Register */
|
||||
x26: usize, /* Callee saved Register */
|
||||
x25: usize, /* Callee saved Register */
|
||||
x24: usize, /* Callee saved Register */
|
||||
x23: usize, /* Callee saved Register */
|
||||
x22: usize, /* Callee saved Register */
|
||||
x21: usize, /* Callee saved Register */
|
||||
x20: usize, /* Callee saved Register */
|
||||
x19: usize, /* Callee saved Register */
|
||||
x18: usize,
|
||||
x17: usize,
|
||||
x16: usize,
|
||||
x15: usize, /* Temporary Register */
|
||||
x14: usize, /* Temporary Register */
|
||||
x13: usize, /* Temporary Register */
|
||||
x12: usize, /* Temporary Register */
|
||||
x11: usize, /* Temporary Register */
|
||||
x10: usize, /* Temporary Register */
|
||||
x9: usize, /* Temporary Register */
|
||||
x8: usize, /* Indirect location Register */
|
||||
x7: usize,
|
||||
x6: usize,
|
||||
x5: usize,
|
||||
x4: usize,
|
||||
x3: usize,
|
||||
x2: usize,
|
||||
x1: usize,
|
||||
x0: usize,
|
||||
lr: usize,
|
||||
handler: extern fn(usize),
|
||||
sig: usize,
|
||||
}
|
||||
|
||||
#[naked]
|
||||
unsafe extern fn signal_handler_wrapper() {
|
||||
#[inline(never)]
|
||||
unsafe fn inner(stack: &SignalHandlerStack) {
|
||||
(stack.handler)(stack.sig);
|
||||
}
|
||||
|
||||
// Push scratch registers
|
||||
llvm_asm!("str x0, [sp, #-8]!
|
||||
str x1, [sp, #-8]!
|
||||
str x2, [sp, #-8]!
|
||||
str x3, [sp, #-8]!
|
||||
str x4, [sp, #-8]!
|
||||
str x5, [sp, #-8]!
|
||||
str x6, [sp, #-8]!
|
||||
str x7, [sp, #-8]!
|
||||
str x8, [sp, #-8]!
|
||||
str x9, [sp, #-8]!
|
||||
str x10, [sp, #-8]!
|
||||
str x11, [sp, #-8]!
|
||||
str x12, [sp, #-8]!
|
||||
str x13, [sp, #-8]!
|
||||
str x14, [sp, #-8]!
|
||||
str x15, [sp, #-8]!
|
||||
str x16, [sp, #-8]!
|
||||
str x17, [sp, #-8]!
|
||||
str x18, [sp, #-8]!
|
||||
str x19, [sp, #-8]!
|
||||
str x20, [sp, #-8]!
|
||||
str x21, [sp, #-8]!
|
||||
str x22, [sp, #-8]!
|
||||
str x23, [sp, #-8]!
|
||||
str x24, [sp, #-8]!
|
||||
str x25, [sp, #-8]!
|
||||
str x26, [sp, #-8]!
|
||||
str x27, [sp, #-8]!
|
||||
str x28, [sp, #-8]!"
|
||||
: : : : "volatile");
|
||||
|
||||
// Get reference to stack variables
|
||||
let sp: usize;
|
||||
llvm_asm!("" : "={sp}"(sp) : : : "volatile");
|
||||
|
||||
let ptr = sp as *const SignalHandlerStack;
|
||||
let final_lr = (*ptr).lr;
|
||||
|
||||
// Call inner rust function
|
||||
inner(&*(sp as *const SignalHandlerStack));
|
||||
|
||||
// Pop scratch registers, error code, and return
|
||||
llvm_asm!("ldr x28, [sp], #8
|
||||
ldr x27, [sp], #8
|
||||
ldr x26, [sp], #8
|
||||
ldr x25, [sp], #8
|
||||
ldr x24, [sp], #8
|
||||
ldr x23, [sp], #8
|
||||
ldr x22, [sp], #8
|
||||
ldr x21, [sp], #8
|
||||
ldr x20, [sp], #8
|
||||
ldr x19, [sp], #8
|
||||
ldr x18, [sp], #8
|
||||
ldr x17, [sp], #8
|
||||
ldr x16, [sp], #8
|
||||
ldr x15, [sp], #8
|
||||
ldr x14, [sp], #8
|
||||
ldr x13, [sp], #8
|
||||
ldr x12, [sp], #8
|
||||
ldr x11, [sp], #8
|
||||
ldr x10, [sp], #8
|
||||
ldr x9, [sp], #8
|
||||
ldr x8, [sp], #8
|
||||
ldr x7, [sp], #8
|
||||
ldr x6, [sp], #8
|
||||
ldr x5, [sp], #8
|
||||
ldr x4, [sp], #8
|
||||
ldr x3, [sp], #8
|
||||
ldr x2, [sp], #8
|
||||
ldr x1, [sp], #8"
|
||||
: : : : "volatile");
|
||||
|
||||
llvm_asm!("mov x30, $0" : : "r"(final_lr) : "memory" : "volatile");
|
||||
}
|
||||
@@ -62,7 +62,7 @@ impl Context {
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_page_table(&mut self) -> usize {
|
||||
pub fn get_page_utable(&mut self) -> usize {
|
||||
self.cr3
|
||||
}
|
||||
|
||||
@@ -110,7 +110,7 @@ impl Context {
|
||||
self.fx = address;
|
||||
}
|
||||
|
||||
pub fn set_page_table(&mut self, address: usize) {
|
||||
pub fn set_page_utable(&mut self, address: usize) {
|
||||
self.cr3 = address;
|
||||
}
|
||||
|
||||
|
||||
+15
-3
@@ -4,7 +4,7 @@ use alloc::collections::BTreeMap;
|
||||
use core::alloc::{GlobalAlloc, Layout};
|
||||
use core::{iter, mem};
|
||||
use core::sync::atomic::Ordering;
|
||||
use crate::paging;
|
||||
use crate::paging::{ActivePageTable, PageTableType};
|
||||
use spin::RwLock;
|
||||
|
||||
use crate::syscall::error::{Result, Error, EAGAIN};
|
||||
@@ -79,18 +79,30 @@ impl ContextList {
|
||||
let context_lock = self.new_context()?;
|
||||
{
|
||||
let mut context = context_lock.write();
|
||||
let mut fx = unsafe { Box::from_raw(crate::ALLOCATOR.alloc(Layout::from_size_align_unchecked(512, 16)) as *mut [u8; 512]) };
|
||||
let mut fx = unsafe { Box::from_raw(crate::ALLOCATOR.alloc(Layout::from_size_align_unchecked(1024, 16)) as *mut [u8; 1024]) };
|
||||
for b in fx.iter_mut() {
|
||||
*b = 0;
|
||||
}
|
||||
let mut stack = vec![0; 65_536].into_boxed_slice();
|
||||
let offset = stack.len() - mem::size_of::<usize>();
|
||||
|
||||
#[cfg(target_arch = "x86_64")]
|
||||
unsafe {
|
||||
let offset = stack.len() - mem::size_of::<usize>();
|
||||
let func_ptr = stack.as_mut_ptr().add(offset);
|
||||
*(func_ptr as *mut usize) = func as usize;
|
||||
}
|
||||
context.arch.set_page_table(unsafe { paging::ActivePageTable::new().address() });
|
||||
|
||||
#[cfg(target_arch = "aarch64")]
|
||||
{
|
||||
let context_id = context.id.into();
|
||||
context.arch.set_lr(func as usize);
|
||||
context.arch.set_context_handle();
|
||||
}
|
||||
|
||||
context.arch.set_page_utable(unsafe { ActivePageTable::new(PageTableType::User).address() });
|
||||
#[cfg(target_arch = "aarch64")]
|
||||
context.arch.set_page_ktable(unsafe { ActivePageTable::new(PageTableType::Kernel).address() });
|
||||
context.arch.set_fx(fx.as_ptr() as usize);
|
||||
context.arch.set_stack(stack.as_ptr() as usize + offset);
|
||||
context.kfx = Some(fx);
|
||||
|
||||
+55
-13
@@ -15,7 +15,7 @@ use crate::arch::paging::PAGE_SIZE;
|
||||
use crate::context::file::FileDescriptor;
|
||||
use crate::ipi::{ipi, IpiKind, IpiTarget};
|
||||
use crate::memory::Frame;
|
||||
use crate::paging::{ActivePageTable, InactivePageTable, Page, PageFlags, PageIter, PhysicalAddress, RmmA, VirtualAddress};
|
||||
use crate::paging::{ActivePageTable, InactivePageTable, Page, PageFlags, PageTableType, PageIter, PhysicalAddress, RmmA, VirtualAddress};
|
||||
use crate::paging::mapper::PageFlushAll;
|
||||
use crate::paging::temporary_page::TemporaryPage;
|
||||
|
||||
@@ -303,7 +303,10 @@ impl Grant {
|
||||
}
|
||||
|
||||
pub fn physmap(from: PhysicalAddress, to: VirtualAddress, size: usize, flags: PageFlags<RmmA>) -> Grant {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match to.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -330,7 +333,10 @@ impl Grant {
|
||||
}
|
||||
|
||||
pub fn map(to: VirtualAddress, size: usize, flags: PageFlags<RmmA>) -> Grant {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match to.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -356,7 +362,10 @@ impl Grant {
|
||||
}
|
||||
|
||||
pub fn map_inactive(from: VirtualAddress, to: VirtualAddress, size: usize, flags: PageFlags<RmmA>, desc_opt: Option<FileDescriptor>, new_table: &mut InactivePageTable, temporary_page: &mut TemporaryPage) -> Grant {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match from.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
//TODO: Do not allocate
|
||||
let mut frames = VecDeque::with_capacity(size/PAGE_SIZE);
|
||||
@@ -368,6 +377,11 @@ impl Grant {
|
||||
frames.push_back(frame);
|
||||
}
|
||||
|
||||
let mut active_table = match to.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
active_table.with(new_table, temporary_page, |mapper| {
|
||||
let start_page = Page::containing_address(to);
|
||||
let end_page = Page::containing_address(VirtualAddress::new(to.data() + size - 1));
|
||||
@@ -397,7 +411,10 @@ impl Grant {
|
||||
pub fn secret_clone(&self, new_start: VirtualAddress) -> Grant {
|
||||
assert!(self.mapped);
|
||||
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match new_start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -454,7 +471,10 @@ impl Grant {
|
||||
pub fn move_to(&mut self, new_start: VirtualAddress, new_table: &mut InactivePageTable, temporary_page: &mut TemporaryPage) {
|
||||
assert!(self.mapped);
|
||||
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match new_start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -490,7 +510,11 @@ impl Grant {
|
||||
pub fn unmap(mut self) {
|
||||
assert!(self.mapped);
|
||||
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start_address().get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -519,7 +543,10 @@ impl Grant {
|
||||
pub fn unmap_inactive(mut self, new_table: &mut InactivePageTable, temporary_page: &mut TemporaryPage) {
|
||||
assert!(self.mapped);
|
||||
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start_address().get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
active_table.with(new_table, temporary_page, |mapper| {
|
||||
let start_page = Page::containing_address(self.start_address());
|
||||
@@ -694,7 +721,10 @@ impl Memory {
|
||||
}
|
||||
|
||||
fn map(&mut self, clear: bool) {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -714,7 +744,10 @@ impl Memory {
|
||||
}
|
||||
|
||||
fn unmap(&mut self) {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -729,7 +762,10 @@ impl Memory {
|
||||
/// A complicated operation to move a piece of memory to a new page table
|
||||
/// It also allows for changing the address at the same time
|
||||
pub fn move_to(&mut self, new_start: VirtualAddress, new_table: &mut InactivePageTable, temporary_page: &mut TemporaryPage) {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match new_start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -751,7 +787,10 @@ impl Memory {
|
||||
}
|
||||
|
||||
pub fn remap(&mut self, new_flags: PageFlags<RmmA>) {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
let flush_all = PageFlushAll::new();
|
||||
|
||||
@@ -766,7 +805,10 @@ impl Memory {
|
||||
}
|
||||
|
||||
pub fn resize(&mut self, new_size: usize, clear: bool) {
|
||||
let mut active_table = unsafe { ActivePageTable::new() };
|
||||
let mut active_table = match self.start.get_type() {
|
||||
VirtualAddressType::User => unsafe { ActivePageTable::new(PageTableType::User) },
|
||||
VirtualAddressType::Kernel => unsafe { ActivePageTable::new(PageTableType::Kernel) }
|
||||
};
|
||||
|
||||
//TODO: Calculate page changes to minimize operations
|
||||
if new_size > self.size {
|
||||
|
||||
+6
-1
@@ -10,6 +10,11 @@ pub use self::context::{Context, ContextId, ContextSnapshot, Status, WaitpidKey}
|
||||
pub use self::list::ContextList;
|
||||
pub use self::switch::switch;
|
||||
|
||||
#[cfg(target_arch = "aarch64")]
|
||||
#[path = "arch/aarch64.rs"]
|
||||
mod arch;
|
||||
|
||||
#[cfg(target_arch = "x86_64")]
|
||||
#[path = "arch/x86_64.rs"]
|
||||
mod arch;
|
||||
|
||||
@@ -52,7 +57,7 @@ pub fn init() {
|
||||
let mut contexts = contexts_mut();
|
||||
let context_lock = contexts.new_context().expect("could not initialize first context");
|
||||
let mut context = context_lock.write();
|
||||
let mut fx = unsafe { Box::from_raw(crate::ALLOCATOR.alloc(Layout::from_size_align_unchecked(512, 16)) as *mut [u8; 512]) };
|
||||
let mut fx = unsafe { Box::from_raw(crate::ALLOCATOR.alloc(Layout::from_size_align_unchecked(1024, 16)) as *mut [u8; 1024]) };
|
||||
for b in fx.iter_mut() {
|
||||
*b = 0;
|
||||
}
|
||||
|
||||
+12
-3
@@ -8,6 +8,7 @@ use spin::RwLock;
|
||||
|
||||
use crate::context::signal::signal_handler;
|
||||
use crate::context::{arch, contexts, Context, Status, CONTEXT_ID};
|
||||
#[cfg(target_arch = "x86_64")]
|
||||
use crate::gdt;
|
||||
use crate::interrupt::irq::PIT_TICKS;
|
||||
use crate::interrupt;
|
||||
@@ -165,10 +166,18 @@ pub unsafe fn switch() -> bool {
|
||||
|
||||
from_context_guard.running = false;
|
||||
to_context.running = true;
|
||||
if let Some(ref stack) = to_context.kstack {
|
||||
gdt::set_tss_stack(stack.as_ptr() as usize + stack.len());
|
||||
#[cfg(target_arch = "x86_64")]
|
||||
{
|
||||
if let Some(ref stack) = to_context.kstack {
|
||||
gdt::set_tss_stack(stack.as_ptr() as usize + stack.len());
|
||||
}
|
||||
gdt::set_tcb(to_context.id.into());
|
||||
}
|
||||
#[cfg(target_arch = "aarch64")]
|
||||
{
|
||||
let pid = to_context.id.into();
|
||||
to_context.arch.set_tcb(pid);
|
||||
}
|
||||
gdt::set_tcb(to_context.id.into());
|
||||
CONTEXT_ID.store(to_context.id, Ordering::SeqCst);
|
||||
|
||||
if let Some(sig) = to_sig {
|
||||
|
||||
Reference in New Issue
Block a user