diff --git a/alxd/src/device/mod.rs b/alxd/src/device/mod.rs index 26395be10a..04da35d59e 100644 --- a/alxd/src/device/mod.rs +++ b/alxd/src/device/mod.rs @@ -213,13 +213,15 @@ struct Tpd { blen: Mmio, vlan: Mmio, flags: Mmio, - addr: Mmio, + addr_low: Mmio, + addr_high: Mmio, } /// Receive free descriptor #[repr(packed)] struct Rfd { - addr: Mmio, + addr_low: Mmio, + addr_high: Mmio, } /// Receive return descriptor @@ -1529,7 +1531,8 @@ impl Alx { // RFD ring for i in 0..self.rfd_ring.len() { - self.rfd_ring[i].addr.write(self.rfd_buffer[i].physical() as u64); + self.rfd_ring[i].addr_low.write(self.rfd_buffer[i].physical() as u32); + self.rfd_ring[i].addr_high.write(((self.rfd_buffer[i].physical() as u64) >> 32) as u32); } self.write(RFD_ADDR_LO, self.rfd_ring.physical() as u32); self.write(RFD_RING_SZ, self.rfd_ring.len() as u32); diff --git a/alxd/src/main.rs b/alxd/src/main.rs index 4de3005c6e..d52371f94a 100644 --- a/alxd/src/main.rs +++ b/alxd/src/main.rs @@ -112,7 +112,7 @@ fn main() { for event_count in event_queue.trigger_all(event::Event { fd: 0, - flags: EventFlags::empty(), + flags: EventFlags::empty(), }).expect("alxd: failed to trigger events") { socket.borrow_mut().write(&Packet { id: 0, diff --git a/ihdad/src/hda/cmdbuff.rs b/ihdad/src/hda/cmdbuff.rs index 36ee9f2237..a401a1053a 100644 --- a/ihdad/src/hda/cmdbuff.rs +++ b/ihdad/src/hda/cmdbuff.rs @@ -73,6 +73,7 @@ struct Corb { impl Corb { pub fn new(regs_addr: usize, corb_buff_phys: usize, corb_buff_virt: usize) -> Corb { + println!("regs addr {:x}", regs_addr); unsafe { Corb { regs: &mut *(regs_addr as *mut CorbRegs), @@ -84,7 +85,9 @@ impl Corb { } //Intel 4.4.1.3 pub fn init(&mut self) { + println!("{}:{}", file!(), line!()); self.stop(); + println!("{}:{}", file!(), line!()); //Determine CORB and RIRB size and allocate buffer //3.3.24 @@ -122,6 +125,7 @@ impl Corb { self.regs.corbctl.writef(CORBRUN, true); } + #[inline(never)] pub fn stop(&mut self) { while self.regs.corbctl.readf(CORBRUN) { self.regs.corbctl.write(0); diff --git a/ihdad/src/hda/device.rs b/ihdad/src/hda/device.rs index 9778ba1b09..718ab6ed73 100755 --- a/ihdad/src/hda/device.rs +++ b/ihdad/src/hda/device.rs @@ -459,7 +459,7 @@ impl IntelHDA { let o = self.output_streams.get_mut(0).unwrap(); for i in 0..NUM_SUB_BUFFS { - self.buff_desc[i].set_address(o.phys() + o.block_size() * i); + self.buff_desc[i].set_address((o.phys() + o.block_size() * i) as u64); self.buff_desc[i].set_length(o.block_size() as u32); self.buff_desc[i].set_interrupt_on_complete(true); } @@ -741,7 +741,7 @@ impl IntelHDA { } } - fn set_dma_position_buff_addr(&mut self, addr: usize) { + fn set_dma_position_buff_addr(&mut self, addr: u64) { let addr_val = addr & !0x7F; self.regs.dplbase.write((addr_val & 0xFFFFFFFF) as u32); self.regs.dpubase.write((addr_val >> 32) as u32); diff --git a/ihdad/src/hda/stream.rs b/ihdad/src/hda/stream.rs index 3f1e383419..62acd2c6d5 100644 --- a/ihdad/src/hda/stream.rs +++ b/ihdad/src/hda/stream.rs @@ -246,18 +246,21 @@ impl OutputStream { #[repr(packed)] pub struct BufferDescriptorListEntry { - addr: Mmio, + addr_low: Mmio, + addr_high: Mmio, len: Mmio, ioc_resv: Mmio, } impl BufferDescriptorListEntry { - pub fn address(&self) -> usize { - self.addr.read() as usize + pub fn address(&self) -> u64 { + (self.addr_low.read() as u64) | + ((self.addr_high.read() as u64) << 32) } - pub fn set_address(&mut self, addr:usize) { - self.addr.write(addr as u64); + pub fn set_address(&mut self, addr: u64) { + self.addr_low.write(addr as u32); + self.addr_high.write((addr >> 32) as u32); } pub fn length(&self) -> u32 { diff --git a/rtl8168d/src/device.rs b/rtl8168d/src/device.rs index a32a5199ee..c3663b8b76 100644 --- a/rtl8168d/src/device.rs +++ b/rtl8168d/src/device.rs @@ -61,14 +61,16 @@ const LS: u32 = 1 << 28; struct Rd { ctrl: Mmio, _vlan: Mmio, - buffer: Mmio + buffer_low: Mmio, + buffer_high: Mmio, } #[repr(packed)] struct Td { ctrl: Mmio, _vlan: Mmio, - buffer: Mmio + buffer_low: Mmio, + buffer_high: Mmio, } pub struct Rtl8168 { @@ -299,7 +301,8 @@ impl Rtl8168 { for i in 0..self.receive_ring.len() { let rd = &mut self.receive_ring[i]; let data = &mut self.receive_buffer[i]; - rd.buffer.write(data.physical() as u64); + rd.buffer_low.write(data.physical() as u32); + rd.buffer_high.write((data.physical() as u64 >> 32) as u32); rd.ctrl.write(OWN | data.len() as u32); } if let Some(rd) = self.receive_ring.last_mut() { @@ -309,7 +312,8 @@ impl Rtl8168 { // Set up normal priority tx buffers println!(" - Transmit buffers (normal priority)"); for i in 0..self.transmit_ring.len() { - self.transmit_ring[i].buffer.write(self.transmit_buffer[i].physical() as u64); + self.transmit_ring[i].buffer_low.write(self.transmit_buffer[i].physical() as u32); + self.transmit_ring[i].buffer_high.write((self.transmit_buffer[i].physical() as u64 >> 32) as u32); } if let Some(td) = self.transmit_ring.last_mut() { td.ctrl.writef(EOR, true); @@ -318,7 +322,8 @@ impl Rtl8168 { // Set up high priority tx buffers println!(" - Transmit buffers (high priority)"); for i in 0..self.transmit_ring_h.len() { - self.transmit_ring_h[i].buffer.write(self.transmit_buffer_h[i].physical() as u64); + self.transmit_ring_h[i].buffer_low.write(self.transmit_buffer_h[i].physical() as u32); + self.transmit_ring_h[i].buffer_high.write((self.transmit_buffer_h[i].physical() as u64 >> 32) as u32); } if let Some(td) = self.transmit_ring_h.last_mut() { td.ctrl.writef(EOR, true);