rtl8168d: DMA barriers + drop false RTL8125 claim from config.toml
- device.rs: release fence before tppoll doorbell write; acquire fence after the OWN-bit read on the receive descriptor. The Realtek descriptor hand-off is the same OWN-bit protocol as e1000d, and the same reordering argument applies: on aarch64 with relaxed ordering the device can clear OWN and update length+status in any order, and without a fence we can observe OWN=0 paired with a stale length and compute a partial read. - config.toml: drop the description's RTL8125 reference. The rtl8168d register layout does not support rtl8125 (a 2.5GbE chip with its own register layout and PHY init sequence); the description now matches the actual capability.
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@@ -1,5 +1,5 @@
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[[drivers]]
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name = "RTL8168 NIC"
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name = "RTL8168/8169 NIC"
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class = 0x02
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ids = { 0x10ec = [0x8168, 0x8169] }
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command = ["rtl8168d"]
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@@ -95,7 +95,9 @@ impl NetworkAdapter for Rtl8168 {
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}
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let rd = &mut self.receive_ring[self.receive_i];
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if !rd.ctrl.readf(OWN) {
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let own = rd.ctrl.readf(OWN);
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if !own {
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core::sync::atomic::fence(core::sync::atomic::Ordering::Acquire);
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let rd_len = rd.ctrl.read() & 0x3FFF;
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let data = &self.receive_buffer[self.receive_i];
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@@ -133,14 +135,15 @@ impl NetworkAdapter for Rtl8168 {
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let mut i = 0;
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while i < buf.len() && i < data.len() {
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data[i].write(buf[i]);
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i += 1;
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}
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data[i].write(buf[i]);
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i += 1;
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}
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let eor = td.ctrl.read() & EOR;
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td.ctrl.write(OWN | eor | FS | LS | i as u32);
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let eor = td.ctrl.read() & EOR;
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td.ctrl.write(OWN | eor | FS | LS | i as u32);
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self.regs.tppoll.writef(1 << 6, true); //Notify of normal priority packet
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core::sync::atomic::fence(core::sync::atomic::Ordering::Release);
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self.regs.tppoll.writef(1 << 6, true); //Notify of normal priority packet
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while self.regs.tppoll.readf(1 << 6) {
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std::hint::spin_loop();
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