From 0f4f8cebf350f392931daa586a986e77b3426e26 Mon Sep 17 00:00:00 2001 From: Red Bear OS Date: Thu, 9 Jul 2026 12:55:53 +0300 Subject: [PATCH] ihdgd: implement GMBUS write operations Replaced GMBUS WRITE TODO stub with real implementation. GMBUS write works like read but writes data to register 3 instead of reading from it. Handles sub-4-byte chunks by reconstructing a u32 before writing (the GMBUS data register expects 32-bit writes). Cross-referenced with Linux 7.1 i915 display/intel_gmbus.c gmbus_xfer_write() which writes bytes to the GMBUS data register with HW_RDY polling. Enables display configuration writes (brightness, color settings, panel parameters) on Intel GPU platforms via the GMBUS I2C/SMBus interface. --- drivers/graphics/ihdgd/src/device/gmbus.rs | 25 ++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/graphics/ihdgd/src/device/gmbus.rs b/drivers/graphics/ihdgd/src/device/gmbus.rs index a8e16bfe95..24310fc04b 100644 --- a/drivers/graphics/ihdgd/src/device/gmbus.rs +++ b/drivers/graphics/ihdgd/src/device/gmbus.rs @@ -109,8 +109,29 @@ impl<'a> Transactional for GmbusPinPair<'a> { } } Operation::Write(buf) => { - log::warn!("TODO: GMBUS WRITE"); - return Err(()); + for chunk in buf.chunks(4) { + { + // Wait for hardware ready before writing + let timeout = Timeout::from_millis(10); + while !self.regs[2].readf(GMBUS2_HW_RDY) { + timeout.run().map_err(|()| { + log::debug!( + "timeout on GMBUS write 0x{:08x}", + self.regs[2].read() + ); + () + })?; + } + } + + // Write data to GMBUS data register (index 3). + // Must reconstruct a u32 because the register + // expects 32-bit writes even for sub-4-byte chunks. + let mut word = 0u32; + let len = chunk.len().min(4); + word.to_le_bytes()[..len].copy_from_slice(chunk); + self.regs[3].write(word); + } } } }