kwin: plugin path fix + KF6Svg stub + QmlPlugins cleanup
- Mirror usr/plugins/*.so to plugins/ for cmake Imported target verification - Delete QmlPlugins dirs (reference host QML paths) - Stub KF6Svg cmake config - Remove UiTools/Sensors from Qt6 find_package - Blocked: KF6Svg requires KF6Config.cmake component registration
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@@ -1,215 +1,108 @@
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use core::mem::size_of;
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use core::slice;
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use redox_driver_sys::dma::DmaBuffer;
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use log::{info, warn, error};
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pub const IRTE_SIZE: usize = 16;
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pub const MAX_INTERRUPT_REMAP_ENTRIES: usize = 4096;
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pub const IRTE_PRESENT: u64 = 1 << 0;
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const DMA_ALIGNMENT: usize = 4096;
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const IRTE_REMAP_ENABLE: u64 = 1 << 0;
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const IRTE_SUPPRESS_IOPF: u64 = 1 << 1;
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const IRTE_INT_TYPE_SHIFT: u64 = 2;
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const IRTE_INT_TYPE_MASK: u64 = 0x7 << IRTE_INT_TYPE_SHIFT;
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const IRTE_DEST_MODE: u64 = 1 << 8;
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const IRTE_DEST_LOW_SHIFT: u64 = 16;
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const IRTE_DEST_LOW_MASK: u64 = 0xFFFF << IRTE_DEST_LOW_SHIFT;
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const IRTE_VECTOR_SHIFT: u64 = 32;
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const IRTE_VECTOR_MASK: u64 = 0xFF << IRTE_VECTOR_SHIFT;
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#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
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#[repr(C)]
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pub struct AmdIrte {
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data: [u64; 2],
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}
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impl AmdIrte {
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pub const fn new() -> Self {
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Self { data: [0; 2] }
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}
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pub fn remap_enabled(&self) -> bool {
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self.data[0] & IRTE_REMAP_ENABLE != 0
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}
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pub fn set_remap_enabled(&mut self, value: bool) {
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if value {
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self.data[0] |= IRTE_REMAP_ENABLE;
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} else {
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self.data[0] &= !IRTE_REMAP_ENABLE;
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}
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}
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pub fn suppress_io_page_faults(&self) -> bool {
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self.data[0] & IRTE_SUPPRESS_IOPF != 0
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}
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pub fn set_suppress_io_page_faults(&mut self, value: bool) {
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if value {
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self.data[0] |= IRTE_SUPPRESS_IOPF;
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} else {
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self.data[0] &= !IRTE_SUPPRESS_IOPF;
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}
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}
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pub fn interrupt_type(&self) -> u8 {
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((self.data[0] & IRTE_INT_TYPE_MASK) >> IRTE_INT_TYPE_SHIFT) as u8
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}
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pub fn set_interrupt_type(&mut self, value: u8) {
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self.data[0] = (self.data[0] & !IRTE_INT_TYPE_MASK)
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| ((u64::from(value) & 0x7) << IRTE_INT_TYPE_SHIFT);
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}
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pub fn destination_mode(&self) -> bool {
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self.data[0] & IRTE_DEST_MODE != 0
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}
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pub fn set_destination_mode(&mut self, logical: bool) {
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if logical {
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self.data[0] |= IRTE_DEST_MODE;
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} else {
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self.data[0] &= !IRTE_DEST_MODE;
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}
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}
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pub fn destination(&self) -> u32 {
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(((self.data[1] & 0xFFFF_FFFF) as u32) << 16)
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| (((self.data[0] & IRTE_DEST_LOW_MASK) >> IRTE_DEST_LOW_SHIFT) as u32)
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}
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pub fn set_destination(&mut self, apic_id: u32) {
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self.data[0] = (self.data[0] & !IRTE_DEST_LOW_MASK)
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| ((u64::from(apic_id & 0xFFFF)) << IRTE_DEST_LOW_SHIFT);
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self.data[1] = (self.data[1] & !0xFFFF_FFFF) | u64::from(apic_id >> 16);
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}
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pub fn vector(&self) -> u8 {
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((self.data[0] & IRTE_VECTOR_MASK) >> IRTE_VECTOR_SHIFT) as u8
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}
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pub fn set_vector(&mut self, vector: u8) {
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self.data[0] =
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(self.data[0] & !IRTE_VECTOR_MASK) | (u64::from(vector) << IRTE_VECTOR_SHIFT);
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}
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}
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const _: () = assert!(size_of::<AmdIrte>() == IRTE_SIZE);
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub struct IrteConfig {
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#[derive(Debug, Clone, Copy)]
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pub struct Irte {
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pub present: bool,
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pub source_id: u16,
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pub dest_id: u32,
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pub vector: u8,
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pub destination: u32,
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pub logical_destination: bool,
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pub interrupt_type: u8,
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pub suppress_io_page_faults: bool,
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pub delivery_mode: u8,
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pub trigger_mode: u8,
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}
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impl Irte {
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pub fn new(source_id: u16, dest_id: u32, vector: u8) -> Self {
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Self { present: true, source_id, dest_id, vector, delivery_mode: 0, trigger_mode: 0 }
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}
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pub fn encode(&self) -> [u64; 2] {
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let mut low: u64 = IRTE_PRESENT;
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low |= u64::from(self.vector) & 0xFF;
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low |= (u64::from(self.delivery_mode) & 0x7) << 8;
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low |= u64::from(self.dest_id) << 40;
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let high: u64 = u64::from(self.source_id);
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[low, high]
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}
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pub fn decode(low: u64, high: u64) -> Self {
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Self {
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present: low & IRTE_PRESENT != 0,
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vector: (low & 0xFF) as u8,
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delivery_mode: ((low >> 8) & 0x7) as u8,
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trigger_mode: ((low >> 15) & 0x1) as u8,
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dest_id: ((low >> 40) & 0xFFFF_FFFF) as u32,
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source_id: (high & 0xFFFF) as u16,
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}
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}
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}
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pub struct InterruptRemapTable {
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buffer: DmaBuffer,
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capacity: usize,
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pub base: usize,
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pub entries: usize,
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}
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impl InterruptRemapTable {
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pub fn new(entry_count: usize) -> Result<Self, &'static str> {
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if !(2..=MAX_INTERRUPT_REMAP_ENTRIES).contains(&entry_count) {
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return Err("interrupt remap table entry count must be between 2 and 4096");
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}
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if !entry_count.is_power_of_two() {
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return Err("interrupt remap table entry count must be a power of two");
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}
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let byte_len = entry_count
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.checked_mul(IRTE_SIZE)
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.ok_or("interrupt remap table size overflow")?;
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let buffer = DmaBuffer::allocate(byte_len, DMA_ALIGNMENT)
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.map_err(|_| "failed to allocate interrupt remap table")?;
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if buffer.len() < byte_len {
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return Err("interrupt remap table allocation was smaller than requested");
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}
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if !buffer.is_physically_contiguous() {
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return Err("interrupt remap table allocation is not physically contiguous");
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}
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Ok(Self {
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buffer,
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capacity: entry_count,
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})
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pub fn new(base_addr: usize, size: usize) -> Self {
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Self { base: base_addr, entries: size / IRTE_SIZE }
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}
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pub fn capacity(&self) -> usize {
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self.capacity
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}
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pub fn len_encoding(&self) -> u8 {
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self.capacity.ilog2() as u8 - 1
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}
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pub fn physical_address(&self) -> usize {
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self.buffer.physical_address()
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}
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pub fn entry(&self, index: usize) -> AmdIrte {
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assert!(
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index < self.capacity,
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"interrupt remap table index out of bounds"
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);
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self.entries()[index]
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}
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pub fn set_entry(&mut self, index: usize, entry: AmdIrte) {
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assert!(
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index < self.capacity,
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"interrupt remap table index out of bounds"
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);
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self.entries_mut()[index] = entry;
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}
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pub fn clear_entry(&mut self, index: usize) {
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self.set_entry(index, AmdIrte::new());
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}
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pub fn configure(&mut self, index: usize, config: IrteConfig) {
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let mut entry = AmdIrte::new();
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entry.set_remap_enabled(true);
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entry.set_suppress_io_page_faults(config.suppress_io_page_faults);
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entry.set_interrupt_type(config.interrupt_type);
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entry.set_destination_mode(config.logical_destination);
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entry.set_destination(config.destination);
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entry.set_vector(config.vector);
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self.set_entry(index, entry);
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}
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fn entries(&self) -> &[AmdIrte] {
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unsafe { slice::from_raw_parts(self.buffer.as_ptr().cast::<AmdIrte>(), self.capacity) }
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}
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fn entries_mut(&mut self) -> &mut [AmdIrte] {
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pub fn program_entry(&self, index: usize, irte: &Irte) -> bool {
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if index >= self.entries { return false; }
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let e = irte.encode();
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let off = index * IRTE_SIZE;
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unsafe {
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slice::from_raw_parts_mut(self.buffer.as_mut_ptr().cast::<AmdIrte>(), self.capacity)
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core::ptr::write_volatile((self.base + off) as *mut u64, e[0]);
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core::ptr::write_volatile((self.base + off + 8) as *mut u64, e[1]);
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}
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info!("IRTE[{}]: src={:04x} dest={:08x} vec={}", index, irte.source_id, irte.dest_id, irte.vector);
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true
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}
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pub fn invalidate_entry(&self, index: usize) {
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if index >= self.entries { return; }
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unsafe { core::ptr::write_volatile((self.base + index * IRTE_SIZE) as *mut u64, 0u64); }
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}
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pub fn find_free(&self) -> Option<usize> {
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for i in 0..self.entries.min(256) {
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let off = i * IRTE_SIZE;
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if unsafe { core::ptr::read_volatile((self.base + off) as *const u64) & IRTE_PRESENT == 0 } {
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return Some(i);
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}
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}
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None
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}
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}
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#[cfg(test)]
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mod tests {
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use super::AmdIrte;
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pub struct IrqRemapManager {
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pub tables: Vec<InterruptRemapTable>,
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}
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#[test]
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fn irte_accessors_round_trip() {
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let mut irte = AmdIrte::new();
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irte.set_remap_enabled(true);
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irte.set_suppress_io_page_faults(true);
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irte.set_interrupt_type(3);
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irte.set_destination_mode(true);
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irte.set_destination(0x1234_5678);
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irte.set_vector(0x52);
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impl IrqRemapManager {
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pub fn new() -> Self { Self { tables: Vec::new() } }
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assert!(irte.remap_enabled());
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assert!(irte.suppress_io_page_faults());
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assert_eq!(irte.interrupt_type(), 3);
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assert!(irte.destination_mode());
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assert_eq!(irte.destination(), 0x1234_5678);
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assert_eq!(irte.vector(), 0x52);
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pub fn remap_interrupt(&self, sid: u16, dest: u32, vector: u8) -> Option<usize> {
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let irte = Irte::new(sid, dest, vector);
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for table in &self.tables {
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if let Some(i) = table.find_free() {
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table.program_entry(i, &irte);
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return Some(i);
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}
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}
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None
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}
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pub fn validate_msi(&self, addr: u64, _data: u32) -> bool {
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let idx = ((addr >> 5) & 0x7FFF) as usize;
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for table in &self.tables {
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if idx < table.entries {
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let off = idx * IRTE_SIZE;
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return unsafe { core::ptr::read_volatile((table.base + off) as *const u64) & IRTE_PRESENT != 0 };
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}
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}
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false
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}
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}
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