From 07d5d730d237fb6b2cd9031fa88c33b12a99eeb6 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Thu, 18 Jan 2024 19:32:14 +0100
Subject: [PATCH] Remove nolock CfgAccess methods

They are only called by the corresponding locked methods.
---
 pcid/src/pci/mod.rs  | 27 ++++++---------------------
 pcid/src/pcie/mod.rs | 15 ++++++---------
 2 files changed, 12 insertions(+), 30 deletions(-)

diff --git a/pcid/src/pci/mod.rs b/pcid/src/pci/mod.rs
index e1a18b472f..f5cb4a6d00 100644
--- a/pcid/src/pci/mod.rs
+++ b/pcid/src/pci/mod.rs
@@ -23,10 +23,7 @@ pub mod header;
 pub mod msi;
 
 pub trait CfgAccess {
-    unsafe fn read_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32;
     unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32;
-
-    unsafe fn write_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32);
     unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32);
 }
 
@@ -68,7 +65,9 @@ impl Pci {
 }
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 impl CfgAccess for Pci {
-    unsafe fn read_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+    unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+        let _guard = self.lock.lock().unwrap();
+
         self.iopl_once.call_once(Self::set_iopl);
 
         let offset = u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
@@ -78,12 +77,9 @@ impl CfgAccess for Pci {
         Pio::<u32>::new(0xCFC).read()
     }
 
-    unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+    unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
         let _guard = self.lock.lock().unwrap();
-        self.read_nolock(bus, dev, func, offset)
-    }
 
-    unsafe fn write_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
         self.iopl_once.call_once(Self::set_iopl);
 
         let offset = u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
@@ -92,28 +88,17 @@ impl CfgAccess for Pci {
         Pio::<u32>::new(0xCF8).write(address);
         Pio::<u32>::new(0xCFC).write(value);
     }
-    unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
-        let _guard = self.lock.lock().unwrap();
-        self.write_nolock(bus, dev, func, offset, value)
-    }
 }
 #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
 impl CfgAccess for Pci {
-    unsafe fn read_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
-        todo!("Pci::CfgAccess::read_nolock on this architecture")
-    }
-
     unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
         let _guard = self.lock.lock().unwrap();
-        self.read_nolock(bus, dev, func, offset)
+        todo!("Pci::CfgAccess::read on this architecture")
     }
 
-    unsafe fn write_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
-        todo!("Pci::CfgAccess::write_nolock on this architecture")
-    }
     unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
         let _guard = self.lock.lock().unwrap();
-        self.write_nolock(bus, dev, func, offset, value)
+        todo!("Pci::CfgAccess::write on this architecture")
     }
 }
 
diff --git a/pcid/src/pcie/mod.rs b/pcid/src/pcie/mod.rs
index 995f4b7482..2fa4994ca3 100644
--- a/pcid/src/pcie/mod.rs
+++ b/pcid/src/pcie/mod.rs
@@ -189,26 +189,23 @@ impl Pcie {
 }
 
 impl CfgAccess for Pcie {
-    unsafe fn read_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+    unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+        let _guard = self.lock.lock().unwrap();
+
         self.with_pointer(bus, dev, func, offset, |pointer| match pointer {
             Some(address) => ptr::read_volatile::<u32>(address),
             None => self.fallback.read(bus, dev, func, offset),
         })
     }
-    unsafe fn read(&self, bus: u8, dev: u8, func: u8, offset: u16) -> u32 {
+
+    unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
         let _guard = self.lock.lock().unwrap();
-        self.read_nolock(bus, dev, func, offset)
-    }
-    unsafe fn write_nolock(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
+
         self.with_pointer(bus, dev, func, offset, |pointer| match pointer {
             Some(address) => ptr::write_volatile::<u32>(address, value),
             None => { self.fallback.read(bus, dev, func, offset); }
         });
     }
-    unsafe fn write(&self, bus: u8, dev: u8, func: u8, offset: u16, value: u32) {
-        let _guard = self.lock.lock().unwrap();
-        self.write_nolock(bus, dev, func, offset, value);
-    }
 }
 
 impl Drop for Pcie {