pcid: Don't include source files in two different crates

This confuses rust-analyzer.
This commit is contained in:
bjorn3
2024-06-16 15:29:09 +02:00
parent 6d15fbba75
commit 07aaf6ea94
8 changed files with 26 additions and 27 deletions
+1 -1
View File
@@ -8,7 +8,7 @@ pub struct VendorSpecificCapability {
}
impl VendorSpecificCapability {
pub(crate) unsafe fn parse(
pub unsafe fn parse(
addr: PciCapabilityAddress,
access: &dyn ConfigRegionAccess,
) -> Self {
+1 -1
View File
@@ -13,7 +13,7 @@ pub struct FullDeviceId {
}
impl FullDeviceId {
pub(crate) fn display(&self) -> String {
pub fn display(&self) -> String {
let mut string = format!(
"{:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
self.vendor_id,
+1 -1
View File
@@ -194,5 +194,5 @@ pub fn allocate_single_interrupt_vector_for_msi(cpu_id: usize) -> (MsiAddrAndDat
let msg_data =
x86_msix::message_data_edge_triggered(x86_msix::DeliveryMode::Fixed, vector);
(MsiAddrAndData::new(addr, msg_data), interrupt_handle)
(MsiAddrAndData { addr, data: msg_data }, interrupt_handle)
}
+5 -3
View File
@@ -21,7 +21,7 @@ pub mod irq_helpers;
pub mod msi;
#[derive(Clone, Copy, Debug, Serialize, Deserialize)]
pub struct LegacyInterruptLine(pub(crate) u8);
pub struct LegacyInterruptLine(#[doc(hidden)] pub u8);
impl LegacyInterruptLine {
/// Get an IRQ handle for this interrupt line.
@@ -257,7 +257,8 @@ pub struct PciFunctionHandle {
mapped_bars: [Option<MappedBar>; 6],
}
pub(crate) fn send<W: Write, T: Serialize>(w: &mut W, message: &T) -> Result<()> {
#[doc(hidden)]
pub fn send<W: Write, T: Serialize>(w: &mut W, message: &T) -> Result<()> {
let mut data = Vec::new();
bincode::serialize_into(&mut data, message)?;
let length_bytes = u64::to_le_bytes(data.len() as u64);
@@ -265,7 +266,8 @@ pub(crate) fn send<W: Write, T: Serialize>(w: &mut W, message: &T) -> Result<()>
w.write_all(&data)?;
Ok(())
}
pub(crate) fn recv<R: Read, T: DeserializeOwned>(r: &mut R) -> Result<T> {
#[doc(hidden)]
pub fn recv<R: Read, T: DeserializeOwned>(r: &mut R) -> Result<T> {
let mut length_bytes = [0u8; 8];
r.read_exact(&mut length_bytes)?;
let length = u64::from_le_bytes(length_bytes);
+2 -8
View File
@@ -11,14 +11,8 @@ use syscall::{Io, Mmio};
/// For MSI-X you can have a single [MsiEntry] for each interrupt vector.
#[derive(Debug, Default, Serialize, Deserialize)]
pub struct MsiAddrAndData {
pub(crate) addr: u64,
pub(crate) data: u32,
}
impl MsiAddrAndData {
pub fn new(addr: u64, data: u32) -> Self {
MsiAddrAndData { addr, data }
}
pub addr: u64,
pub data: u32,
}
#[derive(Debug, Serialize, Deserialize)]