WIP: aarch64 rebase
This commit is contained in:
Robin Randhawa
committed by
Jeremy Soller
Jeremy Soller
parent
5e10feeaeb
commit
02c37d3fae
@@ -0,0 +1,359 @@
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use core::mem;
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use core::sync::atomic::{AtomicBool, AtomicUsize, ATOMIC_BOOL_INIT, ATOMIC_USIZE_INIT, Ordering};
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use crate::device::cpu::registers::{control_regs, tlb};
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/// This must be used by the kernel to ensure that context switches are done atomically
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/// Compare and exchange this to true when beginning a context switch on any CPU
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/// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch
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/// This must be done, as no locks can be held on the stack during switch
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pub static CONTEXT_SWITCH_LOCK: AtomicBool = ATOMIC_BOOL_INIT;
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#[derive(Clone, Debug)]
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pub struct Context {
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elr_el1: usize,
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sp_el0: usize,
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ttbr0_el1: usize, /* Pointer to U4 translation table for this Context */
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tpidr_el0: usize, /* Pointer to TLS region for this Context */
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tpidrro_el0: usize, /* Pointer to TLS (read-only) region for this Context */
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rflags: usize,
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esr_el1: usize,
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padding: usize,
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sp: usize, /* Stack Pointer (x31) */
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lr: usize, /* Link Register (x30) */
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fp: usize, /* Frame pointer Register (x29) */
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x28: usize, /* Callee saved Register */
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x27: usize, /* Callee saved Register */
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x26: usize, /* Callee saved Register */
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x25: usize, /* Callee saved Register */
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x24: usize, /* Callee saved Register */
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x23: usize, /* Callee saved Register */
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x22: usize, /* Callee saved Register */
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x21: usize, /* Callee saved Register */
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x20: usize, /* Callee saved Register */
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x19: usize, /* Callee saved Register */
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x18: usize,
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x17: usize,
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x16: usize,
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x15: usize, /* Temporary Register */
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x14: usize, /* Temporary Register */
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x13: usize, /* Temporary Register */
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x12: usize, /* Temporary Register */
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x11: usize, /* Temporary Register */
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x10: usize, /* Temporary Register */
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x9: usize, /* Temporary Register */
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x8: usize, /* Indirect location Register */
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}
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static CONTEXT_COUNT: AtomicUsize = ATOMIC_USIZE_INIT;
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impl Context {
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pub fn new() -> Context {
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Context {
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elr_el1: 0,
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sp_el0: 0,
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ttbr0_el1: 0,
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tpidr_el0: 0,
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tpidrro_el0: 0,
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rflags: 0, /* spsr_el1 */
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esr_el1: 0,
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padding: 0xbeef0000 | CONTEXT_COUNT.fetch_add(1, Ordering::SeqCst),
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sp: 0,
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lr: 0,
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fp: 0,
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x28: 0,
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x27: 0,
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x26: 0,
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x25: 0,
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x24: 0,
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x23: 0,
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x22: 0,
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x21: 0,
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x20: 0,
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x19: 0,
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x18: 0,
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x17: 0,
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x16: 0,
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x15: 0,
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x14: 0,
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x13: 0,
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x12: 0,
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x11: 0,
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x10: 0,
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x9: 0,
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x8: 0,
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}
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}
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pub fn get_page_table(&self) -> usize {
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self.ttbr0_el1
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}
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pub fn set_fx(&mut self, _address: usize) {
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}
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pub fn set_page_table(&mut self, address: usize) {
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self.ttbr0_el1 = address;
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}
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pub fn set_stack(&mut self, address: usize) {
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self.sp = address;
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}
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pub fn set_lr(&mut self, address: usize) {
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self.lr = address;
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}
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pub fn set_fp(&mut self, address: usize) {
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self.fp = address;
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}
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pub fn set_context_handle(&mut self) {
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let address = self as *const _ as usize;
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self.tpidrro_el0 = address;
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}
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pub fn get_context_handle(&mut self) -> usize {
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self.tpidrro_el0
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}
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pub unsafe fn signal_stack(&mut self, handler: extern fn(usize), sig: u8) {
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self.push_stack(sig as usize);
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self.push_stack(handler as usize);
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let lr = self.lr.clone();
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self.push_stack(lr);
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self.set_lr(signal_handler_wrapper as usize);
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}
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pub unsafe fn push_stack(&mut self, value: usize) {
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self.sp -= 1 * mem::size_of::<usize>();
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*(self.sp as *mut usize) = value;
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}
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pub unsafe fn pop_stack(&mut self) -> usize {
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let value = *(self.sp as *const usize);
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self.sp += 1 * mem::size_of::<usize>();
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value
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}
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#[cold]
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#[inline(never)]
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#[naked]
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pub unsafe fn switch_to(&mut self, next: &mut Context) {
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self.ttbr0_el1 = control_regs::ttbr0_el1() as usize;
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if next.ttbr0_el1 != self.ttbr0_el1 {
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control_regs::ttbr0_el1_write(next.ttbr0_el1 as u64);
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tlb::flush_all();
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}
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llvm_asm!("mov $0, x8" : "=r"(self.x8) : : "memory" : "volatile");
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llvm_asm!("mov x8, $0" : : "r"(next.x8) :"memory" : "volatile");
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llvm_asm!("mov $0, x9" : "=r"(self.x9) : : "memory" : "volatile");
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llvm_asm!("mov x9, $0" : : "r"(next.x9) :"memory" : "volatile");
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llvm_asm!("mov $0, x10" : "=r"(self.x10) : : "memory" : "volatile");
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llvm_asm!("mov x10, $0" : : "r"(next.x10) :"memory" : "volatile");
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llvm_asm!("mov $0, x11" : "=r"(self.x11) : : "memory" : "volatile");
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llvm_asm!("mov x11, $0" : : "r"(next.x11) :"memory" : "volatile");
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llvm_asm!("mov $0, x12" : "=r"(self.x12) : : "memory" : "volatile");
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llvm_asm!("mov x12, $0" : : "r"(next.x12) :"memory" : "volatile");
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llvm_asm!("mov $0, x13" : "=r"(self.x13) : : "memory" : "volatile");
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llvm_asm!("mov x13, $0" : : "r"(next.x13) :"memory" : "volatile");
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llvm_asm!("mov $0, x14" : "=r"(self.x14) : : "memory" : "volatile");
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llvm_asm!("mov x14, $0" : : "r"(next.x14) :"memory" : "volatile");
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llvm_asm!("mov $0, x15" : "=r"(self.x15) : : "memory" : "volatile");
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llvm_asm!("mov x15, $0" : : "r"(next.x15) :"memory" : "volatile");
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llvm_asm!("mov $0, x16" : "=r"(self.x16) : : "memory" : "volatile");
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llvm_asm!("mov x16, $0" : : "r"(next.x16) :"memory" : "volatile");
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llvm_asm!("mov $0, x17" : "=r"(self.x17) : : "memory" : "volatile");
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llvm_asm!("mov x17, $0" : : "r"(next.x17) :"memory" : "volatile");
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llvm_asm!("mov $0, x18" : "=r"(self.x18) : : "memory" : "volatile");
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llvm_asm!("mov x18, $0" : : "r"(next.x18) :"memory" : "volatile");
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llvm_asm!("mov $0, x19" : "=r"(self.x19) : : "memory" : "volatile");
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llvm_asm!("mov x19, $0" : : "r"(next.x19) :"memory" : "volatile");
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llvm_asm!("mov $0, x20" : "=r"(self.x20) : : "memory" : "volatile");
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llvm_asm!("mov x20, $0" : : "r"(next.x20) :"memory" : "volatile");
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llvm_asm!("mov $0, x21" : "=r"(self.x21) : : "memory" : "volatile");
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llvm_asm!("mov x21, $0" : : "r"(next.x21) :"memory" : "volatile");
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llvm_asm!("mov $0, x22" : "=r"(self.x22) : : "memory" : "volatile");
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llvm_asm!("mov x22, $0" : : "r"(next.x22) :"memory" : "volatile");
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llvm_asm!("mov $0, x23" : "=r"(self.x23) : : "memory" : "volatile");
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llvm_asm!("mov x23, $0" : : "r"(next.x23) :"memory" : "volatile");
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llvm_asm!("mov $0, x24" : "=r"(self.x24) : : "memory" : "volatile");
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llvm_asm!("mov x24, $0" : : "r"(next.x24) :"memory" : "volatile");
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llvm_asm!("mov $0, x25" : "=r"(self.x25) : : "memory" : "volatile");
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llvm_asm!("mov x25, $0" : : "r"(next.x25) :"memory" : "volatile");
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llvm_asm!("mov $0, x26" : "=r"(self.x26) : : "memory" : "volatile");
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llvm_asm!("mov x26, $0" : : "r"(next.x26) :"memory" : "volatile");
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llvm_asm!("mov $0, x27" : "=r"(self.x27) : : "memory" : "volatile");
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llvm_asm!("mov x27, $0" : : "r"(next.x27) :"memory" : "volatile");
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llvm_asm!("mov $0, x28" : "=r"(self.x28) : : "memory" : "volatile");
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llvm_asm!("mov x28, $0" : : "r"(next.x28) :"memory" : "volatile");
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llvm_asm!("mov $0, x29" : "=r"(self.fp) : : "memory" : "volatile");
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llvm_asm!("mov x29, $0" : : "r"(next.fp) :"memory" : "volatile");
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llvm_asm!("mov $0, x30" : "=r"(self.lr) : : "memory" : "volatile");
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llvm_asm!("mov x30, $0" : : "r"(next.lr) :"memory" : "volatile");
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llvm_asm!("mrs $0, elr_el1" : "=r"(self.elr_el1) : : "memory" : "volatile");
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llvm_asm!("msr elr_el1, $0" : : "r"(next.elr_el1) : "memory" : "volatile");
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llvm_asm!("mrs $0, sp_el0" : "=r"(self.sp_el0) : : "memory" : "volatile");
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llvm_asm!("msr sp_el0, $0" : : "r"(next.sp_el0) : "memory" : "volatile");
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llvm_asm!("mrs $0, tpidr_el0" : "=r"(self.tpidr_el0) : : "memory" : "volatile");
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llvm_asm!("msr tpidr_el0, $0" : : "r"(next.tpidr_el0) : "memory" : "volatile");
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llvm_asm!("mrs $0, tpidrro_el0" : "=r"(self.tpidrro_el0) : : "memory" : "volatile");
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llvm_asm!("msr tpidrro_el0, $0" : : "r"(next.tpidrro_el0) : "memory" : "volatile");
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llvm_asm!("mrs $0, spsr_el1" : "=r"(self.rflags) : : "memory" : "volatile");
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llvm_asm!("msr spsr_el1, $0" : : "r"(next.rflags) : "memory" : "volatile");
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llvm_asm!("mrs $0, esr_el1" : "=r"(self.esr_el1) : : "memory" : "volatile");
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llvm_asm!("msr esr_el1, $0" : : "r"(next.esr_el1) : "memory" : "volatile");
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llvm_asm!("mov $0, sp" : "=r"(self.sp) : : "memory" : "volatile");
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llvm_asm!("mov sp, $0" : : "r"(next.sp) : "memory" : "volatile");
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}
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}
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#[allow(dead_code)]
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#[repr(packed)]
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pub struct SignalHandlerStack {
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x28: usize, /* Callee saved Register */
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x27: usize, /* Callee saved Register */
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x26: usize, /* Callee saved Register */
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x25: usize, /* Callee saved Register */
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x24: usize, /* Callee saved Register */
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x23: usize, /* Callee saved Register */
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x22: usize, /* Callee saved Register */
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x21: usize, /* Callee saved Register */
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x20: usize, /* Callee saved Register */
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x19: usize, /* Callee saved Register */
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x18: usize,
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x17: usize,
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x16: usize,
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x15: usize, /* Temporary Register */
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x14: usize, /* Temporary Register */
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x13: usize, /* Temporary Register */
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x12: usize, /* Temporary Register */
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x11: usize, /* Temporary Register */
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x10: usize, /* Temporary Register */
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x9: usize, /* Temporary Register */
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x8: usize, /* Indirect location Register */
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x7: usize,
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x6: usize,
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x5: usize,
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x4: usize,
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x3: usize,
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x2: usize,
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x1: usize,
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x0: usize,
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lr: usize,
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handler: extern fn(usize),
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sig: usize,
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}
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#[naked]
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unsafe extern fn signal_handler_wrapper() {
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#[inline(never)]
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unsafe fn inner(stack: &SignalHandlerStack) {
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(stack.handler)(stack.sig);
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}
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// Push scratch registers
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llvm_asm!("str x0, [sp, #-8]!
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str x1, [sp, #-8]!
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str x2, [sp, #-8]!
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str x3, [sp, #-8]!
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str x4, [sp, #-8]!
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str x5, [sp, #-8]!
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str x6, [sp, #-8]!
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str x7, [sp, #-8]!
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str x8, [sp, #-8]!
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str x9, [sp, #-8]!
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str x10, [sp, #-8]!
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str x11, [sp, #-8]!
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str x12, [sp, #-8]!
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str x13, [sp, #-8]!
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str x14, [sp, #-8]!
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str x15, [sp, #-8]!
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str x16, [sp, #-8]!
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str x17, [sp, #-8]!
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str x18, [sp, #-8]!
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str x19, [sp, #-8]!
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str x20, [sp, #-8]!
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str x21, [sp, #-8]!
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str x22, [sp, #-8]!
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str x23, [sp, #-8]!
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str x24, [sp, #-8]!
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str x25, [sp, #-8]!
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str x26, [sp, #-8]!
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str x27, [sp, #-8]!
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str x28, [sp, #-8]!"
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: : : : "volatile");
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// Get reference to stack variables
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let sp: usize;
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llvm_asm!("" : "={sp}"(sp) : : : "volatile");
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let ptr = sp as *const SignalHandlerStack;
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let final_lr = (*ptr).lr;
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// Call inner rust function
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inner(&*(sp as *const SignalHandlerStack));
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// Pop scratch registers, error code, and return
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llvm_asm!("ldr x28, [sp], #8
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ldr x27, [sp], #8
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ldr x26, [sp], #8
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ldr x25, [sp], #8
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ldr x24, [sp], #8
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ldr x23, [sp], #8
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ldr x22, [sp], #8
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ldr x21, [sp], #8
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ldr x20, [sp], #8
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ldr x19, [sp], #8
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ldr x18, [sp], #8
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ldr x17, [sp], #8
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ldr x16, [sp], #8
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ldr x15, [sp], #8
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ldr x14, [sp], #8
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ldr x13, [sp], #8
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ldr x12, [sp], #8
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ldr x11, [sp], #8
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ldr x10, [sp], #8
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ldr x9, [sp], #8
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ldr x8, [sp], #8
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ldr x7, [sp], #8
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ldr x6, [sp], #8
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ldr x5, [sp], #8
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ldr x4, [sp], #8
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ldr x3, [sp], #8
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ldr x2, [sp], #8
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ldr x1, [sp], #8"
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: : : : "volatile");
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llvm_asm!("mov x30, $0" : : "r"(final_lr) : "memory" : "volatile");
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}
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@@ -10,6 +10,11 @@ pub use self::context::{Context, ContextId, ContextSnapshot, Status, WaitpidKey}
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pub use self::list::ContextList;
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pub use self::switch::switch;
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#[cfg(target_arch = "aarch64")]
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#[path = "arch/aarch64.rs"]
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mod arch;
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#[cfg(target_arch = "x86_64")]
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#[path = "arch/x86_64.rs"]
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mod arch;
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@@ -2,6 +2,7 @@ use core::sync::atomic::Ordering;
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use crate::context::signal::signal_handler;
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use crate::context::{arch, contexts, Context, Status, CONTEXT_ID};
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#[cfg(target_arch = "x86_64")]
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use crate::gdt;
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use crate::interrupt::irq::PIT_TICKS;
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use crate::interrupt;
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@@ -143,10 +144,13 @@ pub unsafe fn switch() -> bool {
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if to_ptr as usize != 0 {
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(*from_ptr).running = false;
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(*to_ptr).running = true;
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if let Some(ref stack) = (*to_ptr).kstack {
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gdt::set_tss_stack(stack.as_ptr() as usize + stack.len());
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#[cfg(target_arch = "x86_64")]
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{
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if let Some(ref stack) = (*to_ptr).kstack {
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gdt::set_tss_stack(stack.as_ptr() as usize + stack.len());
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}
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gdt::set_tcb((*to_ptr).id.into());
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}
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gdt::set_tcb((*to_ptr).id.into());
|
||||
CONTEXT_ID.store((*to_ptr).id, Ordering::SeqCst);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user